OV - exec - Function main._omp

	Function: main._omp_fn.3	Module: exec	Source: stream.c:290-292	Coverage (incl. loops): 0.93% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c: 290 - 292

--------------------------------------------------------------------------------

290: #pragma omp parallel for

291:     for (j = 0; j < STREAM_ARRAY_SIZE; j++)

292: 		a[j] = 2.0E0 * a[j];

0x401eb0 PUSH	%RBP

0x401eb1 MOV	$0x401060,%RAX

0x401ebb MOV	%RSP,%RBP

0x401ebe PUSH	%RBX

0x401ebf AND	$-0x20,%RSP

0x401ec3 CALL	%RAX

0x401ec5 MOVSXD	%EAX,%RBX

0x401ec8 MOV	$0x401030,%RAX

0x401ed2 CALL	%RAX

0x401ed4 MOVSXD	%EAX,%RCX

0x401ed7 MOV	$0x33450000,%EAX

0x401edc CQTO

0x401ede IDIV	%RBX

0x401ee1 CMP	%RDX,%RCX

0x401ee4 JL	4020f8

0x401eea IMUL	%RAX,%RCX

0x401eee ADD	%RCX,%RDX

0x401ef1 LEA	(%RAX,%RDX,1),%RSI

0x401ef5 CMP	%RSI,%RDX

0x401ef8 JGE	4020ed

0x401efe LEA	-0x1(%RAX),%RDI

0x401f02 MOV	%RDX,%R9

0x401f05 CMP	$0x2,%RDI

0x401f09 JBE	402108

0x401f0f MOV	%RAX,%RBX

0x401f12 MOV	$0x3349060e0,%R10

0x401f1c SHR	$0x2,%RBX

0x401f20 SAL	$0x5,%RBX

0x401f24 LEA	(%R10,%RDX,8),%R11

0x401f28 LEA	(%RBX,%R11,1),%R8

0x401f2c SUB	$0x20,%RBX

0x401f30 SHR	$0x5,%RBX

0x401f34 INC	%RBX

0x401f37 AND	$0x7,%EBX

0x401f3a JE	401ff9

0x401f40 CMP	$0x1,%RBX

0x401f44 JE	401fdc

0x401f4a CMP	$0x2,%RBX

0x401f4e JE	401fc8

0x401f50 CMP	$0x3,%RBX

0x401f54 JE	401fb4

0x401f56 CMP	$0x4,%RBX

0x401f5a JE	401fa1

0x401f5c CMP	$0x5,%RBX

0x401f60 JE	401f8e

0x401f62 CMP	$0x6,%RBX

0x401f66 JE	401f7b

0x401f68 VMOVUPD	(%R11),%YMM0

0x401f6d ADD	$0x20,%R11

0x401f71 VADDPD	%YMM0,%YMM0,%YMM1

0x401f75 VMOVUPD	%YMM1,-0x20(%R11)

0x401f7b VMOVUPD	(%R11),%YMM2

0x401f80 ADD	$0x20,%R11

0x401f84 VADDPD	%YMM2,%YMM2,%YMM3

0x401f88 VMOVUPD	%YMM3,-0x20(%R11)

0x401f8e VMOVUPD	(%R11),%YMM4

0x401f93 ADD	$0x20,%R11

0x401f97 VADDPD	%YMM4,%YMM4,%YMM5

0x401f9b VMOVUPD	%YMM5,-0x20(%R11)

0x401fa1 VMOVUPD	(%R11),%YMM6

0x401fa6 ADD	$0x20,%R11

0x401faa VADDPD	%YMM6,%YMM6,%YMM7

0x401fae VMOVUPD	%YMM7,-0x20(%R11)

0x401fb4 VMOVUPD	(%R11),%YMM8

0x401fb9 ADD	$0x20,%R11

0x401fbd VADDPD	%YMM8,%YMM8,%YMM9

0x401fc2 VMOVUPD	%YMM9,-0x20(%R11)

0x401fc8 VMOVUPD	(%R11),%YMM10

0x401fcd ADD	$0x20,%R11

0x401fd1 VADDPD	%YMM10,%YMM10,%YMM11

0x401fd6 VMOVUPD	%YMM11,-0x20(%R11)

0x401fdc VMOVUPD	(%R11),%YMM12

0x401fe1 ADD	$0x20,%R11

0x401fe5 VADDPD	%YMM12,%YMM12,%YMM13

0x401fea VMOVUPD	%YMM13,-0x20(%R11)

0x401ff0 CMP	%R8,%R11

0x401ff3 JE	4020a3

(4) 0x401ff9 VMOVUPD	(%R11),%YMM14

(4) 0x401ffe VMOVUPD	0x20(%R11),%YMM0

(4) 0x402004 VMOVUPD	0x40(%R11),%YMM2

(4) 0x40200a VMOVUPD	0x60(%R11),%YMM4

(4) 0x402010 VMOVUPD	0x80(%R11),%YMM6

(4) 0x402019 VMOVUPD	0xa0(%R11),%YMM8

(4) 0x402022 VMOVUPD	0xc0(%R11),%YMM10

(4) 0x40202b VMOVUPD	0xe0(%R11),%YMM12

(4) 0x402034 VADDPD	%YMM14,%YMM14,%YMM15

(4) 0x402039 VADDPD	%YMM0,%YMM0,%YMM1

(4) 0x40203d VADDPD	%YMM2,%YMM2,%YMM3

(4) 0x402041 VADDPD	%YMM4,%YMM4,%YMM5

(4) 0x402045 VADDPD	%YMM6,%YMM6,%YMM7

(4) 0x402049 VADDPD	%YMM8,%YMM8,%YMM9

(4) 0x40204e VADDPD	%YMM10,%YMM10,%YMM11

(4) 0x402053 VADDPD	%YMM12,%YMM12,%YMM13

(4) 0x402058 VMOVUPD	%YMM15,(%R11)

(4) 0x40205d VMOVUPD	%YMM1,0x20(%R11)

(4) 0x402063 VMOVUPD	%YMM3,0x40(%R11)

(4) 0x402069 VMOVUPD	%YMM5,0x60(%R11)

(4) 0x40206f VMOVUPD	%YMM7,0x80(%R11)

(4) 0x402078 VMOVUPD	%YMM9,0xa0(%R11)

(4) 0x402081 VMOVUPD	%YMM11,0xc0(%R11)

(4) 0x40208a VMOVUPD	%YMM13,0xe0(%R11)

(4) 0x402093 ADD	$0x100,%R11

(4) 0x40209a CMP	%R8,%R11

(4) 0x40209d JNE	401ff9

0x4020a3 MOV	%RAX,%RCX

0x4020a6 AND	$-0x4,%RCX

0x4020aa ADD	%RCX,%RDX

0x4020ad CMP	%RCX,%RAX

0x4020b0 JE	402120

0x4020b2 VZEROUPPER

0x4020b5 SUB	%RCX,%RAX

0x4020b8 CMP	$0x1,%RAX

0x4020bc JE	4020dd

0x4020be ADD	%R9,%RCX

0x4020c1 LEA	(%R10,%RCX,8),%RSI

0x4020c5 VMOVUPD	(%RSI),%XMM14

0x4020c9 VADDPD	%XMM14,%XMM14,%XMM15

0x4020ce VMOVUPD	%XMM15,(%RSI)

0x4020d2 TEST	$0x1,%AL

0x4020d4 JE	4020ed

0x4020d6 AND	$-0x2,%RAX

0x4020da ADD	%RAX,%RDX

0x4020dd VMOVSD	(%R10,%RDX,8),%XMM0

0x4020e3 VADDSD	%XMM0,%XMM0,%XMM1

0x4020e7 VMOVSD	%XMM1,(%R10,%RDX,8)

0x4020ed MOV	-0x8(%RBP),%RBX

0x4020f1 LEAVE

0x4020f2 RET

0x4020f3 NOPL	(%RAX,%RAX,1)

0x4020f8 INC	%RAX

0x4020fb XOR	%EDX,%EDX

0x4020fd JMP	401eea

0x402102 NOPW	(%RAX,%RAX,1)

0x402108 XOR	%ECX,%ECX

0x40210a MOV	$0x3349060e0,%R10

0x402114 JMP	4020b5

0x402116 NOPW	%CS:(%RAX,%RAX,1)

0x402120 VZEROUPPER

0x402123 MOV	-0x8(%RBP),%RBX

0x402127 LEAVE

0x402128 RET

0x402129 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○99.16	gomp_thread_start	team.c:130	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	stream.c:290-292
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:290-292.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.17 to 8.67 cycles (2.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 31% of vector register length is used (average across all SSE/AVX instructions).

Details

57% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

88% of SSE/AVX loads are used in vector version.
88% of SSE/AVX stores are used in vector version.
88% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
11% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:290
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:290

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:290
LEAVE: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:290
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:290
VZEROUPPER: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:290

Vector unaligned load/store instructions

Detected 14 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 14 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:290

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 7 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 31 FP arithmetical operations:

31: addition or subtraction

The binary function is loading 264 bytes (33 double precision FP elements). The binary function is storing 248 bytes (31 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	115
nb uops	127
loop length	470
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	14
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.17 cycles
front end	21.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.00	14.10	5.00	5.00	6.50	13.90	14.00	6.50	6.50	6.50	14.00	5.00
cycles	14.00	14.10	5.00	5.00	6.50	13.90	14.00	6.50	6.50	6.50	14.00	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	21.17
Dispatch	14.10
DIV/SQRT	10.00
Overall L1	21.17

Vectorization ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	88%
load	88%
store	88%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	88%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	57%
load	88%
store	88%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	88%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	43%
load	43%
store	43%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	43%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	31%
load	43%
store	43%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	43%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.17 cycles. At this rate:

6% of peak load performance is reached (12.47 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.72 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 21.17 to 14.10 cycles (1.50x speedup).

ASM code

In the binary file, the address of the function is: 401eb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x401060,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV $0x33450000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RBX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 4020f8 <main._omp_fn.3+0x248>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%RDX,1),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4020ed <main._omp_fn.3+0x23d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RAX),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP $0x2,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 402108 <main._omp_fn.3+0x258>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x3349060e0,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
SHR $0x2,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SAL $0x5,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%R10,%RDX,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%R11,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x20,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x5,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 401ff9 <main._omp_fn.3+0x149>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 401fdc <main._omp_fn.3+0x12c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 401fc8 <main._omp_fn.3+0x118>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 401fb4 <main._omp_fn.3+0x104>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 401fa1 <main._omp_fn.3+0xf1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 401f8e <main._omp_fn.3+0xde>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 401f7b <main._omp_fn.3+0xcb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD (%R11),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x20,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM0,%YMM0,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM1,-0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R11),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x20,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM2,%YMM2,%YMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM3,-0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R11),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x20,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM4,%YMM4,%YMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM5,-0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R11),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x20,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM6,%YMM6,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM7,-0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R11),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x20,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM8,%YMM8,%YMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM9,-0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R11),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x20,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM10,%YMM10,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM11,-0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R11),%YMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x20,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM12,%YMM12,%YMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM13,-0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
CMP %R8,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4020a3 <main._omp_fn.3+0x1f3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402120 <main._omp_fn.3+0x270>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
SUB %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $0x1,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4020dd <main._omp_fn.3+0x22d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R10,%RCX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD (%RSI),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VADDPD %XMM14,%XMM14,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM15,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4020ed <main._omp_fn.3+0x23d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
AND $-0x2,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R10,%RDX,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,(%R10,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEAVE	3	0.60	0.60	0.33	0.33	0	0.60	0.60	0	0	0	0.60	0.33	2-6	2	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 401eea <main._omp_fn.3+0x3a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x3349060e0,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
JMP 4020b5 <main._omp_fn.3+0x205>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV -0x8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEAVE	3	0.60	0.60	0.33	0.33	0	0.60	0.60	0	0	0	0.60	0.33	2-6	2	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	stream.c:290-292
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.17 to 8.67 cycles (2.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 31% of vector register length is used (average across all SSE/AVX instructions).

Details

57% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

88% of SSE/AVX loads are used in vector version.
88% of SSE/AVX stores are used in vector version.
88% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
11% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:290
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:290

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:290
LEAVE: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:290
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:290
VZEROUPPER: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:290

Vector unaligned load/store instructions

Detected 14 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 14 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:292

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-8011/stream-scale/build/stream-scale/src/stream.c:290

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 31 FP arithmetical operations:

31: addition or subtraction

The binary function is loading 264 bytes (33 double precision FP elements). The binary function is storing 248 bytes (31 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	115
nb uops	127
loop length	470
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	14
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.17 cycles
front end	21.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.00	14.10	5.00	5.00	6.50	13.90	14.00	6.50	6.50	6.50	14.00	5.00
cycles	14.00	14.10	5.00	5.00	6.50	13.90	14.00	6.50	6.50	6.50	14.00	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	21.17
Dispatch	14.10
DIV/SQRT	10.00
Overall L1	21.17

Vectorization ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	88%
load	88%
store	88%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	88%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	57%
load	88%
store	88%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	88%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	43%
load	43%
store	43%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	43%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	31%
load	43%
store	43%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	43%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.17 cycles. At this rate:

6% of peak load performance is reached (12.47 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.72 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 401eb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x401060,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV $0x33450000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RBX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 4020f8 <main._omp_fn.3+0x248>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%RDX,1),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4020ed <main._omp_fn.3+0x23d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RAX),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP $0x2,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 402108 <main._omp_fn.3+0x258>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x3349060e0,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
SHR $0x2,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SAL $0x5,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%R10,%RDX,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%R11,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x20,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x5,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 401ff9 <main._omp_fn.3+0x149>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 401fdc <main._omp_fn.3+0x12c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 401fc8 <main._omp_fn.3+0x118>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 401fb4 <main._omp_fn.3+0x104>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 401fa1 <main._omp_fn.3+0xf1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 401f8e <main._omp_fn.3+0xde>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 401f7b <main._omp_fn.3+0xcb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD (%R11),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x20,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM0,%YMM0,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM1,-0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R11),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x20,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM2,%YMM2,%YMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM3,-0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R11),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x20,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM4,%YMM4,%YMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM5,-0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R11),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x20,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM6,%YMM6,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM7,-0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R11),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x20,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM8,%YMM8,%YMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM9,-0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R11),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x20,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM10,%YMM10,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM11,-0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%R11),%YMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x20,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM12,%YMM12,%YMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM13,-0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
CMP %R8,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4020a3 <main._omp_fn.3+0x1f3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402120 <main._omp_fn.3+0x270>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
SUB %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $0x1,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4020dd <main._omp_fn.3+0x22d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R10,%RCX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD (%RSI),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VADDPD %XMM14,%XMM14,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM15,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4020ed <main._omp_fn.3+0x23d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
AND $-0x2,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R10,%RDX,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,(%R10,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEAVE	3	0.60	0.60	0.33	0.33	0	0.60	0.60	0	0	0	0.60	0.33	2-6	2	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 401eea <main._omp_fn.3+0x3a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x3349060e0,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
JMP 4020b5 <main._omp_fn.3+0x205>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV -0x8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEAVE	3	0.60	0.60	0.33	0.33	0	0.60	0.60	0	0	0	0.60	0.33	2-6	2	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼main._omp_fn.3–	0.93	0.03
○Loop 4 - stream.c:292-292 - exec	0.93	0.03

Report Configuration

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Execution units bottlenecks

512-bits vectorization

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CALL instructions

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Complex instructions

Details

Vector unaligned load/store instructions

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Conversion instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code