OV - exec - Function main.omp

	Function: main.omp_outlined.14	Module: exec	Source: stream.c:271-275	Coverage (incl. loops): 1.03% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c: 271 - 275

--------------------------------------------------------------------------------

271: #pragma omp parallel for

272:     for (j=0; j<STREAM_ARRAY_SIZE; j++) {

273: 	    a[j] = 1.0;

274: 	    b[j] = 2.0;

275: 	    c[j] = 0.0;

0x203010 PUSH	%RBP

0x203011 MOV	%RSP,%RBP

0x203014 PUSH	%R15

0x203016 PUSH	%R14

0x203018 PUSH	%R13

0x20301a PUSH	%R12

0x20301c PUSH	%RBX

0x20301d SUB	$0x28,%RSP

0x203021 MOVQ	$0,-0x40(%RBP)

0x203029 MOVQ	$0x3344ffff,-0x30(%RBP)

0x203031 LEA	0x33a8(%RIP),%RBX

0x203038 MOVQ	$0x1,-0x48(%RBP)

0x203040 MOVL	$0,-0x34(%RBP)

0x203047 MOV	(%RDI),%R14D

0x20304a SUB	$0x8,%RSP

0x20304e LEA	-0x48(%RBP),%RAX

0x203052 MOV	$0x10c0,%RDI

0x20305c ADD	%RBX,%RDI

0x20305f LEA	-0x34(%RBP),%RCX

0x203063 LEA	-0x40(%RBP),%R8

0x203067 LEA	-0x30(%RBP),%R9

0x20306b MOV	%R14D,%ESI

0x20306e MOV	$0x22,%EDX

0x203073 PUSH	$0x1

0x203075 PUSH	$0x1

0x203077 PUSH	%RAX

0x203078 CALL	2041d0 <@plt_start@+0x80>

0x20307d ADD	$0x20,%RSP

0x203081 MOV	-0x30(%RBP),%RAX

0x203085 CMP	$0x3344ffff,%RAX

0x20308b MOV	$0x3344ffff,%R15D

0x203091 CMOVL	%RAX,%R15

0x203095 MOV	%R15,-0x30(%RBP)

0x203099 MOV	-0x40(%RBP),%R13

0x20309d CMP	%R15,%R13

0x2030a0 JG	2031c2

0x2030a6 MOV	$0x3345011a0,%RAX

0x2030b0 ADD	%RBX,%RAX

0x2030b3 LEA	(%RAX,%R13,8),%RDI

0x2030b7 MOV	%R15,%R12

0x2030ba SUB	%R13,%R12

0x2030bd LEA	0x8(,%R12,8),%RDX

0x2030c5 INC	%R12

0x2030c8 XOR	%ESI,%ESI

0x2030ca CALL	2041e0 <@plt_start@+0x90>

0x2030cf MOV	$0x11a0,%RAX

0x2030d9 MOV	$0x19a2811a0,%RCX

0x2030e3 CMP	$0x10,%R12

0x2030e7 JAE	2030f1

0x2030e9 MOV	%R13,%RDX

0x2030ec JMP	203184

0x2030f1 MOV	%R12,%RSI

0x2030f4 AND	$-0x10,%RSI

0x2030f8 LEA	(%R13,%RSI,1),%RDX

0x2030fd LEA	(%RBX,%RAX,1),%RDI

0x203101 LEA	0x60(%RDI,%R13,8),%RDI

0x203106 LEA	(%RBX,%RCX,1),%R8

0x20310a LEA	0x60(%R8,%R13,8),%R8

0x20310f XOR	%R9D,%R9D

0x203112 MOV	$-0x5bb8,%R10

0x20311c VBROADCASTSD	(%RBX,%R10,1),%YMM0

0x203122 MOV	$-0x5be0,%R10

0x20312c VBROADCASTSD	(%RBX,%R10,1),%YMM1

0x203132 NOPW	%CS:(%RAX,%RAX,1)

(2) 0x203140 VMOVUPS	%YMM0,-0x60(%RDI,%R9,8)

(2) 0x203147 VMOVUPS	%YMM0,-0x40(%RDI,%R9,8)

(2) 0x20314e VMOVUPS	%YMM0,-0x20(%RDI,%R9,8)

(2) 0x203155 VMOVUPS	%YMM0,(%RDI,%R9,8)

(2) 0x20315b VMOVUPS	%YMM1,-0x60(%R8,%R9,8)

(2) 0x203162 VMOVUPS	%YMM1,-0x40(%R8,%R9,8)

(2) 0x203169 VMOVUPS	%YMM1,-0x20(%R8,%R9,8)

(2) 0x203170 VMOVUPS	%YMM1,(%R8,%R9,8)

(2) 0x203176 ADD	$0x10,%R9

(2) 0x20317a CMP	%R9,%RSI

(2) 0x20317d JNE	203140

0x20317f CMP	%RSI,%R12

0x203182 JE	2031c2

0x203184 DEC	%RDX

0x203187 ADD	%RBX,%RAX

0x20318a MOV	$0x3ff0000000000000,%RSI

0x203194 ADD	%RBX,%RCX

0x203197 MOV	$0x4000000000000000,%RDI

0x2031a1 NOPW	%CS:(%RAX,%RAX,1)

(3) 0x2031b0 MOV	%RSI,0x8(%RAX,%RDX,8)

(3) 0x2031b5 MOV	%RDI,0x8(%RCX,%RDX,8)

(3) 0x2031ba INC	%RDX

(3) 0x2031bd CMP	%R15,%RDX

(3) 0x2031c0 JL	2031b0

0x2031c2 MOV	$0x10d8,%RAX

0x2031cc ADD	%RAX,%RBX

0x2031cf MOV	%RBX,%RDI

0x2031d2 MOV	%R14D,%ESI

0x2031d5 VZEROUPPER

0x2031d8 CALL	2041f0 <@plt_start@+0xa0>

0x2031dd ADD	$0x28,%RSP

0x2031e1 POP	%RBX

0x2031e2 POP	%R12

0x2031e4 POP	%R13

0x2031e6 POP	%R14

0x2031e8 POP	%R15

0x2031ea POP	%RBP

0x2031eb RET

0x2031ec NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►98.98+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
►1.02+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	unknown kernel region	unknown kernel region	kernel

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	stream.c:271-275
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:271-275.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.17 to 1.83 cycles (8.27x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:275
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:271

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	87
nb uops	91
loop length	399
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.17 cycles
front end	15.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.90	5.80	4.00	4.00	8.50	5.80	5.70	8.50	8.50	8.50	5.80	4.00
cycles	5.90	6.40	4.00	4.00	8.50	5.80	5.70	8.50	8.50	8.50	5.80	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.17
Dispatch	8.50
Overall L1	15.17

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Vector efficiency ratios

INT

all	10%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.17 cycles. At this rate:

1% of peak load performance is reached (2.37 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.37 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.17 to 8.50 cycles (1.78x speedup).

ASM code

In the binary file, the address of the function is: 203010

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x33a8(%RIP),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%RDI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x10c0,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %RBX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x34(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x40(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 2041d0 <@plt_start@+0x80>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP $0x3344ffff,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $0x3344ffff,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVL %RAX,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x40(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R15,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JG 2031c2 <main.omp_outlined.14+0x1b2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x3345011a0,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%R13,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x8(,%R12,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2041e0 <@plt_start@+0x90>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x11a0,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x19a2811a0,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
CMP $0x10,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 2030f1 <main.omp_outlined.14+0xe1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 203184 <main.omp_outlined.14+0x174>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x10,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R13,%RSI,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RAX,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x60(%RDI,%R13,8),%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RBX,%RCX,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x60(%R8,%R13,8),%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $-0x5bb8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
VBROADCASTSD (%RBX,%R10,1),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
MOV $-0x5be0,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
VBROADCASTSD (%RBX,%R10,1),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 2031c2 <main.omp_outlined.14+0x1b2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x3ff0000000000000,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %RBX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x4000000000000000,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x10d8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %RAX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 2041f0 <@plt_start@+0xa0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	stream.c:271-275
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.17 to 1.83 cycles (8.27x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:275
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:271

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	87
nb uops	91
loop length	399
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.17 cycles
front end	15.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.90	5.80	4.00	4.00	8.50	5.80	5.70	8.50	8.50	8.50	5.80	4.00
cycles	5.90	6.40	4.00	4.00	8.50	5.80	5.70	8.50	8.50	8.50	5.80	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.17
Dispatch	8.50
Overall L1	15.17

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Vector efficiency ratios

INT

all	10%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.17 cycles. At this rate:

1% of peak load performance is reached (2.37 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.37 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 203010

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x33a8(%RIP),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%RDI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x10c0,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %RBX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x34(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x40(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 2041d0 <@plt_start@+0x80>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP $0x3344ffff,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $0x3344ffff,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVL %RAX,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x40(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R15,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JG 2031c2 <main.omp_outlined.14+0x1b2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x3345011a0,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%R13,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x8(,%R12,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2041e0 <@plt_start@+0x90>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x11a0,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x19a2811a0,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
CMP $0x10,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 2030f1 <main.omp_outlined.14+0xe1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 203184 <main.omp_outlined.14+0x174>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x10,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R13,%RSI,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RAX,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x60(%RDI,%R13,8),%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RBX,%RCX,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x60(%R8,%R13,8),%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $-0x5bb8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
VBROADCASTSD (%RBX,%R10,1),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
MOV $-0x5be0,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
VBROADCASTSD (%RBX,%R10,1),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 2031c2 <main.omp_outlined.14+0x1b2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x3ff0000000000000,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %RBX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x4000000000000000,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x10d8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %RAX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 2041f0 <@plt_start@+0xa0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼main.omp_outlined.14–	1.03	0.03
○Loop 2 - stream.c:273-274 - exec	1.03	0.03
○Loop 3 - stream.c:272-274 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code