OV - exec - Function main._omp

	Function: main._omp_fn.3	Module: exec	Source: stream.c:290-292	Coverage (incl. loops): 0.85% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c: 290 - 292

--------------------------------------------------------------------------------

290: #pragma omp parallel for

291:     for (j = 0; j < STREAM_ARRAY_SIZE; j++)

292: 		a[j] = 2.0E0 * a[j];

0x402390 PUSH	%RBP

0x402391 MOV	$0x401060,%RAX

0x40239b MOV	%RSP,%RBP

0x40239e PUSH	%RBX

0x40239f AND	$-0x40,%RSP

0x4023a3 CALL	%RAX

0x4023a5 MOVSXD	%EAX,%RBX

0x4023a8 MOV	$0x401030,%RAX

0x4023b2 CALL	%RAX

0x4023b4 MOVSXD	%EAX,%RCX

0x4023b7 MOV	$0x33450000,%EAX

0x4023bc CQTO

0x4023be IDIV	%RBX

0x4023c1 CMP	%RDX,%RCX

0x4023c4 JL	402640

0x4023ca IMUL	%RAX,%RCX

0x4023ce ADD	%RCX,%RDX

0x4023d1 LEA	(%RAX,%RDX,1),%R8

0x4023d5 CMP	%R8,%RDX

0x4023d8 JGE	402623

0x4023de LEA	-0x1(%RAX),%RSI

0x4023e2 MOV	%RDX,%R9

0x4023e5 CMP	$0x6,%RSI

0x4023e9 JBE	402650

0x4023ef MOV	%RAX,%RBX

0x4023f2 MOV	$0x334906100,%RDI

0x4023fc SHR	$0x3,%RBX

0x402400 SAL	$0x6,%RBX

0x402404 LEA	(%RDI,%RDX,8),%R11

0x402408 LEA	(%RBX,%R11,1),%RCX

0x40240c SUB	$0x40,%RBX

0x402410 SHR	$0x6,%RBX

0x402414 INC	%RBX

0x402417 AND	$0x7,%EBX

0x40241a JE	4024f6

0x402420 CMP	$0x1,%RBX

0x402424 JE	4024d6

0x40242a CMP	$0x2,%RBX

0x40242e JE	4024bf

0x402434 CMP	$0x3,%RBX

0x402438 JE	4024a8

0x40243a CMP	$0x4,%RBX

0x40243e JE	402491

0x402440 CMP	$0x5,%RBX

0x402444 JE	40247a

0x402446 CMP	$0x6,%RBX

0x40244a JE	402463

0x40244c VMOVUPD	(%R11),%ZMM0

0x402452 ADD	$0x40,%R11

0x402456 VADDPD	%ZMM0,%ZMM0,%ZMM1

0x40245c VMOVUPD	%ZMM1,-0x40(%R11)

0x402463 VMOVUPD	(%R11),%ZMM2

0x402469 ADD	$0x40,%R11

0x40246d VADDPD	%ZMM2,%ZMM2,%ZMM3

0x402473 VMOVUPD	%ZMM3,-0x40(%R11)

0x40247a VMOVUPD	(%R11),%ZMM4

0x402480 ADD	$0x40,%R11

0x402484 VADDPD	%ZMM4,%ZMM4,%ZMM5

0x40248a VMOVUPD	%ZMM5,-0x40(%R11)

0x402491 VMOVUPD	(%R11),%ZMM6

0x402497 ADD	$0x40,%R11

0x40249b VADDPD	%ZMM6,%ZMM6,%ZMM7

0x4024a1 VMOVUPD	%ZMM7,-0x40(%R11)

0x4024a8 VMOVUPD	(%R11),%ZMM8

0x4024ae ADD	$0x40,%R11

0x4024b2 VADDPD	%ZMM8,%ZMM8,%ZMM9

0x4024b8 VMOVUPD	%ZMM9,-0x40(%R11)

0x4024bf VMOVUPD	(%R11),%ZMM10

0x4024c5 ADD	$0x40,%R11

0x4024c9 VADDPD	%ZMM10,%ZMM10,%ZMM11

0x4024cf VMOVUPD	%ZMM11,-0x40(%R11)

0x4024d6 VMOVUPD	(%R11),%ZMM12

0x4024dc ADD	$0x40,%R11

0x4024e0 VADDPD	%ZMM12,%ZMM12,%ZMM13

0x4024e6 VMOVUPD	%ZMM13,-0x40(%R11)

0x4024ed CMP	%RCX,%R11

0x4024f0 JE	4025a4

(3) 0x4024f6 VMOVUPD	(%R11),%ZMM14

(3) 0x4024fc VMOVUPD	0x40(%R11),%ZMM0

(3) 0x402503 VMOVUPD	0x80(%R11),%ZMM2

(3) 0x40250a VMOVUPD	0xc0(%R11),%ZMM4

(3) 0x402511 VMOVUPD	0x100(%R11),%ZMM6

(3) 0x402518 VMOVUPD	0x140(%R11),%ZMM8

(3) 0x40251f VMOVUPD	0x180(%R11),%ZMM10

(3) 0x402526 VMOVUPD	0x1c0(%R11),%ZMM12

(3) 0x40252d VADDPD	%ZMM14,%ZMM14,%ZMM15

(3) 0x402533 VADDPD	%ZMM0,%ZMM0,%ZMM1

(3) 0x402539 VADDPD	%ZMM2,%ZMM2,%ZMM3

(3) 0x40253f VADDPD	%ZMM4,%ZMM4,%ZMM5

(3) 0x402545 VADDPD	%ZMM6,%ZMM6,%ZMM7

(3) 0x40254b VADDPD	%ZMM8,%ZMM8,%ZMM9

(3) 0x402551 VADDPD	%ZMM10,%ZMM10,%ZMM11

(3) 0x402557 VADDPD	%ZMM12,%ZMM12,%ZMM13

(3) 0x40255d VMOVUPD	%ZMM15,(%R11)

(3) 0x402563 VMOVUPD	%ZMM1,0x40(%R11)

(3) 0x40256a VMOVUPD	%ZMM3,0x80(%R11)

(3) 0x402571 VMOVUPD	%ZMM5,0xc0(%R11)

(3) 0x402578 VMOVUPD	%ZMM7,0x100(%R11)

(3) 0x40257f VMOVUPD	%ZMM9,0x140(%R11)

(3) 0x402586 VMOVUPD	%ZMM11,0x180(%R11)

(3) 0x40258d VMOVUPD	%ZMM13,0x1c0(%R11)

(3) 0x402594 ADD	$0x200,%R11

(3) 0x40259b CMP	%RCX,%R11

(3) 0x40259e JNE	4024f6

0x4025a4 MOV	%RAX,%R10

0x4025a7 AND	$-0x8,%R10

0x4025ab ADD	%R10,%RDX

0x4025ae CMP	%R10,%RAX

0x4025b1 JE	402630

0x4025b3 SUB	%R10,%RAX

0x4025b6 LEA	-0x1(%RAX),%RSI

0x4025ba CMP	$0x2,%RSI

0x4025be JBE	4025e4

0x4025c0 ADD	%R9,%R10

0x4025c3 LEA	(%RDI,%R10,8),%R9

0x4025c7 VMOVUPD	(%R9),%YMM14

0x4025cc MOV	%RAX,%R10

0x4025cf VADDPD	%YMM14,%YMM14,%YMM15

0x4025d4 AND	$-0x4,%R10

0x4025d8 ADD	%R10,%RDX

0x4025db VMOVUPD	%YMM15,(%R9)

0x4025e0 TEST	$0x3,%AL

0x4025e2 JE	402630

0x4025e4 VMOVSD	(%RDI,%RDX,8),%XMM0

0x4025e9 LEA	0x1(%RDX),%RAX

0x4025ed VADDSD	%XMM0,%XMM0,%XMM1

0x4025f1 VMOVSD	%XMM1,(%RDI,%RDX,8)

0x4025f6 CMP	%RAX,%R8

0x4025f9 JLE	402630

0x4025fb VMOVSD	(%RDI,%RAX,8),%XMM2

0x402600 ADD	$0x2,%RDX

0x402604 VADDSD	%XMM2,%XMM2,%XMM3

0x402608 VMOVSD	%XMM3,(%RDI,%RAX,8)

0x40260d CMP	%RDX,%R8

0x402610 JLE	402630

0x402612 VMOVSD	(%RDI,%RDX,8),%XMM4

0x402617 VADDSD	%XMM4,%XMM4,%XMM5

0x40261b VMOVSD	%XMM5,(%RDI,%RDX,8)

0x402620 VZEROUPPER

0x402623 MOV	-0x8(%RBP),%RBX

0x402627 LEAVE

0x402628 RET

0x402629 NOPL	(%RAX)

0x402630 VZEROUPPER

0x402633 MOV	-0x8(%RBP),%RBX

0x402637 LEAVE

0x402638 RET

0x402639 NOPL	(%RAX)

0x402640 INC	%RAX

0x402643 XOR	%EDX,%EDX

0x402645 JMP	4023ca

0x40264a NOPW	(%RAX,%RAX,1)

0x402650 XOR	%R10D,%R10D

0x402653 MOV	$0x334906100,%RDI

0x40265d JMP	4025b3

0x402662 NOPW	%CS:(%RAX,%RAX,1)

0x40266d NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○99.07	gomp_thread_start	team.c:130	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	stream.c:290-292
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:290-292.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.67 to 10.00 cycles (2.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 48% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 23.67 to 18.82 cycles (1.26x speedup).

Details

48% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

72% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
72% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
10% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:290
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:290

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:290
LEAVE: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:290
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:290
VZEROUPPER: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:290

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:290

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time). 7 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 63 FP arithmetical operations:

63: addition or subtraction

The binary function is loading 520 bytes (65 double precision FP elements). The binary function is storing 504 bytes (63 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	130
nb uops	142
loop length	562
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	2
used zmm registers	14
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.67 cycles
front end	23.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.20	15.30	5.67	5.67	7.50	15.10	15.20	7.50	7.50	7.50	15.20	5.67
cycles	15.20	15.30	5.67	5.67	7.50	15.10	15.20	7.50	7.50	7.50	15.20	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	23.67
Dispatch	15.30
DIV/SQRT	10.00
Overall L1	23.67

Vectorization ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	72%
load	72%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	72%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	48%
load	72%
store	72%
mul	0%
add-sub	72%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	71%
load	71%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	48%
load	71%
store	71%
mul	12%
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.67 cycles. At this rate:

11% of peak load performance is reached (21.97 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (21.30 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 23.67 to 15.30 cycles (1.55x speedup).

ASM code

In the binary file, the address of the function is: 402390

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x401060,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV $0x33450000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RBX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 402640 <main._omp_fn.3+0x2b0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%RDX,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 402623 <main._omp_fn.3+0x293>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 402650 <main._omp_fn.3+0x2c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x334906100,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
SHR $0x3,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SAL $0x6,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RDI,%RDX,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%R11,1),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x40,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x6,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4024f6 <main._omp_fn.3+0x166>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4024d6 <main._omp_fn.3+0x146>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4024bf <main._omp_fn.3+0x12f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4024a8 <main._omp_fn.3+0x118>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402491 <main._omp_fn.3+0x101>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40247a <main._omp_fn.3+0xea>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402463 <main._omp_fn.3+0xd3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD (%R11),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
ADD $0x40,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %ZMM0,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM1,-0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R11),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
ADD $0x40,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %ZMM2,%ZMM2,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM3,-0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R11),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
ADD $0x40,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %ZMM4,%ZMM4,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM5,-0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R11),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
ADD $0x40,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %ZMM6,%ZMM6,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM7,-0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R11),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
ADD $0x40,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %ZMM8,%ZMM8,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM9,-0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R11),%ZMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
ADD $0x40,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %ZMM10,%ZMM10,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM11,-0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R11),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
ADD $0x40,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %ZMM12,%ZMM12,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM13,-0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
CMP %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4025a4 <main._omp_fn.3+0x214>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %R10,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402630 <main._omp_fn.3+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x2,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 4025e4 <main._omp_fn.3+0x254>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R9,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RDI,%R10,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD (%R9),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM14,%YMM14,%YMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
AND $-0x4,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %R10,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD %YMM15,(%R9)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
TEST $0x3,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 402630 <main._omp_fn.3+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RDI,%RDX,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSD %XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,(%RDI,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 402630 <main._omp_fn.3+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RDI,%RAX,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x2,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDSD %XMM2,%XMM2,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM3,(%RDI,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 402630 <main._omp_fn.3+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RDI,%RDX,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM4,%XMM4,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%RDI,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV -0x8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEAVE	3	0.60	0.60	0.33	0.33	0	0.60	0.60	0	0	0	0.60	0.33	2-6	2	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV -0x8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEAVE	3	0.60	0.60	0.33	0.33	0	0.60	0.60	0	0	0	0.60	0.33	2-6	2	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4023ca <main._omp_fn.3+0x3a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x334906100,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
JMP 4025b3 <main._omp_fn.3+0x223>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	stream.c:290-292
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

48% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

72% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
72% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
10% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:290
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:290

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:290
LEAVE: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:290
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:290
VZEROUPPER: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:290

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:290

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 63 FP arithmetical operations:

63: addition or subtraction

The binary function is loading 520 bytes (65 double precision FP elements). The binary function is storing 504 bytes (63 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	130
nb uops	142
loop length	562
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	2
used zmm registers	14
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.67 cycles
front end	23.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.20	15.30	5.67	5.67	7.50	15.10	15.20	7.50	7.50	7.50	15.20	5.67
cycles	15.20	15.30	5.67	5.67	7.50	15.10	15.20	7.50	7.50	7.50	15.20	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	23.67
Dispatch	15.30
DIV/SQRT	10.00
Overall L1	23.67

Vectorization ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	72%
load	72%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	72%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	48%
load	72%
store	72%
mul	0%
add-sub	72%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	71%
load	71%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	48%
load	71%
store	71%
mul	12%
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.67 cycles. At this rate:

11% of peak load performance is reached (21.97 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (21.30 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402390

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x401060,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV $0x33450000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RBX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 402640 <main._omp_fn.3+0x2b0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%RDX,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 402623 <main._omp_fn.3+0x293>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 402650 <main._omp_fn.3+0x2c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x334906100,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
SHR $0x3,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SAL $0x6,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RDI,%RDX,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%R11,1),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x40,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x6,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4024f6 <main._omp_fn.3+0x166>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4024d6 <main._omp_fn.3+0x146>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4024bf <main._omp_fn.3+0x12f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4024a8 <main._omp_fn.3+0x118>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402491 <main._omp_fn.3+0x101>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40247a <main._omp_fn.3+0xea>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402463 <main._omp_fn.3+0xd3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD (%R11),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
ADD $0x40,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %ZMM0,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM1,-0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R11),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
ADD $0x40,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %ZMM2,%ZMM2,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM3,-0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R11),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
ADD $0x40,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %ZMM4,%ZMM4,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM5,-0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R11),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
ADD $0x40,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %ZMM6,%ZMM6,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM7,-0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R11),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
ADD $0x40,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %ZMM8,%ZMM8,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM9,-0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R11),%ZMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
ADD $0x40,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %ZMM10,%ZMM10,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM11,-0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R11),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
ADD $0x40,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %ZMM12,%ZMM12,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM13,-0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
CMP %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4025a4 <main._omp_fn.3+0x214>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %R10,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402630 <main._omp_fn.3+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x2,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 4025e4 <main._omp_fn.3+0x254>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R9,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RDI,%R10,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD (%R9),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDPD %YMM14,%YMM14,%YMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
AND $-0x4,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %R10,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD %YMM15,(%R9)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
TEST $0x3,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 402630 <main._omp_fn.3+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RDI,%RDX,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSD %XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,(%RDI,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 402630 <main._omp_fn.3+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RDI,%RAX,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x2,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDSD %XMM2,%XMM2,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM3,(%RDI,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 402630 <main._omp_fn.3+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RDI,%RDX,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM4,%XMM4,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%RDI,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV -0x8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEAVE	3	0.60	0.60	0.33	0.33	0	0.60	0.60	0	0	0	0.60	0.33	2-6	2	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV -0x8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEAVE	3	0.60	0.60	0.33	0.33	0	0.60	0.60	0	0	0	0.60	0.33	2-6	2	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4023ca <main._omp_fn.3+0x3a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x334906100,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
JMP 4025b3 <main._omp_fn.3+0x223>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼main._omp_fn.3–	0.85	0.03
○Loop 3 - stream.c:292-292 - exec	0.85	0.03

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Complex instructions

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Vector unaligned load/store instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

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