OV - exec - Loop 4

	Loop Id: 4	Module: exec	Source: stream.c:292-292	Coverage: 0.92%

0x401fb9 VMOVUPD	(%R11),%YMM14    [1]

0x401fbe VMOVUPD	0x20(%R11),%YMM0    [1]

0x401fc4 VMOVUPD	0x40(%R11),%YMM2    [1]

0x401fca VMOVUPD	0x60(%R11),%YMM4    [1]

0x401fd0 VMOVUPD	0x80(%R11),%YMM6    [1]

0x401fd9 VMOVUPD	0xa0(%R11),%YMM8    [1]

0x401fe2 VMOVUPD	0xc0(%R11),%YMM10    [1]

0x401feb VMOVUPD	0xe0(%R11),%YMM12    [1]

0x401ff4 VADDPD	%YMM14,%YMM14,%YMM15

0x401ff9 VADDPD	%YMM0,%YMM0,%YMM1

0x401ffd VADDPD	%YMM2,%YMM2,%YMM3

0x402001 VADDPD	%YMM4,%YMM4,%YMM5

0x402005 VADDPD	%YMM6,%YMM6,%YMM7

0x402009 VADDPD	%YMM8,%YMM8,%YMM9

0x40200e VADDPD	%YMM10,%YMM10,%YMM11

0x402013 VADDPD	%YMM12,%YMM12,%YMM13

0x402018 VMOVUPD	%YMM15,(%R11)    [1]

0x40201d VMOVUPD	%YMM1,0x20(%R11)    [1]

0x402023 VMOVUPD	%YMM3,0x40(%R11)    [1]

0x402029 VMOVUPD	%YMM5,0x60(%R11)    [1]

0x40202f VMOVUPD	%YMM7,0x80(%R11)    [1]

0x402038 VMOVUPD	%YMM9,0xa0(%R11)    [1]

0x402041 VMOVUPD	%YMM11,0xc0(%R11)    [1]

0x40204a VMOVUPD	%YMM13,0xe0(%R11)    [1]

0x402053 ADD	$0x100,%R11

0x40205a CMP	%R8,%R11

0x40205d JNE	401fb9

/beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c: 292 - 292

--------------------------------------------------------------------------------

292: 		a[j] = 2.0E0 * a[j];

Coverage (%)	Name	Source Location	Module
○99.15	gomp_thread_start	team.c:130	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.08
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	micro-operation queue,
Function	main._omp_fn.3
Source	stream.c:292-292
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.33
CQA cycles if no scalar integer	4.33
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	2.17
Front-end cycles	4.33
P0 cycles	0.70
P1 cycles	4.00
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	4.00
P5 cycles	4.00
P6 cycles	0.70
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.60
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	26.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	7.38
Nb FLOP add-sub	32.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	118.15
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.08
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	micro-operation queue,
Function	main._omp_fn.3
Source	stream.c:292-292
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.33
CQA cycles if no scalar integer	4.33
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	2.17
Front-end cycles	4.33
P0 cycles	0.70
P1 cycles	4.00
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	4.00
P5 cycles	4.00
P6 cycles	0.70
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.60
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	26.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	7.38
Nb FLOP add-sub	32.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	118.15
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.3
Source file and lines	stream.c:292-292
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Vector unaligned load/store instructions

Detected 16 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 16 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

8 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

32: addition or subtraction

The binary loop is loading 256 bytes (32 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	27
nb uops	26
loop length	170
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	16
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	0.70	4.00	2.67	2.67	4.00	4.00	0.70	4.00	4.00	4.00	0.60	2.67
cycles	0.70	4.00	2.67	2.67	4.00	4.00	0.70	4.00	4.00	4.00	0.60	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.33
Dispatch	4.00
Data deps.	1.00
Overall L1	4.33

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.33 cycles. At this rate:

30% of peak load performance is reached (59.08 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
46% of peak store performance is reached (59.08 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.33 to 4.00 cycles (1.08x speedup).

ASM code

In the binary file, the address of the loop is: 401fb9

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%R11),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R11),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%R11),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%R11),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x80(%R11),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0xa0(%R11),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0xc0(%R11),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0xe0(%R11),%YMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM14,%YMM14,%YMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM0,%YMM0,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM2,%YMM2,%YMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM4,%YMM4,%YMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM6,%YMM6,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM8,%YMM8,%YMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM10,%YMM10,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM12,%YMM12,%YMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM15,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM1,0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM3,0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM5,0x60(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM7,0x80(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM9,0xa0(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM11,0xc0(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM13,0xe0(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x100,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R8,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 401fb9 <main._omp_fn.3+0x149>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main._omp_fn.3
Source file and lines	stream.c:292-292
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Vector unaligned load/store instructions

Detected 16 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 16 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix04.benchmarkcenter.megware.com/177-373-7189/stream-copy/build/stream-copy/src/stream.c:292

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

8 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

32: addition or subtraction

The binary loop is loading 256 bytes (32 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	27
nb uops	26
loop length	170
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	16
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	0.70	4.00	2.67	2.67	4.00	4.00	0.70	4.00	4.00	4.00	0.60	2.67
cycles	0.70	4.00	2.67	2.67	4.00	4.00	0.70	4.00	4.00	4.00	0.60	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.33
Dispatch	4.00
Data deps.	1.00
Overall L1	4.33

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.33 cycles. At this rate:

30% of peak load performance is reached (59.08 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
46% of peak store performance is reached (59.08 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 401fb9

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%R11),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R11),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%R11),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x60(%R11),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x80(%R11),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0xa0(%R11),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0xc0(%R11),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0xe0(%R11),%YMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPD %YMM14,%YMM14,%YMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM0,%YMM0,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM2,%YMM2,%YMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM4,%YMM4,%YMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM6,%YMM6,%YMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM8,%YMM8,%YMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM10,%YMM10,%YMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM12,%YMM12,%YMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM15,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM1,0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM3,0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM5,0x60(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM7,0x80(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM9,0xa0(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM11,0xc0(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM13,0xe0(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x100,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R8,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 401fb9 <main._omp_fn.3+0x149>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code