OV - exec - Loop 11

	Loop Id: 11	Module: exec	Source: stream.c:476-479	Coverage: 0.51%

0x403850 VMOVAPD	(%RSI,%RBX,1),%ZMM12    [3]

0x403857 VMOVAPD	(%R9,%RBX,1),%ZMM15    [1]

0x40385e VSUBPD	%ZMM11,%ZMM12,%ZMM13

0x403864 VSUBPD	%ZMM10,%ZMM15,%ZMM2

0x40386a VANDPD	%ZMM4,%ZMM13,%ZMM14

0x403870 VANDPD	%ZMM4,%ZMM2,%ZMM12

0x403876 VMOVAPD	(%R10,%RBX,1),%ZMM13    [2]

0x40387d VMOVAPD	0x40(%RSI,%RBX,1),%ZMM2    [3]

0x403885 VADDPD	%ZMM14,%ZMM0,%ZMM0

0x40388b VADDPD	%ZMM12,%ZMM1,%ZMM1

0x403891 VSUBPD	%ZMM9,%ZMM13,%ZMM14

0x403897 VSUBPD	%ZMM11,%ZMM2,%ZMM12

0x40389d VANDPD	%ZMM4,%ZMM14,%ZMM15

0x4038a3 VANDPD	%ZMM4,%ZMM12,%ZMM13

0x4038a9 VMOVAPD	0x40(%R9,%RBX,1),%ZMM14    [1]

0x4038b1 VMOVAPD	0x40(%R10,%RBX,1),%ZMM12    [2]

0x4038b9 VADDPD	%ZMM15,%ZMM3,%ZMM3

0x4038bf VADDPD	%ZMM13,%ZMM0,%ZMM0

0x4038c5 VSUBPD	%ZMM10,%ZMM14,%ZMM15

0x4038cb VSUBPD	%ZMM9,%ZMM12,%ZMM13

0x4038d1 VANDPD	%ZMM4,%ZMM15,%ZMM2

0x4038d7 VANDPD	%ZMM4,%ZMM13,%ZMM14

0x4038dd VMOVAPD	0x80(%RSI,%RBX,1),%ZMM15    [3]

0x4038e5 VMOVAPD	0x80(%R9,%RBX,1),%ZMM13    [1]

0x4038ed VADDPD	%ZMM2,%ZMM1,%ZMM1

0x4038f3 VADDPD	%ZMM14,%ZMM3,%ZMM3

0x4038f9 VSUBPD	%ZMM11,%ZMM15,%ZMM2

0x4038ff VSUBPD	%ZMM10,%ZMM13,%ZMM14

0x403905 VANDPD	%ZMM4,%ZMM2,%ZMM12

0x40390b VANDPD	%ZMM4,%ZMM14,%ZMM15

0x403911 VMOVAPD	0x80(%R10,%RBX,1),%ZMM2    [2]

0x403919 VMOVAPD	0xc0(%RSI,%RBX,1),%ZMM14    [3]

0x403921 VADDPD	%ZMM12,%ZMM0,%ZMM0

0x403927 VADDPD	%ZMM15,%ZMM1,%ZMM1

0x40392d VSUBPD	%ZMM9,%ZMM2,%ZMM12

0x403933 VSUBPD	%ZMM11,%ZMM14,%ZMM15

0x403939 VANDPD	%ZMM4,%ZMM12,%ZMM13

0x40393f VANDPD	%ZMM4,%ZMM15,%ZMM2

0x403945 VMOVAPD	0xc0(%R9,%RBX,1),%ZMM12    [1]

0x40394d VMOVAPD	0xc0(%R10,%RBX,1),%ZMM15    [2]

0x403955 VADDPD	%ZMM13,%ZMM3,%ZMM3

0x40395b VADDPD	%ZMM2,%ZMM0,%ZMM0

0x403961 VSUBPD	%ZMM10,%ZMM12,%ZMM13

0x403967 VSUBPD	%ZMM9,%ZMM15,%ZMM2

0x40396d ADD	$0x100,%RBX

0x403974 VANDPD	%ZMM4,%ZMM13,%ZMM14

0x40397a VANDPD	%ZMM4,%ZMM2,%ZMM12

0x403980 VADDPD	%ZMM14,%ZMM1,%ZMM1

0x403986 VADDPD	%ZMM12,%ZMM3,%ZMM3

0x40398c CMP	%R8,%RBX

0x40398f JNE	403850

/beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c: 476 - 479

--------------------------------------------------------------------------------

476: 	for (j=0; j<STREAM_ARRAY_SIZE; j++) {

477: 		aSumErr += abs(a[j] - aj);

478: 		bSumErr += abs(b[j] - bj);

479: 		cSumErr += abs(c[j] - cj);

Coverage (%)	Name	Source Location	Module
►63.02+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P0, P5,
Function	checkSTREAMresults
Source	stream.c:476-479
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.00
CQA cycles if no scalar integer	18.00
CQA cycles if FP arith vectorized	18.00
CQA cycles if fully vectorized	18.00
Front-end cycles	8.33
P0 cycles	18.00
P1 cycles	12.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	0.00
P5 cycles	18.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.40
P11 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	12
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	50.00
Nb loads	12.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	10.67
Nb FLOP add-sub	192.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.67
Bytes prefetched	0.00
Bytes loaded	768.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P0, P5,
Function	checkSTREAMresults
Source	stream.c:476-479
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.00
CQA cycles if no scalar integer	18.00
CQA cycles if FP arith vectorized	18.00
CQA cycles if fully vectorized	18.00
Front-end cycles	8.33
P0 cycles	18.00
P1 cycles	12.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	0.00
P5 cycles	18.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.40
P11 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	12
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	50.00
Nb loads	12.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	10.67
Nb FLOP add-sub	192.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.67
Bytes prefetched	0.00
Bytes loaded	768.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	checkSTREAMresults
Source file and lines	stream.c:476-479
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c:476-479.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 18.00 to 12.00 cycles (1.50x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Type of elements and instruction set

24 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

192: addition or subtraction

The binary loop is loading 768 bytes (96 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	51
nb uops	50
loop length	325
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	12
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	18.00	0.60	4.00	4.00	0.00	18.00	1.00	0.00	0.00	0.00	0.40	4.00
cycles	18.00	12.00	4.00	4.00	0.00	18.00	1.00	0.00	0.00	0.00	0.40	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	12.00

Cycles summary

Front-end	8.33
Dispatch	18.00
Data deps.	12.00
Overall L1	18.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

22% of peak load performance is reached (42.67 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 403850

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VMOVAPD (%RSI,%RBX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVAPD (%R9,%RBX,1),%ZMM15	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD %ZMM11,%ZMM12,%ZMM13	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM15,%ZMM2	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM13,%ZMM14	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM2,%ZMM12	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VMOVAPD (%R10,%RBX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVAPD 0x40(%RSI,%RBX,1),%ZMM2	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM0,%ZMM0	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM12,%ZMM1,%ZMM1	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM9,%ZMM13,%ZMM14	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM11,%ZMM2,%ZMM12	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM14,%ZMM15	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM12,%ZMM13	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VMOVAPD 0x40(%R9,%RBX,1),%ZMM14	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVAPD 0x40(%R10,%RBX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM15,%ZMM3,%ZMM3	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM0,%ZMM0	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM14,%ZMM15	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM9,%ZMM12,%ZMM13	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM15,%ZMM2	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM13,%ZMM14	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VMOVAPD 0x80(%RSI,%RBX,1),%ZMM15	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVAPD 0x80(%R9,%RBX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM1,%ZMM1	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM3,%ZMM3	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM11,%ZMM15,%ZMM2	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM13,%ZMM14	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM2,%ZMM12	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM14,%ZMM15	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VMOVAPD 0x80(%R10,%RBX,1),%ZMM2	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVAPD 0xc0(%RSI,%RBX,1),%ZMM14	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM12,%ZMM0,%ZMM0	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM15,%ZMM1,%ZMM1	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM9,%ZMM2,%ZMM12	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM11,%ZMM14,%ZMM15	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM12,%ZMM13	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM15,%ZMM2	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VMOVAPD 0xc0(%R9,%RBX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVAPD 0xc0(%R10,%RBX,1),%ZMM15	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM3,%ZMM3	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM0,%ZMM0	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM12,%ZMM13	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM9,%ZMM15,%ZMM2	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
ADD $0x100,%RBX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VANDPD %ZMM4,%ZMM13,%ZMM14	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM2,%ZMM12	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM1,%ZMM1	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM12,%ZMM3,%ZMM3	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
CMP %R8,%RBX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 403850 <checkSTREAMresults+0x140>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	checkSTREAMresults
Source file and lines	stream.c:476-479
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Type of elements and instruction set

24 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

192: addition or subtraction

The binary loop is loading 768 bytes (96 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	51
nb uops	50
loop length	325
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	12
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	18.00	0.60	4.00	4.00	0.00	18.00	1.00	0.00	0.00	0.00	0.40	4.00
cycles	18.00	12.00	4.00	4.00	0.00	18.00	1.00	0.00	0.00	0.00	0.40	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	12.00

Cycles summary

Front-end	8.33
Dispatch	18.00
Data deps.	12.00
Overall L1	18.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

22% of peak load performance is reached (42.67 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 403850

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VMOVAPD (%RSI,%RBX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVAPD (%R9,%RBX,1),%ZMM15	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPD %ZMM11,%ZMM12,%ZMM13	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM15,%ZMM2	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM13,%ZMM14	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM2,%ZMM12	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VMOVAPD (%R10,%RBX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVAPD 0x40(%RSI,%RBX,1),%ZMM2	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM0,%ZMM0	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM12,%ZMM1,%ZMM1	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM9,%ZMM13,%ZMM14	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM11,%ZMM2,%ZMM12	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM14,%ZMM15	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM12,%ZMM13	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VMOVAPD 0x40(%R9,%RBX,1),%ZMM14	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVAPD 0x40(%R10,%RBX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM15,%ZMM3,%ZMM3	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM0,%ZMM0	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM14,%ZMM15	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM9,%ZMM12,%ZMM13	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM15,%ZMM2	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM13,%ZMM14	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VMOVAPD 0x80(%RSI,%RBX,1),%ZMM15	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVAPD 0x80(%R9,%RBX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM1,%ZMM1	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM3,%ZMM3	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM11,%ZMM15,%ZMM2	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM13,%ZMM14	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM2,%ZMM12	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM14,%ZMM15	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VMOVAPD 0x80(%R10,%RBX,1),%ZMM2	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVAPD 0xc0(%RSI,%RBX,1),%ZMM14	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM12,%ZMM0,%ZMM0	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM15,%ZMM1,%ZMM1	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM9,%ZMM2,%ZMM12	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM11,%ZMM14,%ZMM15	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM12,%ZMM13	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM15,%ZMM2	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VMOVAPD 0xc0(%R9,%RBX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVAPD 0xc0(%R10,%RBX,1),%ZMM15	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM3,%ZMM3	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM0,%ZMM0	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM12,%ZMM13	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM9,%ZMM15,%ZMM2	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
ADD $0x100,%RBX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VANDPD %ZMM4,%ZMM13,%ZMM14	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM4,%ZMM2,%ZMM12	1	0.50	0	0	0	0.50	0	0	0	1	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM1,%ZMM1	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM12,%ZMM3,%ZMM3	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
CMP %R8,%RBX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 403850 <checkSTREAMresults+0x140>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

▶Scalability Runs Description

Run 1x6	Number processes: 1Number nodes: NANumber processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/run/oneview_runs/multicore/gcc_2/oneview_run_1773739244OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threadsOMP_NUM_THREADS: 6
Run 1x96	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/run/oneview_runs/multicore/gcc_2/oneview_run_1773739244OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x120	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/run/oneview_runs/multicore/gcc_2/oneview_run_1773739244OMP_NUM_THREADS: 120OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x126	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/run/oneview_runs/multicore/gcc_2/oneview_run_1773739244OMP_NUM_THREADS: 126OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x144	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/run/oneview_runs/multicore/gcc_2/oneview_run_1773739244OMP_NUM_THREADS: 144OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x168	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/run/oneview_runs/multicore/gcc_2/oneview_run_1773739244OMP_NUM_THREADS: 168OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x192	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/run/oneview_runs/multicore/gcc_2/oneview_run_1773739244OMP_NUM_THREADS: 192OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x216	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/run/oneview_runs/multicore/gcc_2/oneview_run_1773739244OMP_NUM_THREADS: 216OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x240	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/run/oneview_runs/multicore/gcc_2/oneview_run_1773739244OMP_NUM_THREADS: 240OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x256	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/run/oneview_runs/multicore/gcc_2/oneview_run_1773739244OMP_NUM_THREADS: 256OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x6) Efficiency	(1x6) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)	(1x120) Efficiency	(1x120) Potential Speed-Up (%)	(1x126) Efficiency	(1x126) Potential Speed-Up (%)	(1x144) Efficiency	(1x144) Potential Speed-Up (%)	(1x168) Efficiency	(1x168) Potential Speed-Up (%)	(1x192) Efficiency	(1x192) Potential Speed-Up (%)	(1x216) Efficiency	(1x216) Potential Speed-Up (%)	(1x240) Efficiency	(1x240) Potential Speed-Up (%)	(1x256) Efficiency	(1x256) Potential Speed-Up (%)
1	0	0.88	0.03	0.85	0.03	0.84	0.03	0.86	0.02	0.85	0.02	0.9	0.01	0.84	0.02	0.88	0.01	0.85	0.01

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x6	1	1	1	1	2.0549993515015	0.51307642459869
1x96	1	0.88	14.04	16	1.7899993658066	0.21015916764736
1x120	1	0.85	16.98	20	1.8649997711182	0.20410279929638
1x126	1	0.84	17.62	21	1.8500000238419	0.2002305239439
1x144	1	0.86	20.53	24	1.8750001192093	0.16248182952404
1x168	1	0.85	23.84	28	1.8150000572205	0.14964504539967
1x192	1	0.9	28.93	32	1.8499995470047	0.11427403241396
1x216	1	0.84	30.09	36	2.1600000858307	0.12479091435671
1x240	1	0.88	35.2	40	2.0849995613098	0.11522100865841
1x256	1	0.85	36.29	42.666666666667	1.8149998188019	0.098681777715683

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency