OV - exec - Function main.omp

	Function: main.omp_outlined.31	Module: exec	Source: stream.c:342-344	Coverage (incl. loops): 28.63% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c: 342 - 344

--------------------------------------------------------------------------------

342: #pragma omp parallel for

343: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

344: 	    c[j] = a[j]+b[j];

0x203bb0 PUSH	%RBP

0x203bb1 MOV	%RSP,%RBP

0x203bb4 PUSH	%R15

0x203bb6 PUSH	%R14

0x203bb8 PUSH	%R13

0x203bba PUSH	%R12

0x203bbc PUSH	%RBX

0x203bbd SUB	$0x28,%RSP

0x203bc1 MOVQ	$0,-0x40(%RBP)

0x203bc9 MOVQ	$0x3344ffff,-0x30(%RBP)

0x203bd1 LEA	0x3458(%RIP),%RBX

0x203bd8 MOVQ	$0x1,-0x48(%RBP)

0x203be0 MOVL	$0,-0x34(%RBP)

0x203be7 MOV	(%RDI),%R14D

0x203bea SUB	$0x8,%RSP

0x203bee LEA	-0x48(%RBP),%RAX

0x203bf2 MOV	$0x11e0,%RDI

0x203bfc ADD	%RBX,%RDI

0x203bff LEA	-0x34(%RBP),%RCX

0x203c03 LEA	-0x40(%RBP),%R8

0x203c07 LEA	-0x30(%RBP),%R9

0x203c0b MOV	%R14D,%ESI

0x203c0e MOV	$0x22,%EDX

0x203c13 PUSH	$0x1

0x203c15 PUSH	$0x1

0x203c17 PUSH	%RAX

0x203c18 CALL	204e20 <@plt_start@+0x80>

0x203c1d ADD	$0x20,%RSP

0x203c21 MOV	-0x30(%RBP),%RCX

0x203c25 CMP	$0x3344ffff,%RCX

0x203c2c MOV	$0x3344ffff,%EAX

0x203c31 CMOVL	%RCX,%RAX

0x203c35 MOV	%RAX,-0x30(%RBP)

0x203c39 MOV	-0x40(%RBP),%R8

0x203c3d CMP	%RAX,%R8

0x203c40 JG	203dad

0x203c46 MOV	%RAX,%RDI

0x203c49 SUB	%R8,%RDI

0x203c4c INC	%RDI

0x203c4f MOV	$0x1270,%RCX

0x203c59 MOV	$0x19a281270,%RDX

0x203c63 MOV	$0x334501270,%RSI

0x203c6d CMP	$0x4,%RDI

0x203c71 JAE	203c7b

0x203c73 MOV	%R8,%R10

0x203c76 JMP	203d80

0x203c7b CMP	$0x20,%RDI

0x203c7f JAE	203c89

0x203c81 XOR	%R9D,%R9D

0x203c84 JMP	203d39

0x203c89 MOV	%RDI,%R9

0x203c8c AND	$-0x20,%R9

0x203c90 LEA	(%RBX,%RCX,1),%R10

0x203c94 LEA	0xc0(%R10,%R8,8),%R10

0x203c9c LEA	(%RBX,%RDX,1),%R11

0x203ca0 LEA	0xc0(%R11,%R8,8),%R11

0x203ca8 LEA	(%RBX,%RSI,1),%R15

0x203cac LEA	0xc0(%R15,%R8,8),%R15

0x203cb4 XOR	%R12D,%R12D

0x203cb7 NOPW	(%RAX,%RAX,1)

(11) 0x203cc0 VMOVUPD	-0xc0(%R11,%R12,8),%ZMM0

(11) 0x203cc8 VMOVUPD	-0x80(%R11,%R12,8),%ZMM1

(11) 0x203cd0 VMOVUPD	-0x40(%R11,%R12,8),%ZMM2

(11) 0x203cd8 VMOVUPD	(%R11,%R12,8),%ZMM3

(11) 0x203cdf VADDPD	-0xc0(%R10,%R12,8),%ZMM0,%ZMM0

(11) 0x203ce7 VADDPD	-0x80(%R10,%R12,8),%ZMM1,%ZMM1

(11) 0x203cef VADDPD	-0x40(%R10,%R12,8),%ZMM2,%ZMM2

(11) 0x203cf7 VADDPD	(%R10,%R12,8),%ZMM3,%ZMM3

(11) 0x203cfe VMOVUPD	%ZMM0,-0xc0(%R15,%R12,8)

(11) 0x203d06 VMOVUPD	%ZMM1,-0x80(%R15,%R12,8)

(11) 0x203d0e VMOVUPD	%ZMM2,-0x40(%R15,%R12,8)

(11) 0x203d16 VMOVUPD	%ZMM3,(%R15,%R12,8)

(11) 0x203d1d ADD	$0x20,%R12

(11) 0x203d21 CMP	%R12,%R9

(11) 0x203d24 JNE	203cc0

0x203d26 CMP	%R9,%RDI

0x203d29 JE	203dad

0x203d2f TEST	$0x1c,%DIL

0x203d33 JE	203dd7

0x203d39 MOV	%RDI,%R11

0x203d3c AND	$-0x4,%R11

0x203d40 LEA	(%R8,%R11,1),%R10

0x203d44 LEA	(%RBX,%RCX,1),%R15

0x203d48 LEA	(%R15,%R8,8),%R15

0x203d4c LEA	(%RBX,%RDX,1),%R12

0x203d50 LEA	(%R12,%R8,8),%R12

0x203d54 LEA	(%RBX,%RSI,1),%R13

0x203d58 LEA	(%R13,%R8,8),%R8

0x203d5d NOPL	(%RAX)

(13) 0x203d60 VMOVUPD	(%R12,%R9,8),%YMM0

(13) 0x203d66 VADDPD	(%R15,%R9,8),%YMM0,%YMM0

(13) 0x203d6c VMOVUPD	%YMM0,(%R8,%R9,8)

(13) 0x203d72 ADD	$0x4,%R9

(13) 0x203d76 CMP	%R9,%R11

(13) 0x203d79 JNE	203d60

0x203d7b CMP	%R11,%RDI

0x203d7e JE	203dad

0x203d80 DEC	%R10

0x203d83 ADD	%RBX,%RCX

0x203d86 ADD	%RBX,%RDX

0x203d89 ADD	%RBX,%RSI

0x203d8c NOPL	(%RAX)

(12) 0x203d90 VMOVSD	0x8(%RDX,%R10,8),%XMM0

(12) 0x203d97 VADDSD	0x8(%RCX,%R10,8),%XMM0,%XMM0

(12) 0x203d9e VMOVSD	%XMM0,0x8(%RSI,%R10,8)

(12) 0x203da5 INC	%R10

(12) 0x203da8 CMP	%RAX,%R10

(12) 0x203dab JL	203d90

0x203dad MOV	$0x11f8,%RAX

0x203db7 ADD	%RAX,%RBX

0x203dba MOV	%RBX,%RDI

0x203dbd MOV	%R14D,%ESI

0x203dc0 VZEROUPPER

0x203dc3 CALL	204e40 <@plt_start@+0xa0>

0x203dc8 ADD	$0x28,%RSP

0x203dcc POP	%RBX

0x203dcd POP	%R12

0x203dcf POP	%R13

0x203dd1 POP	%R14

0x203dd3 POP	%R15

0x203dd5 POP	%RBP

0x203dd6 RET

0x203dd7 ADD	%R9,%R8

0x203dda JMP	203c73

0x203ddf NOP

Coverage (%)	Name	Source Location	Module
►99.67+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_7

Source file and lines	stream.c:342-344
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c:342-344.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 16.83 to 1.20 cycles (14.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c:342

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c:342

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	98
nb uops	101
loop length	402
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.83 cycles
front end	16.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.80	6.80	3.33	3.33	8.00	6.80	6.80	8.00	8.00	8.00	6.80	3.33
cycles	6.80	7.60	3.33	3.33	8.00	6.80	6.80	8.00	8.00	8.00	6.80	3.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.83
Dispatch	8.00
Overall L1	16.83

Vectorization ratios

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

all	11%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.83 cycles. At this rate:

0% of peak load performance is reached (1.19 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.83 to 8.00 cycles (2.10x speedup).

ASM code

In the binary file, the address of the function is: 203bb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x3458(%RIP),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%RDI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x11e0,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %RBX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x34(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x40(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 204e20 <@plt_start@+0x80>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP $0x3344ffff,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $0x3344ffff,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMOVL %RCX,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x40(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JG 203dad <main.omp_outlined.31+0x1fd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x1270,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x19a281270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x334501270,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
CMP $0x4,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 203c7b <main.omp_outlined.31+0xcb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 203d80 <main.omp_outlined.31+0x1d0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP $0x20,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 203c89 <main.omp_outlined.31+0xd9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 203d39 <main.omp_outlined.31+0x189>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x20,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RBX,%RCX,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xc0(%R10,%R8,8),%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RBX,%RDX,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xc0(%R11,%R8,8),%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RBX,%RSI,1),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xc0(%R15,%R8,8),%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R9,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 203dad <main.omp_outlined.31+0x1fd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x1c,%DIL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 203dd7 <main.omp_outlined.31+0x227>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R8,%R11,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RCX,1),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R15,%R8,8),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RDX,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R12,%R8,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RSI,1),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R13,%R8,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R11,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 203dad <main.omp_outlined.31+0x1fd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RBX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RBX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RBX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x11f8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %RAX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 204e40 <@plt_start@+0xa0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
ADD %R9,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 203c73 <main.omp_outlined.31+0xc3>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_7

Source file and lines	stream.c:342-344
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c:342

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c:342

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	98
nb uops	101
loop length	402
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.83 cycles
front end	16.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.80	6.80	3.33	3.33	8.00	6.80	6.80	8.00	8.00	8.00	6.80	3.33
cycles	6.80	7.60	3.33	3.33	8.00	6.80	6.80	8.00	8.00	8.00	6.80	3.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.83
Dispatch	8.00
Overall L1	16.83

Vectorization ratios

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

all	11%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.83 cycles. At this rate:

0% of peak load performance is reached (1.19 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 203bb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x3458(%RIP),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%RDI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x11e0,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %RBX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x34(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x40(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 204e20 <@plt_start@+0x80>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP $0x3344ffff,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $0x3344ffff,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMOVL %RCX,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x40(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JG 203dad <main.omp_outlined.31+0x1fd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x1270,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x19a281270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x334501270,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
CMP $0x4,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 203c7b <main.omp_outlined.31+0xcb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 203d80 <main.omp_outlined.31+0x1d0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP $0x20,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 203c89 <main.omp_outlined.31+0xd9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 203d39 <main.omp_outlined.31+0x189>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x20,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RBX,%RCX,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xc0(%R10,%R8,8),%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RBX,%RDX,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xc0(%R11,%R8,8),%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RBX,%RSI,1),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xc0(%R15,%R8,8),%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R9,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 203dad <main.omp_outlined.31+0x1fd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x1c,%DIL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 203dd7 <main.omp_outlined.31+0x227>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R8,%R11,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RCX,1),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R15,%R8,8),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RDX,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R12,%R8,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RSI,1),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R13,%R8,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R11,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 203dad <main.omp_outlined.31+0x1fd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RBX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RBX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RBX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x11f8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %RAX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 204e40 <@plt_start@+0xa0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
ADD %R9,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 203c73 <main.omp_outlined.31+0xc3>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼main.omp_outlined.31–	28.63	4.63
○Loop 11 - stream.c:344-344 - exec	28.63	4.19
○Loop 12 - stream.c:343-344 - exec	0.00	0.00
○Loop 13 - stream.c:344-344 - exec	0.00	0.00

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Vectorization

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Matching between your function (in the source code) and the binary function

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Vectorization

Details

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Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code