OV - exec - Function main.extracted.40

	Function: main.extracted.40	Module: exec	Source: stream.c:271-276	Coverage (incl. loops): 0.43% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c: 271 - 276

--------------------------------------------------------------------------------

271: #pragma omp parallel for

272:     for (j=0; j<STREAM_ARRAY_SIZE; j++) {

273: 	    a[j] = 1.0;

274: 	    b[j] = 2.0;

275: 	    c[j] = 0.0;

276: 	}

0x402b20 PUSH	%RBP

0x402b21 MOV	%RSP,%RBP

0x402b24 PUSH	%R15

0x402b26 PUSH	%R14

0x402b28 PUSH	%RBX

0x402b29 SUB	$0x28,%RSP

0x402b2d MOVL	$0,-0x1c(%RBP)

0x402b34 MOV	(%RDI),%EBX

0x402b36 MOVQ	$0,-0x30(%RBP)

0x402b3e MOVQ	$0x3344ffff,-0x28(%RBP)

0x402b46 MOVQ	$0x1,-0x38(%RBP)

0x402b4e SUB	$0x8,%RSP

0x402b52 LEA	-0x38(%RBP),%RAX

0x402b56 MOV	$0x4ceb89060,%RDI

0x402b60 MOV	$0x401050,%R10

0x402b6a LEA	-0x1c(%RBP),%RCX

0x402b6e LEA	-0x30(%RBP),%R8

0x402b72 LEA	-0x28(%RBP),%R9

0x402b76 MOV	%EBX,%ESI

0x402b78 MOV	$0x22,%EDX

0x402b7d PUSH	$0x1

0x402b7f PUSH	$0x1

0x402b81 PUSH	%RAX

0x402b82 CALL	%R10

0x402b85 ADD	$0x20,%RSP

0x402b89 MOV	-0x30(%RBP),%RAX

0x402b8d MOV	-0x28(%RBP),%R10

0x402b91 CMP	%R10,%RAX

0x402b94 JA	402c8e

0x402b9a SUB	%RAX,%R10

0x402b9d INC	%R10

0x402ba0 MOV	%R10,%R8

0x402ba3 MOV	$0x406060,%RCX

0x402bad MOV	$0x404048,%R9

0x402bb7 MOV	$0x19a686060,%RDX

0x402bc1 MOV	$0x404068,%RDI

0x402bcb MOV	$0x334906060,%RSI

0x402bd5 AND	$0x7ffffff8,%R8

0x402bdc JE	402c40

0x402bde LEA	(,%RAX,8),%R11

0x402be6 XOR	%R14D,%R14D

0x402be9 VBROADCASTSD	(%R9),%ZMM0

0x402bef VBROADCASTSD	(%RDI),%ZMM1

0x402bf5 VXORPS	%XMM2,%XMM2,%XMM2

0x402bf9 NOPL	(%RAX)

(12) 0x402c00 LEA	(%R11,%R14,8),%R15

(12) 0x402c04 VMOVUPD	%ZMM0,(%RCX,%R15,1)

(12) 0x402c0b VMOVUPD	%ZMM1,(%RDX,%R15,1)

(12) 0x402c12 VMOVUPS	%ZMM2,(%RSI,%R15,1)

(12) 0x402c19 ADD	$0x8,%R14

(12) 0x402c1d CMP	%R8,%R14

(12) 0x402c20 JB	402c00

0x402c22 CMP	%R8,%R10

0x402c25 JE	402c8e

0x402c27 VPBROADCASTQ	%R10,%ZMM0

0x402c2d JMP	402c49

0x402c2f NOPW	%CS:(%RAX,%RAX,1)

0x402c3e XCHG	%AX,%AX

0x402c40 VPBROADCASTQ	%R10,%ZMM0

0x402c46 XOR	%R8D,%R8D

0x402c49 VPBROADCASTQ	%R8,%ZMM1

0x402c4f VPSUBQ	%ZMM1,%ZMM0,%ZMM0

0x402c55 VBROADCASTSD	(%R9),%ZMM1

0x402c5b MOV	$0x404100,%R9

0x402c65 ADD	%R8,%RAX

0x402c68 VPCMPNLEUQ	(%R9),%ZMM0,%K1

0x402c6f VMOVUPD	%ZMM1,(%RCX,%RAX,8){%K1}

0x402c76 VBROADCASTSD	(%RDI),%ZMM0

0x402c7c VMOVUPD	%ZMM0,(%RDX,%RAX,8){%K1}

0x402c83 VXORPD	%XMM0,%XMM0,%XMM0

0x402c87 VMOVUPD	%ZMM0,(%RSI,%RAX,8){%K1}

0x402c8e MOV	$0x4ceb89080,%RDI

0x402c98 MOV	$0x401030,%RAX

0x402ca2 MOV	%EBX,%ESI

0x402ca4 ADD	$0x28,%RSP

0x402ca8 POP	%RBX

0x402ca9 POP	%R14

0x402cab POP	%R15

0x402cad POP	%RBP

0x402cae VZEROUPPER

0x402cb1 JMP	%RAX

0x402cb3 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_2

Source file and lines	stream.c:271-276
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c:271-276.

Warnings:
get_cqa_results:

Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.67 to 3.67 cycles (3.45x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 26% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 12.67 to 9.83 cycles (1.29x speedup).

Details

26% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

14% of SSE/AVX loads are used in vector version.
42% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
22% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c:271

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 116 bytes. The binary function is storing 220 bytes.

General properties

nb instructions	75
nb uops	76
loop length	382
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	2
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.67 cycles
front end	12.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.00	5.00	3.67	3.67	7.50	5.00	5.00	7.50	7.50	7.50	5.00	3.67
cycles	5.00	5.00	3.67	3.67	7.50	5.00	5.00	7.50	7.50	7.50	5.00	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.67
Dispatch	7.50
Overall L1	12.67

Vectorization ratios

INT

all	14%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	55%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

INT+FP

all	26%
load	14%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Vector efficiency ratios

INT

all	19%
load	39%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	44%
load	12%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	26%
load	24%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 12.67 cycles. At this rate:

4% of peak load performance is reached (9.16 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (17.37 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.67 to 7.50 cycles (1.69x speedup).

ASM code

In the binary file, the address of the function is: 402b20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x1c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x28(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4ceb89060,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x401050,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
LEA -0x1c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x28(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x28(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 402c8e <main.extracted.40+0x16e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
INC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x406060,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x404048,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x19a686060,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x404068,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x334906060,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
AND $0x7ffffff8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
JE 402c40 <main.extracted.40+0x120>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RAX,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VBROADCASTSD (%R9),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD (%RDI),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402c8e <main.extracted.40+0x16e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTQ %R10,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
JMP 402c49 <main.extracted.40+0x129>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %R10,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VPBROADCASTQ %R8,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VBROADCASTSD (%R9),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
MOV $0x404100,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VPCMPNLEUQ (%R9),%ZMM0,%K1																vect (100.0%)
VMOVUPD %ZMM1,(%RCX,%RAX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VBROADCASTSD (%RDI),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMOVUPD %ZMM0,(%RDX,%RAX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVUPD %ZMM0,(%RSI,%RAX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
MOV $0x4ceb89080,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x401030,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	1.75	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_2

Source file and lines	stream.c:271-276
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c:271-276.

Warnings:
get_cqa_results:

Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.67 to 3.67 cycles (3.45x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

26% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

14% of SSE/AVX loads are used in vector version.
42% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
22% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix02.benchmarkcenter.megware.com/177-373-7005/stream/build/stream/src/stream.c:271

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 116 bytes. The binary function is storing 220 bytes.

General properties

nb instructions	75
nb uops	76
loop length	382
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	2
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.67 cycles
front end	12.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.00	5.00	3.67	3.67	7.50	5.00	5.00	7.50	7.50	7.50	5.00	3.67
cycles	5.00	5.00	3.67	3.67	7.50	5.00	5.00	7.50	7.50	7.50	5.00	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.67
Dispatch	7.50
Overall L1	12.67

Vectorization ratios

INT

all	14%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	55%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

INT+FP

all	26%
load	14%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Vector efficiency ratios

INT

all	19%
load	39%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	44%
load	12%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	26%
load	24%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 12.67 cycles. At this rate:

4% of peak load performance is reached (9.16 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (17.37 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402b20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x1c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x28(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4ceb89060,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x401050,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
LEA -0x1c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x28(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x28(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 402c8e <main.extracted.40+0x16e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
INC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x406060,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x404048,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x19a686060,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x404068,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x334906060,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
AND $0x7ffffff8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
JE 402c40 <main.extracted.40+0x120>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RAX,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VBROADCASTSD (%R9),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSD (%RDI),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402c8e <main.extracted.40+0x16e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTQ %R10,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
JMP 402c49 <main.extracted.40+0x129>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %R10,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VPBROADCASTQ %R8,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VBROADCASTSD (%R9),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
MOV $0x404100,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VPCMPNLEUQ (%R9),%ZMM0,%K1																vect (100.0%)
VMOVUPD %ZMM1,(%RCX,%RAX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VBROADCASTSD (%RDI),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMOVUPD %ZMM0,(%RDX,%RAX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVUPD %ZMM0,(%RSI,%RAX,8){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
MOV $0x4ceb89080,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x401030,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	1.75	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.40–	0.43	0.07
○Loop 12 - stream.c:272-276 - exec	0.43	0.06

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code