OV - exec - Function main._omp

	Function: main._omp_fn.4	Module: exec	Source: stream.c:342-344	Coverage (incl. loops): 95.61% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c: 342 - 344

--------------------------------------------------------------------------------

342: #pragma omp parallel for

343: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

344: 	    c[j] = a[j]+b[j];

0x4020e0 PUSH	%RBP

0x4020e1 MOV	$0x401060,%RAX

0x4020eb MOV	%RSP,%RBP

0x4020ee PUSH	%R14

0x4020f0 PUSH	%R13

0x4020f2 PUSH	%R12

0x4020f4 MOV	$0x401030,%R12

0x4020fe PUSH	%RBX

0x4020ff AND	$-0x40,%RSP

0x402103 CALL	%RAX

0x402105 MOVSXD	%EAX,%RBX

0x402108 CALL	%R12

0x40210b MOVSXD	%EAX,%RCX

0x40210e MOV	$0x33450000,%EAX

0x402113 CQTO

0x402115 IDIV	%RBX

0x402118 CMP	%RDX,%RCX

0x40211b JL	402400

0x402121 IMUL	%RAX,%RCX

0x402125 ADD	%RCX,%RDX

0x402128 LEA	(%RAX,%RDX,1),%R11

0x40212c CMP	%R11,%RDX

0x40212f JGE	4023da

0x402135 LEA	-0x1(%RAX),%RSI

0x402139 MOV	%RDX,%R14

0x40213c CMP	$0x6,%RSI

0x402140 JBE	402410

0x402146 MOV	%RAX,%R10

0x402149 SHR	$0x3,%R10

0x40214d SAL	$0x6,%R10

0x402151 LEA	-0x40(%R10),%R9

0x402155 SHR	$0x6,%R9

0x402159 LEA	(,%RDX,8),%RSI

0x402161 MOV	$0x334906100,%RBX

0x40216b MOV	$0x19a686100,%R12

0x402175 MOV	$0x406100,%R13

0x40217f INC	%R9

0x402182 LEA	(%RBX,%RSI,1),%RDI

0x402186 LEA	(%R12,%RSI,1),%R8

0x40218a XOR	%ECX,%ECX

0x40218c ADD	%R13,%RSI

0x40218f AND	$0x7,%R9D

0x402193 JE	40227b

0x402199 CMP	$0x1,%R9

0x40219d JE	402259

0x4021a3 CMP	$0x2,%R9

0x4021a7 JE	402240

0x4021ad CMP	$0x3,%R9

0x4021b1 JE	402227

0x4021b3 CMP	$0x4,%R9

0x4021b7 JE	40220e

0x4021b9 CMP	$0x5,%R9

0x4021bd JE	4021f5

0x4021bf CMP	$0x6,%R9

0x4021c3 JE	4021dc

0x4021c5 VMOVUPD	(%R8),%ZMM0

0x4021cb MOV	$0x40,%ECX

0x4021d0 VADDPD	(%RDI),%ZMM0,%ZMM1

0x4021d6 VMOVUPD	%ZMM1,(%RSI)

0x4021dc VMOVUPD	(%R8,%RCX,1),%ZMM2

0x4021e3 VADDPD	(%RDI,%RCX,1),%ZMM2,%ZMM3

0x4021ea VMOVUPD	%ZMM3,(%RSI,%RCX,1)

0x4021f1 ADD	$0x40,%RCX

0x4021f5 VMOVUPD	(%R8,%RCX,1),%ZMM4

0x4021fc VADDPD	(%RDI,%RCX,1),%ZMM4,%ZMM5

0x402203 VMOVUPD	%ZMM5,(%RSI,%RCX,1)

0x40220a ADD	$0x40,%RCX

0x40220e VMOVUPD	(%R8,%RCX,1),%ZMM6

0x402215 VADDPD	(%RDI,%RCX,1),%ZMM6,%ZMM7

0x40221c VMOVUPD	%ZMM7,(%RSI,%RCX,1)

0x402223 ADD	$0x40,%RCX

0x402227 VMOVUPD	(%R8,%RCX,1),%ZMM8

0x40222e VADDPD	(%RDI,%RCX,1),%ZMM8,%ZMM9

0x402235 VMOVUPD	%ZMM9,(%RSI,%RCX,1)

0x40223c ADD	$0x40,%RCX

0x402240 VMOVUPD	(%R8,%RCX,1),%ZMM10

0x402247 VADDPD	(%RDI,%RCX,1),%ZMM10,%ZMM11

0x40224e VMOVUPD	%ZMM11,(%RSI,%RCX,1)

0x402255 ADD	$0x40,%RCX

0x402259 VMOVUPD	(%R8,%RCX,1),%ZMM12

0x402260 VADDPD	(%RDI,%RCX,1),%ZMM12,%ZMM13

0x402267 VMOVUPD	%ZMM13,(%RSI,%RCX,1)

0x40226e ADD	$0x40,%RCX

0x402272 CMP	%R10,%RCX

0x402275 JE	402348

(2) 0x40227b VMOVUPD	(%R8,%RCX,1),%ZMM14

(2) 0x402282 VADDPD	(%RDI,%RCX,1),%ZMM14,%ZMM15

(2) 0x402289 VMOVUPD	%ZMM15,(%RSI,%RCX,1)

(2) 0x402290 VMOVUPD	0x40(%R8,%RCX,1),%ZMM0

(2) 0x402298 VADDPD	0x40(%RDI,%RCX,1),%ZMM0,%ZMM1

(2) 0x4022a0 VMOVUPD	%ZMM1,0x40(%RSI,%RCX,1)

(2) 0x4022a8 VMOVUPD	0x80(%R8,%RCX,1),%ZMM2

(2) 0x4022b0 VADDPD	0x80(%RDI,%RCX,1),%ZMM2,%ZMM3

(2) 0x4022b8 VMOVUPD	%ZMM3,0x80(%RSI,%RCX,1)

(2) 0x4022c0 VMOVUPD	0xc0(%R8,%RCX,1),%ZMM4

(2) 0x4022c8 VADDPD	0xc0(%RDI,%RCX,1),%ZMM4,%ZMM5

(2) 0x4022d0 VMOVUPD	%ZMM5,0xc0(%RSI,%RCX,1)

(2) 0x4022d8 VMOVUPD	0x100(%R8,%RCX,1),%ZMM6

(2) 0x4022e0 VADDPD	0x100(%RDI,%RCX,1),%ZMM6,%ZMM7

(2) 0x4022e8 VMOVUPD	%ZMM7,0x100(%RSI,%RCX,1)

(2) 0x4022f0 VMOVUPD	0x140(%R8,%RCX,1),%ZMM8

(2) 0x4022f8 VADDPD	0x140(%RDI,%RCX,1),%ZMM8,%ZMM9

(2) 0x402300 VMOVUPD	%ZMM9,0x140(%RSI,%RCX,1)

(2) 0x402308 VMOVUPD	0x180(%R8,%RCX,1),%ZMM10

(2) 0x402310 VADDPD	0x180(%RDI,%RCX,1),%ZMM10,%ZMM11

(2) 0x402318 VMOVUPD	%ZMM11,0x180(%RSI,%RCX,1)

(2) 0x402320 VMOVUPD	0x1c0(%R8,%RCX,1),%ZMM12

(2) 0x402328 VADDPD	0x1c0(%RDI,%RCX,1),%ZMM12,%ZMM13

(2) 0x402330 VMOVUPD	%ZMM13,0x1c0(%RSI,%RCX,1)

(2) 0x402338 ADD	$0x200,%RCX

(2) 0x40233f CMP	%R10,%RCX

(2) 0x402342 JNE	40227b

0x402348 MOV	%RAX,%RDI

0x40234b AND	$-0x8,%RDI

0x40234f ADD	%RDI,%RDX

0x402352 CMP	%RDI,%RAX

0x402355 JE	4023f0

0x40235b SUB	%RDI,%RAX

0x40235e LEA	-0x1(%RAX),%RSI

0x402362 CMP	$0x2,%RSI

0x402366 JBE	40238f

0x402368 ADD	%R14,%RDI

0x40236b SAL	$0x3,%RDI

0x40236f VMOVUPD	(%R12,%RDI,1),%YMM14

0x402375 MOV	%RAX,%R14

0x402378 VADDPD	(%RBX,%RDI,1),%YMM14,%YMM15

0x40237d AND	$-0x4,%R14

0x402381 ADD	%R14,%RDX

0x402384 VMOVUPD	%YMM15,(%R13,%RDI,1)

0x40238b TEST	$0x3,%AL

0x40238d JE	4023f0

0x40238f VMOVSD	(%RBX,%RDX,8),%XMM0

0x402394 LEA	0x1(%RDX),%RAX

0x402398 VADDSD	(%R12,%RDX,8),%XMM0,%XMM1

0x40239e VMOVSD	%XMM1,(%R13,%RDX,8)

0x4023a5 CMP	%RAX,%R11

0x4023a8 JLE	4023f0

0x4023aa VMOVSD	(%R12,%RAX,8),%XMM2

0x4023b0 ADD	$0x2,%RDX

0x4023b4 VADDSD	(%RBX,%RAX,8),%XMM2,%XMM3

0x4023b9 VMOVSD	%XMM3,(%R13,%RAX,8)

0x4023c0 CMP	%RDX,%R11

0x4023c3 JLE	4023f0

0x4023c5 VMOVSD	(%RBX,%RDX,8),%XMM4

0x4023ca VADDSD	(%R12,%RDX,8),%XMM4,%XMM5

0x4023d0 VMOVSD	%XMM5,(%R13,%RDX,8)

0x4023d7 VZEROUPPER

0x4023da LEA	-0x20(%RBP),%RSP

0x4023de POP	%RBX

0x4023df POP	%R12

0x4023e1 POP	%R13

0x4023e3 POP	%R14

0x4023e5 POP	%RBP

0x4023e6 RET

0x4023e7 NOPW	(%RAX,%RAX,1)

0x4023f0 VZEROUPPER

0x4023f3 LEA	-0x20(%RBP),%RSP

0x4023f7 POP	%RBX

0x4023f8 POP	%R12

0x4023fa POP	%R13

0x4023fc POP	%R14

0x4023fe POP	%RBP

0x4023ff RET

0x402400 INC	%RAX

0x402403 XOR	%EDX,%EDX

0x402405 JMP	402121

0x40240a NOPW	(%RAX,%RAX,1)

0x402410 XOR	%EDI,%EDI

0x402412 MOV	$0x334906100,%RBX

0x40241c MOV	$0x19a686100,%R12

0x402426 MOV	$0x406100,%R13

0x402430 JMP	40235b

0x402435 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○83.46	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○16.54	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Coverage (%)	Name	Source Location	Module
○99.00	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Coverage (%)	Name	Source Location	Module
○99.25	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Coverage (%)	Name	Source Location	Module
○99.23	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Coverage (%)	Name	Source Location	Module
○99.36	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Coverage (%)	Name	Source Location	Module
○99.45	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Coverage (%)	Name	Source Location	Module
○99.54	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Coverage (%)	Name	Source Location	Module
○99.64	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Coverage (%)	Name	Source Location	Module
○99.71	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Coverage (%)	Name	Source Location	Module
○99.60	gomp_thread_start	team.c:130	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x6

Source file and lines	stream.c:342-344
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:342-344.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 27.33 to 11.50 cycles (2.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 46% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 27.33 to 21.85 cycles (1.25x speedup).

Details

44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

72% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
8% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:342

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:342
VZEROUPPER: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:342

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:344

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:342

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time). 7 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 63 FP arithmetical operations:

63: addition or subtraction

The binary function is loading 1008 bytes (126 double precision FP elements). The binary function is storing 504 bytes (63 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	146
nb uops	154
loop length	659
used x86 registers	15
used mmx registers	0
used xmm registers	6
used ymm registers	2
used zmm registers	14
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	27.33 cycles
front end	27.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.30	15.50	11.33	11.33	9.00	15.50	15.30	9.00	9.00	9.00	15.40	11.33
cycles	15.30	15.50	11.33	11.33	9.00	15.50	15.30	9.00	9.00	9.00	15.40	11.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	27.33
Dispatch	15.50
DIV/SQRT	10.00
Overall L1	27.33

Vectorization ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	72%
load	72%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	72%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	44%
load	72%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	71%
load	71%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	46%
load	71%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 27.33 cycles. At this rate:

19% of peak load performance is reached (36.88 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (18.44 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 27.33 to 15.50 cycles (1.76x speedup).

ASM code

In the binary file, the address of the function is: 4020e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x401060,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x401030,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
CALL %R12	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV $0x33450000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RBX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 402400 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%RDX,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R11,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4023da <main._omp_fn.4+0x2fa>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP $0x6,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 402410 <main._omp_fn.4+0x330>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SAL $0x6,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA -0x40(%R10),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x6,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
LEA (,%RDX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x334906100,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x19a686100,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x406100,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA (%RBX,%RSI,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R12,%RSI,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R13,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
JE 40227b <main._omp_fn.4+0x19b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402259 <main._omp_fn.4+0x179>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402240 <main._omp_fn.4+0x160>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402227 <main._omp_fn.4+0x147>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40220e <main._omp_fn.4+0x12e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4021f5 <main._omp_fn.4+0x115>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4021dc <main._omp_fn.4+0xfc>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD (%R8),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV $0x40,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VADDPD (%RDI),%ZMM0,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM1,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R8,%RCX,1),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM2,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM3,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM4,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM5,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM6,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM7,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM8,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM9,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM10,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM11,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM12,%ZMM13	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM13,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402348 <main._omp_fn.4+0x268>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4023f0 <main._omp_fn.4+0x310>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x2,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 40238f <main._omp_fn.4+0x2af>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R14,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAL $0x3,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VMOVUPD (%R12,%RDI,1),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VADDPD (%RBX,%RDI,1),%YMM14,%YMM15	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
AND $-0x4,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %R14,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD %YMM15,(%R13,%RDI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
TEST $0x3,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4023f0 <main._omp_fn.4+0x310>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RBX,%RDX,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSD (%R12,%RDX,8),%XMM0,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM1,(%R13,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4023f0 <main._omp_fn.4+0x310>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R12,%RAX,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x2,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDSD (%RBX,%RAX,8),%XMM2,%XMM3	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM3,(%R13,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4023f0 <main._omp_fn.4+0x310>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RBX,%RDX,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R12,%RDX,8),%XMM4,%XMM5	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%R13,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 402121 <main._omp_fn.4+0x41>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x334906100,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x19a686100,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x406100,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
JMP 40235b <main._omp_fn.4+0x27b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x6

Source file and lines	stream.c:342-344
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

72% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
8% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:342

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:342
VZEROUPPER: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:342

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:344

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:342

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 63 FP arithmetical operations:

63: addition or subtraction

The binary function is loading 1008 bytes (126 double precision FP elements). The binary function is storing 504 bytes (63 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	146
nb uops	154
loop length	659
used x86 registers	15
used mmx registers	0
used xmm registers	6
used ymm registers	2
used zmm registers	14
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	27.33 cycles
front end	27.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.30	15.50	11.33	11.33	9.00	15.50	15.30	9.00	9.00	9.00	15.40	11.33
cycles	15.30	15.50	11.33	11.33	9.00	15.50	15.30	9.00	9.00	9.00	15.40	11.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	27.33
Dispatch	15.50
DIV/SQRT	10.00
Overall L1	27.33

Vectorization ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	72%
load	72%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	72%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	44%
load	72%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	71%
load	71%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	46%
load	71%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 27.33 cycles. At this rate:

19% of peak load performance is reached (36.88 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (18.44 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4020e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x401060,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x401030,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
CALL %R12	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV $0x33450000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RBX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 402400 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%RDX,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R11,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4023da <main._omp_fn.4+0x2fa>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP $0x6,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 402410 <main._omp_fn.4+0x330>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SAL $0x6,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA -0x40(%R10),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x6,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
LEA (,%RDX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x334906100,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x19a686100,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x406100,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA (%RBX,%RSI,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R12,%RSI,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R13,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
JE 40227b <main._omp_fn.4+0x19b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402259 <main._omp_fn.4+0x179>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402240 <main._omp_fn.4+0x160>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402227 <main._omp_fn.4+0x147>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40220e <main._omp_fn.4+0x12e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4021f5 <main._omp_fn.4+0x115>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4021dc <main._omp_fn.4+0xfc>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD (%R8),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV $0x40,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VADDPD (%RDI),%ZMM0,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM1,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R8,%RCX,1),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM2,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM3,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM4,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM5,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM6,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM7,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM8,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM9,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM10,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM11,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM12,%ZMM13	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD %ZMM13,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402348 <main._omp_fn.4+0x268>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4023f0 <main._omp_fn.4+0x310>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x2,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 40238f <main._omp_fn.4+0x2af>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R14,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAL $0x3,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VMOVUPD (%R12,%RDI,1),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VADDPD (%RBX,%RDI,1),%YMM14,%YMM15	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
AND $-0x4,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %R14,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD %YMM15,(%R13,%RDI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
TEST $0x3,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4023f0 <main._omp_fn.4+0x310>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RBX,%RDX,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSD (%R12,%RDX,8),%XMM0,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM1,(%R13,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4023f0 <main._omp_fn.4+0x310>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R12,%RAX,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x2,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDSD (%RBX,%RAX,8),%XMM2,%XMM3	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM3,(%R13,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4023f0 <main._omp_fn.4+0x310>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RBX,%RDX,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R12,%RDX,8),%XMM4,%XMM5	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%R13,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 402121 <main._omp_fn.4+0x41>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x334906100,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x19a686100,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x406100,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
JMP 40235b <main._omp_fn.4+0x27b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

▶Scalability Runs Description

Run 1x6	Number processes: 1Number nodes: NANumber processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/run/oneview_runs/multicore/gcc_2/oneview_run_1773737889OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threadsOMP_NUM_THREADS: 6
Run 1x96	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/run/oneview_runs/multicore/gcc_2/oneview_run_1773737889OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x120	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/run/oneview_runs/multicore/gcc_2/oneview_run_1773737889OMP_NUM_THREADS: 120OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x126	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/run/oneview_runs/multicore/gcc_2/oneview_run_1773737889OMP_NUM_THREADS: 126OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x144	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/run/oneview_runs/multicore/gcc_2/oneview_run_1773737889OMP_NUM_THREADS: 144OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x168	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/run/oneview_runs/multicore/gcc_2/oneview_run_1773737889OMP_NUM_THREADS: 168OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x192	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/run/oneview_runs/multicore/gcc_2/oneview_run_1773737889OMP_NUM_THREADS: 192OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x216	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/run/oneview_runs/multicore/gcc_2/oneview_run_1773737889OMP_NUM_THREADS: 216OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x240	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/run/oneview_runs/multicore/gcc_2/oneview_run_1773737889OMP_NUM_THREADS: 240OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x256	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/run/oneview_runs/multicore/gcc_2/oneview_run_1773737889OMP_NUM_THREADS: 256OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x6) Efficiency	(1x6) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)	(1x120) Efficiency	(1x120) Potential Speed-Up (%)	(1x126) Efficiency	(1x126) Potential Speed-Up (%)	(1x144) Efficiency	(1x144) Potential Speed-Up (%)	(1x168) Efficiency	(1x168) Potential Speed-Up (%)	(1x192) Efficiency	(1x192) Potential Speed-Up (%)	(1x216) Efficiency	(1x216) Potential Speed-Up (%)	(1x240) Efficiency	(1x240) Potential Speed-Up (%)	(1x256) Efficiency	(1x256) Potential Speed-Up (%)
1	0	0.64	31.51	0.52	42.13	0.5	45.14	0.43	48.32	0.38	57.81	0.3	56.34	0.27	62.95	0.26	66.09	0.24	70.34

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x6	6	1	1	1	18.169998168945	95.607864379883
1x96	96	0.64	10.17	16	1.8649998903275	86.494323730469
1x120	120	0.52	10.33	20	1.8199998140335	87.10962677002
1x126	126	0.5	10.45	21	1.7500001192093	89.893432617188
1x144	144	0.43	10.28	24	1.9350001811981	84.532089233398
1x168	168	0.38	10.51	28	1.6899998188019	92.563194274902
1x192	192	0.3	9.59	32	2.2499997615814	80.457885742188
1x216	216	0.27	9.81	36	2.0100002288818	86.520652770996
1x240	240	0.26	10.41	40	1.8300001621246	89.338172912598
1x256	256	0.24	10.38	42.666666666667	1.6950001716614	92.957946777344

Name	Coverage (%)	Time (s)
▼main._omp_fn.4–	95.61	17.90
○Loop 2 - stream.c:344-344 - exec	95.61	17.81

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency