OV - exec - Function main._omp

	Function: main._omp_fn.2	Module: exec	Source: stream.c:271-275	Coverage (incl. loops): 0.78% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c: 271 - 275

--------------------------------------------------------------------------------

271: #pragma omp parallel for

272:     for (j=0; j<STREAM_ARRAY_SIZE; j++) {

273: 	    a[j] = 1.0;

274: 	    b[j] = 2.0;

275: 	    c[j] = 0.0;

0x402720 PUSH	%RBP

0x402721 MOV	$0x401060,%RAX

0x40272b MOV	%RSP,%RBP

0x40272e PUSH	%R14

0x402730 PUSH	%R13

0x402732 PUSH	%R12

0x402734 MOV	$0x401030,%R12

0x40273e PUSH	%RBX

0x40273f CALL	%RAX

0x402741 MOVSXD	%EAX,%RBX

0x402744 CALL	%R12

0x402747 MOVSXD	%EAX,%RCX

0x40274a MOV	$0x33450000,%EAX

0x40274f CQTO

0x402751 IDIV	%RBX

0x402754 CMP	%RDX,%RCX

0x402757 JL	402aa8

0x40275d IMUL	%RAX,%RCX

0x402761 ADD	%RCX,%RDX

0x402764 LEA	(%RAX,%RDX,1),%R11

0x402768 CMP	%R11,%RDX

0x40276b JGE	402a8c

0x402771 LEA	-0x1(%RAX),%RSI

0x402775 MOV	%RDX,%R14

0x402778 CMP	$0x6,%RSI

0x40277c JBE	402ab8

0x402782 MOV	%RAX,%R10

0x402785 MOV	$0x404700,%R9

0x40278f SHR	$0x3,%R10

0x402793 VMOVAPD	(%R9),%ZMM2

0x402799 SAL	$0x6,%R10

0x40279d MOV	$0x404740,%R9

0x4027a7 VMOVAPD	(%R9),%ZMM1

0x4027ad LEA	-0x40(%R10),%R9

0x4027b1 SHR	$0x6,%R9

0x4027b5 LEA	(,%RDX,8),%RSI

0x4027bd MOV	$0x334906100,%RBX

0x4027c7 MOV	$0x19a686100,%R12

0x4027d1 MOV	$0x406100,%R13

0x4027db INC	%R9

0x4027de LEA	(%RBX,%RSI,1),%R8

0x4027e2 LEA	(%R12,%RSI,1),%RDI

0x4027e6 XOR	%ECX,%ECX

0x4027e8 ADD	%R13,%RSI

0x4027eb VXORPD	%XMM0,%XMM0,%XMM0

0x4027ef AND	$0x7,%R9D

0x4027f3 JE	4028db

0x4027f9 CMP	$0x1,%R9

0x4027fd JE	4028b9

0x402803 CMP	$0x2,%R9

0x402807 JE	4028a0

0x40280d CMP	$0x3,%R9

0x402811 JE	402887

0x402813 CMP	$0x4,%R9

0x402817 JE	40286e

0x402819 CMP	$0x5,%R9

0x40281d JE	402855

0x40281f CMP	$0x6,%R9

0x402823 JE	40283c

0x402825 VMOVUPD	%ZMM2,(%R8)

0x40282b MOV	$0x40,%ECX

0x402830 VMOVUPD	%ZMM1,(%RDI)

0x402836 VMOVUPD	%ZMM0,(%RSI)

0x40283c VMOVUPD	%ZMM2,(%R8,%RCX,1)

0x402843 VMOVUPD	%ZMM1,(%RDI,%RCX,1)

0x40284a VMOVUPD	%ZMM0,(%RSI,%RCX,1)

0x402851 ADD	$0x40,%RCX

0x402855 VMOVUPD	%ZMM2,(%R8,%RCX,1)

0x40285c VMOVUPD	%ZMM1,(%RDI,%RCX,1)

0x402863 VMOVUPD	%ZMM0,(%RSI,%RCX,1)

0x40286a ADD	$0x40,%RCX

0x40286e VMOVUPD	%ZMM2,(%R8,%RCX,1)

0x402875 VMOVUPD	%ZMM1,(%RDI,%RCX,1)

0x40287c VMOVUPD	%ZMM0,(%RSI,%RCX,1)

0x402883 ADD	$0x40,%RCX

0x402887 VMOVUPD	%ZMM2,(%R8,%RCX,1)

0x40288e VMOVUPD	%ZMM1,(%RDI,%RCX,1)

0x402895 VMOVUPD	%ZMM0,(%RSI,%RCX,1)

0x40289c ADD	$0x40,%RCX

0x4028a0 VMOVUPD	%ZMM2,(%R8,%RCX,1)

0x4028a7 VMOVUPD	%ZMM1,(%RDI,%RCX,1)

0x4028ae VMOVUPD	%ZMM0,(%RSI,%RCX,1)

0x4028b5 ADD	$0x40,%RCX

0x4028b9 VMOVUPD	%ZMM2,(%R8,%RCX,1)

0x4028c0 VMOVUPD	%ZMM1,(%RDI,%RCX,1)

0x4028c7 VMOVUPD	%ZMM0,(%RSI,%RCX,1)

0x4028ce ADD	$0x40,%RCX

0x4028d2 CMP	%R10,%RCX

0x4028d5 JE	4029a8

(4) 0x4028db VMOVUPD	%ZMM2,(%R8,%RCX,1)

(4) 0x4028e2 VMOVUPD	%ZMM1,(%RDI,%RCX,1)

(4) 0x4028e9 VMOVUPD	%ZMM0,(%RSI,%RCX,1)

(4) 0x4028f0 VMOVUPD	%ZMM2,0x40(%R8,%RCX,1)

(4) 0x4028f8 VMOVUPD	%ZMM1,0x40(%RDI,%RCX,1)

(4) 0x402900 VMOVUPD	%ZMM0,0x40(%RSI,%RCX,1)

(4) 0x402908 VMOVUPD	%ZMM2,0x80(%R8,%RCX,1)

(4) 0x402910 VMOVUPD	%ZMM1,0x80(%RDI,%RCX,1)

(4) 0x402918 VMOVUPD	%ZMM0,0x80(%RSI,%RCX,1)

(4) 0x402920 VMOVUPD	%ZMM2,0xc0(%R8,%RCX,1)

(4) 0x402928 VMOVUPD	%ZMM1,0xc0(%RDI,%RCX,1)

(4) 0x402930 VMOVUPD	%ZMM0,0xc0(%RSI,%RCX,1)

(4) 0x402938 VMOVUPD	%ZMM2,0x100(%R8,%RCX,1)

(4) 0x402940 VMOVUPD	%ZMM1,0x100(%RDI,%RCX,1)

(4) 0x402948 VMOVUPD	%ZMM0,0x100(%RSI,%RCX,1)

(4) 0x402950 VMOVUPD	%ZMM2,0x140(%R8,%RCX,1)

(4) 0x402958 VMOVUPD	%ZMM1,0x140(%RDI,%RCX,1)

(4) 0x402960 VMOVUPD	%ZMM0,0x140(%RSI,%RCX,1)

(4) 0x402968 VMOVUPD	%ZMM2,0x180(%R8,%RCX,1)

(4) 0x402970 VMOVUPD	%ZMM1,0x180(%RDI,%RCX,1)

(4) 0x402978 VMOVUPD	%ZMM0,0x180(%RSI,%RCX,1)

(4) 0x402980 VMOVUPD	%ZMM2,0x1c0(%R8,%RCX,1)

(4) 0x402988 VMOVUPD	%ZMM1,0x1c0(%RDI,%RCX,1)

(4) 0x402990 VMOVUPD	%ZMM0,0x1c0(%RSI,%RCX,1)

(4) 0x402998 ADD	$0x200,%RCX

(4) 0x40299f CMP	%R10,%RCX

(4) 0x4029a2 JNE	4028db

0x4029a8 MOV	%RAX,%RDI

0x4029ab AND	$-0x8,%RDI

0x4029af ADD	%RDI,%RDX

0x4029b2 CMP	%RDI,%RAX

0x4029b5 JE	402a98

0x4029bb SUB	%RDI,%RAX

0x4029be LEA	-0x1(%RAX),%RSI

0x4029c2 CMP	$0x2,%RSI

0x4029c6 JBE	402a15

0x4029c8 ADD	%R14,%RDI

0x4029cb MOV	$0x404740,%R8

0x4029d5 MOV	$0x404700,%R14

0x4029df VMOVAPD	(%R14),%YMM3

0x4029e4 VMOVAPD	(%R8),%YMM4

0x4029e9 SAL	$0x3,%RDI

0x4029ed VXORPD	%XMM5,%XMM5,%XMM5

0x4029f1 VMOVUPD	%YMM3,(%RBX,%RDI,1)

0x4029f6 VMOVUPD	%YMM4,(%R12,%RDI,1)

0x4029fc VMOVUPD	%YMM5,(%R13,%RDI,1)

0x402a03 MOV	%RAX,%RDI

0x402a06 AND	$-0x4,%RDI

0x402a0a ADD	%RDI,%RDX

0x402a0d TEST	$0x3,%AL

0x402a0f JE	402a98

0x402a15 MOV	$0x404700,%RAX

0x402a1f MOV	$0x404740,%R10

0x402a29 MOV	$0x404918,%R9

0x402a33 VMOVSD	(%RAX),%XMM6

0x402a37 VMOVSD	(%R10),%XMM7

0x402a3c VMOVSD	(%R9),%XMM8

0x402a41 LEA	0x1(%RDX),%RCX

0x402a45 VMOVSD	%XMM6,(%RBX,%RDX,8)

0x402a4a VMOVSD	%XMM7,(%R12,%RDX,8)

0x402a50 VMOVSD	%XMM8,(%R13,%RDX,8)

0x402a57 CMP	%RCX,%R11

0x402a5a JLE	402a98

0x402a5c ADD	$0x2,%RDX

0x402a60 VMOVSD	%XMM6,(%RBX,%RCX,8)

0x402a65 VMOVSD	%XMM7,(%R12,%RCX,8)

0x402a6b VMOVSD	%XMM8,(%R13,%RCX,8)

0x402a72 CMP	%RDX,%R11

0x402a75 JLE	402a98

0x402a77 VMOVSD	%XMM6,(%RBX,%RDX,8)

0x402a7c VMOVSD	%XMM7,(%R12,%RDX,8)

0x402a82 VMOVSD	%XMM8,(%R13,%RDX,8)

0x402a89 VZEROUPPER

0x402a8c POP	%RBX

0x402a8d POP	%R12

0x402a8f POP	%R13

0x402a91 POP	%R14

0x402a93 POP	%RBP

0x402a94 RET

0x402a95 NOPL	(%RAX)

0x402a98 VZEROUPPER

0x402a9b POP	%RBX

0x402a9c POP	%R12

0x402a9e POP	%R13

0x402aa0 POP	%R14

0x402aa2 POP	%RBP

0x402aa3 RET

0x402aa4 NOPL	(%RAX)

0x402aa8 INC	%RAX

0x402aab XOR	%EDX,%EDX

0x402aad JMP	40275d

0x402ab2 NOPW	(%RAX,%RAX,1)

0x402ab8 XOR	%EDI,%EDI

0x402aba MOV	$0x334906100,%RBX

0x402ac4 MOV	$0x19a686100,%R12

0x402ace MOV	$0x406100,%R13

0x402ad8 JMP	4029bb

0x402add NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○99.28	gomp_thread_start	team.c:130	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	stream.c:271-275
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:271-275.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.00 to 16.50 cycles (1.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 49% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 28.00 to 23.01 cycles (1.22x speedup).

Details

52% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

57% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
20% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:271
VZEROUPPER: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:275
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:271

Vector unaligned load/store instructions

Detected 3 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:273
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:274
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:275

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:271

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 216 bytes. The binary function is storing 1512 bytes.

General properties

nb instructions	160
nb uops	168
loop length	755
used x86 registers	15
used mmx registers	0
used xmm registers	5
used ymm registers	3
used zmm registers	3
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	28.00 cycles
front end	28.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.50	14.40	6.33	6.33	20.00	14.40	14.30	20.00	20.00	20.00	14.40	6.33
cycles	14.50	14.40	6.33	6.33	20.00	14.40	14.30	20.00	20.00	20.00	14.40	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	28.00
Dispatch	20.00
DIV/SQRT	10.00
Overall L1	28.00

Vectorization ratios

INT

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	71%
load	57%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	52%
load	57%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	20%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	65%
load	48%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	49%
load	48%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.00 cycles. At this rate:

4% of peak load performance is reached (7.71 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (54.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 28.00 to 20.00 cycles (1.40x speedup).

ASM code

In the binary file, the address of the function is: 402720

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x401060,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x401030,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
CALL %R12	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV $0x33450000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RBX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 402aa8 <main._omp_fn.2+0x388>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%RDX,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R11,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 402a8c <main._omp_fn.2+0x36c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 402ab8 <main._omp_fn.2+0x398>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x404700,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
SHR $0x3,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VMOVAPD (%R9),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
SAL $0x6,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0x404740,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
VMOVAPD (%R9),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
LEA -0x40(%R10),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x6,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (,%RDX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x334906100,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x19a686100,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x406100,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RBX,%RSI,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R12,%RSI,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R13,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
AND $0x7,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4028db <main._omp_fn.2+0x1bb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4028b9 <main._omp_fn.2+0x199>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4028a0 <main._omp_fn.2+0x180>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402887 <main._omp_fn.2+0x167>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40286e <main._omp_fn.2+0x14e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402855 <main._omp_fn.2+0x135>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40283c <main._omp_fn.2+0x11c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD %ZMM2,(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
MOV $0x40,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD %ZMM1,(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM0,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM2,(%R8,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM0,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM2,(%R8,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM0,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM2,(%R8,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM0,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM2,(%R8,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM0,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM2,(%R8,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM0,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM2,(%R8,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM0,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4029a8 <main._omp_fn.2+0x288>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402a98 <main._omp_fn.2+0x378>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x2,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 402a15 <main._omp_fn.2+0x2f5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R14,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x404740,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x404700,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
VMOVAPD (%R14),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD (%R8),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
SAL $0x3,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VXORPD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVUPD %YMM3,(%RBX,%RDI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM4,(%R12,%RDI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM5,(%R13,%RDI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST $0x3,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 402a98 <main._omp_fn.2+0x378>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x404700,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x404740,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x404918,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
VMOVSD (%RAX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R10),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R9),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RDX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM6,(%RBX,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM7,(%R12,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM8,(%R13,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 402a98 <main._omp_fn.2+0x378>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x2,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM6,(%RBX,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM7,(%R12,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM8,(%R13,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 402a98 <main._omp_fn.2+0x378>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD %XMM6,(%RBX,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM7,(%R12,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM8,(%R13,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 40275d <main._omp_fn.2+0x3d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x334906100,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x19a686100,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x406100,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
JMP 4029bb <main._omp_fn.2+0x29b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	stream.c:271-275
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

52% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

57% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
20% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:271
VZEROUPPER: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:275
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:271

Vector unaligned load/store instructions

Detected 3 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:273
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:274
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:275

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix03.benchmarkcenter.megware.com/177-373-7190/stream-add/build/stream-add/src/stream.c:271

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 216 bytes. The binary function is storing 1512 bytes.

General properties

nb instructions	160
nb uops	168
loop length	755
used x86 registers	15
used mmx registers	0
used xmm registers	5
used ymm registers	3
used zmm registers	3
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	28.00 cycles
front end	28.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.50	14.40	6.33	6.33	20.00	14.40	14.30	20.00	20.00	20.00	14.40	6.33
cycles	14.50	14.40	6.33	6.33	20.00	14.40	14.30	20.00	20.00	20.00	14.40	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	28.00
Dispatch	20.00
DIV/SQRT	10.00
Overall L1	28.00

Vectorization ratios

INT

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	71%
load	57%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	52%
load	57%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	20%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	65%
load	48%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	49%
load	48%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.00 cycles. At this rate:

4% of peak load performance is reached (7.71 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (54.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402720

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x401060,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x401030,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
CALL %R12	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV $0x33450000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RBX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 402aa8 <main._omp_fn.2+0x388>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%RDX,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R11,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 402a8c <main._omp_fn.2+0x36c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 402ab8 <main._omp_fn.2+0x398>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x404700,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
SHR $0x3,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VMOVAPD (%R9),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
SAL $0x6,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0x404740,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
VMOVAPD (%R9),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
LEA -0x40(%R10),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x6,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (,%RDX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x334906100,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x19a686100,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x406100,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RBX,%RSI,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R12,%RSI,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R13,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
AND $0x7,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4028db <main._omp_fn.2+0x1bb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4028b9 <main._omp_fn.2+0x199>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4028a0 <main._omp_fn.2+0x180>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402887 <main._omp_fn.2+0x167>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40286e <main._omp_fn.2+0x14e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402855 <main._omp_fn.2+0x135>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40283c <main._omp_fn.2+0x11c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD %ZMM2,(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
MOV $0x40,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD %ZMM1,(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM0,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM2,(%R8,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM0,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM2,(%R8,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM0,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM2,(%R8,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM0,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM2,(%R8,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM0,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM2,(%R8,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM0,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM2,(%R8,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM0,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4029a8 <main._omp_fn.2+0x288>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402a98 <main._omp_fn.2+0x378>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x2,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 402a15 <main._omp_fn.2+0x2f5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R14,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x404740,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x404700,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
VMOVAPD (%R14),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD (%R8),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
SAL $0x3,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VXORPD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVUPD %YMM3,(%RBX,%RDI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM4,(%R12,%RDI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM5,(%R13,%RDI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST $0x3,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 402a98 <main._omp_fn.2+0x378>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x404700,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x404740,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x404918,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
VMOVSD (%RAX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R10),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R9),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RDX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM6,(%RBX,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM7,(%R12,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM8,(%R13,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 402a98 <main._omp_fn.2+0x378>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x2,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM6,(%RBX,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM7,(%R12,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM8,(%R13,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 402a98 <main._omp_fn.2+0x378>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD %XMM6,(%RBX,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM7,(%R12,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM8,(%R13,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 40275d <main._omp_fn.2+0x3d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x334906100,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x19a686100,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x406100,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
JMP 4029bb <main._omp_fn.2+0x29b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼main._omp_fn.2–	0.78	0.03
○Loop 4 - stream.c:273-275 - exec	0.78	0.03

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