	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/run/oneview_runs/compilers/aocc_6/oneview_results_1786546388 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/run/oneview_runs/compilers/aocc_6/oneview_results_1786546388


+====================================================================================================================+
+                                                    1  -  GLOBAL                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             1.1  -  Experiment Summary                                             +
+--------------------------------------------------------------------------------------------------------------------+

  Application:			/beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/run/binaries/aocc_6/exec
  Timestamp:			2026-08-12 16:53:08
  Universal Timestamp:		1786546388
  Experiment Type:		MPI; OpenMP; Throughput; 
  Machine:			gmz12.benchmarkcenter.megware.com
  Architecture:			x86_64
  Micro Architecture:		ZEN_V5
  Model Name:			AMD EPYC 9655 96-Core Processor
  Cache Size:			1024 KB
  Number of Cores:		96
  OS Version:			Linux 5.14.0-687.29.1.el9_8.x86_64 #1 SMP PREEMPT_DYNAMIC Thu Jul 23 16:18:48 EDT 2026
  Compilation Options:		
		exec: AMD clang version 17.0.6 (CLANG: AOCC_5.1.0-Build#1994 2025_12_23) /cluster/comp/aocc/5.1.0/bin/clang-17 -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/build/HACCmk/CoMD/src-openmp -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/build/aocc_6 -O2 -march=znver5 -ffast-math -g -fno-omit-frame-pointer -fcf-protection=none -nopie -grecord-command-line -fopenmp=libomp -ffast-math -MD -MT CMakeFiles/HACCmk.dir/src/Step10_orig.c.o -MF CMakeFiles/HACCmk.dir/src/Step10_orig.c.o.d -o CMakeFiles/HACCmk.dir/src/Step10_orig.c.o -c /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/build/HACCmk/src/Step10_orig.c 
  Number of processes observed:	1
  Number of threads observed:	192
  MAQAO version:		2026.1.0
  MAQAO build:			6d1be1d51c1e63266254997eb301734a7264775d::20260810-150026




+--------------------------------------------------------------------------------------------------------------------+
+                                               1.2  -  Global Metrics                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Total Time:				4.46 s
  Max (Thread Active Time):		4.33 s
  Average Active Time:			4.32 s
  Activity Ratio:			98.9 %
  Average number of active threads:	185.854
  Affinity Stability:			98.8 %
  Time spent in analyzed loops:		66.8 %
  Time spent in analyzed innermost loops: 66.8 %
  Time spent in user code:		66.9 %
  Compilation Options Score:		100
  Array Access Efficiency:		99.9 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.00
  Perfect OpenMP/MPI/Pthread/TBB:	1.28
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	1.48
  If No Scalar Integer:
      Potential Speedup:		1.00
      Nb Loops to get 80%:		1
  If FP Vectorized:
      Potential Speedup:		1.00
      Nb Loops to get 80%:		1
  If Fully Vectorized:
      Potential Speedup:		1.00
      Nb Loops to get 80%:		1
  If Only FP Arithmetic:
      Potential Speedup:		1.00
      Nb Loops to get 80%:		1




+--------------------------------------------------------------------------------------------------------------------+
+                                             1.3  -  Potential Speedups                                             +
+--------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 2      | 3      | 4      | 
      Cumulated Speedup | 1.0003 | 1.0003 | 1.0003 | 1.0003 | 
  Top 5 loops:
    exec - 3:	1.0003
    exec - 1:	1.0003
    exec - 6:	1.0003
    exec - 5:	1.0003

  If FP Vectorized:
      Number of loops   | 1      | 2      | 3      | 4      | 
      Cumulated Speedup | 1.0007 | 1.0008 | 1.0008 | 1.0008 | 
  Top 5 loops:
    exec - 3:	1.0007
    exec - 5:	1.0008
    exec - 1:	1.0008
    exec - 6:	1.0008

  If Fully Vectorized:
      Number of loops   | 1      | 2      | 3      | 4      | 
      Cumulated Speedup | 1.0027 | 1.0027 | 1.0027 | 1.0027 | 
  Top 5 loops:
    exec - 3:	1.0027
    exec - 5:	1.0027
    exec - 1:	1.0027
    exec - 6:	1.0027

  If Only FP Arithmetic:
      Number of loops   | 1      | 2      | 3      | 4      | 
      Cumulated Speedup | 1.0019 | 1.0022 | 1.0022 | 1.0022 | 
  Top 5 loops:
    exec - 3:	1.0019
    exec - 1:	1.0022
    exec - 6:	1.0022
    exec - 5:	1.0022



+====================================================================================================================+
+                                                   2  -  SUMMARY                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             2.1  -  EXPERIMENT QUALITY                                             +
+--------------------------------------------------------------------------------------------------------------------+

  [0 / 4] Application profile is too short (4.33 s)
If the overall application profiling time is less than 10 seconds, many of the measurements at function or loop level
will very likely be under the measurement quality threshold (0,1 seconds).
 Rerun to increase runtime duration: for example use a larger dataset or include a repetition loop.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [3 / 3] Most of time spent in analyzed modules (100.00%) comes from functions compiled with architecture specialization option
-march=znver5


  [3 / 3] Most of time spent in analyzed modules comes from functions with compilation options informations and
-fno-omit-frame-pointer is present
-fno-omit-frame-pointer improves the accuracy of callchains found during the application profiling.

  [3 / 3] Optimization level option is correctly used


  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.00 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the execution
time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+--------------------------------------------------------------------------------------------------------------------+
+                                                2.2  -  CODE QUALITY                                                +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (66.80%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [4 / 4] Threads activity is good
On average, more than 96.80% of observed threads are actually active 

  [4 / 4] CPU activity is good
CPU cores are active 98.87% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (66.41%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (66.80%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (98.76%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [0 / 3] Too many functions do not use all threads
Functions running on a reduced number of threads (typically sequential code) cover at least 10% of application
walltime (31.52%). Check both "Max Inclusive Time Over Threads" and "Nb Threads" in Functions or Loops tabs and
consider parallelizing sequential regions or improving parallelization of regions running on a reduced number of
threads

  [3 / 3] Cumulative Outermost/In between loops coverage (0.00%) lower than cumulative innermost loop coverage (66.80%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+--------------------------------------------------------------------------------------------------------------------+
+                                               2.3  -  LOOPS OVERVIEW                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 6   :
     analysis: Execution Time: 66 % - Vectorization Ratio: 100.00 % - Vector Length Use: 56.69 %
     Loop Computation Issues: 16
        [16] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 4
            issues (= instructions) costing 4 points each.
     Control Flow Issues: 2
        [2] [SA] Several paths (2 paths) - Simplify control structure or force the compiler to use masked
            instructions. There are 2 issues ( = paths) costing 1 point each.
     Data Access Issues: 2
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 2
        [2] [SA] Several paths (2 paths) - Simplify control structure or force the compiler to use masked
            instructions. There are 2 issues ( = paths) costing 1 point each.
     Inefficient Vectorization: 2
        [2] [SA] Inefficient vectorization: use of masked instructions - Simplify control structure. The issue costs 2
            points.

   + exec - 3   :
     analysis: Execution Time: 0 % - Vectorization Ratio: 0.00 % - Vector Length Use: 6.62 %
     Control Flow Issues: 1
        [1] [SA] Presence of calls - Inline either by compiler or by hand and use SVML for libm calls. There are 1
            issues (= calls) costing 1 point each.
     Data Access Issues: 8
        [6] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 3 issues ( = data accesses) costing 2 point
            each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 7
        [1] [SA] Presence of calls - Inline either by compiler or by hand and use SVML for libm calls. There are 1
            issues (= calls) costing 1 point each.
        [6] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 3 issues ( = data accesses) costing 2 point
            each.

   + exec - 1   :
     analysis: Execution Time: 0 % - Vectorization Ratio: 100.00 % - Vector Length Use: 100.00 %

   + exec - 5   :
     analysis: Execution Time: 0 % - Vectorization Ratio: 100.00 % - Vector Length Use: 29.10 %
     Loop Computation Issues: 8
        [8] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 2
            issues (= instructions) costing 4 points each.
     Control Flow Issues: 2
        [2] [SA] Several paths (2 paths) - Simplify control structure or force the compiler to use masked
            instructions. There are 2 issues ( = paths) costing 1 point each.
     Vectorization Roadblocks: 2
        [2] [SA] Several paths (2 paths) - Simplify control structure or force the compiler to use masked
            instructions. There are 2 issues ( = paths) costing 1 point each.
     Inefficient Vectorization: 2
        [2] [SA] Inefficient vectorization: use of masked instructions - Simplify control structure. The issue costs 2
            points.



+====================================================================================================================+
+                                                 3  -  APPLICATION                                                  +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                               3.1  -  Categorization                                               +
+--------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others  | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+---------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 66.86  | 0.97    | 0.00    | 0.01   | 0.00   | 0.00  | 0.00  | 32.16 | 0.00    | 0.00  |




+--------------------------------------------------------------------------------------------------------------------+
+                                          3.2  -  Function Based Profiling                                          +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 3                         | 98.22                     | 98.22                     |
   4% to 8%                   | 0                         | 0.00                      | 98.22                     |
   2% to 4%                   | 0                         | 0.00                      | 98.22                     |
   1% to 2%                   | 0                         | 0.00                      | 98.22                     |
   0.5% to 1%                 | 1                         | 0.93                      | 99.15                     |
   0.25% to 0.5%              | 1                         | 0.32                      | 99.47                     |
   0.125% to 0.25%            | 2                         | 0.33                      | 99.80                     |
   < 0.125%                   | 15                        | 0.20                      | 100.00                    |




+--------------------------------------------------------------------------------------------------------------------+
+                                            3.3  -  Loop Based Profiling                                            +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 1                         | 66.41                     | 66.41                     |
   4% to 8%                   | 0                         | 0.00                      | 66.41                     |
   2% to 4%                   | 0                         | 0.00                      | 66.41                     |
   1% to 2%                   | 0                         | 0.00                      | 66.41                     |
   0.5% to 1%                 | 0                         | 0.00                      | 66.41                     |
   0.25% to 0.5%              | 1                         | 0.28                      | 66.69                     |
   0.125% to 0.25%            | 0                         | 0.00                      | 66.69                     |
   < 0.125%                   | 2                         | 0.11                      | 66.80                     |


+====================================================================================================================+
+                                                  4  -  FUNCTIONS                                                   +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                              4.1  -  Top 10 Functions                                              +
+--------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module              | Coverage (%)   | Time (s)       |
  --------------------------------------------------------+---------------------+----------------+----------------+
   Step10_orig                                            | exec                | 66.44          | 2.87           |
   __kmp_hardware_timestamp                               | libomp.so           | 17.44          | 0.75           |
   __kmp_hyper_barrier_release(barrier_type, kmp_info*... | libomp.so           | 14.33          | 0.62           |
   unknown_kernel_region                                  | kernel              | 0.93           | 0.04           |
   main.omp_outlined.7                                    | exec                | 0.32           | 0.02           |
   __kmp_hyper_barrier_gather(barrier_type, kmp_info*,... | libomp.so           | 0.20           | 0.02           |
   __GI___sched_yield                                     | libc.so.6           | 0.13           | 0.01           |
   main                                                   | exec                | 0.09           | 0.76           |
   __kmp_fork_barrier(int, int)                           | libomp.so           | 0.04           | 0.01           |
   __kmpc_for_static_init_4                               | libomp.so           | 0.03           | 0.01           |


+====================================================================================================================+
+                                                    5  -  LOOPS                                                     +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                5.1  -  Top 10 Loops                                                +
+--------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module              | Source Location                                        | Coverage (%)   |
  ----------------+---------------------+--------------------------------------------------------+----------------+
   6              | exec                | Step10_orig.c:21-35                                    | 66.41          |
   3              | exec                | main.c:142-149                                         | 0.28           |
   1              | exec                | main.c:116-119                                         | 0.09           |
   5              | exec                | Step10_orig.c:19-35                                    | 0.02           |





+====================================================================================================================+
+                                                     6  -  CQA                                                      +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                    +
+--------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 6 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/build/HACCmk/src/Step10_orig.c:21-35.

It is main loop of related source loop which is unrolled by 16 (including vectorization).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.1.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

22% of peak computational performance is used (21.57 out of 96.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using 56% register length (average across all SSE/AVX instructions).


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.1.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 23.00 to 17.00 cycles (1.35x speedup).


Workaround
Reduce the number of division or square root instructions:
 - If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast





      6.1.1.1.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 23.00 to 16.00 cycles (1.44x speedup).


      6.1.1.1.4  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.1.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 176 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - KORTESTW: 1 occurrences<<list_path_1_complex_1>>
 - VCVTPD2PS: 2 occurrences<<list_path_1_complex_2>>
 - VCVTPS2PD: 4 occurrences<<list_path_1_complex_3>>



      6.1.1.1.7  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - VCVTPD2PS (FP64 to FP32, SIMD): 2 occurrences<<list_path_1_cvt_1>>
 - VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.


      6.1.1.1.8  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

38 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).
8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.1.1.9  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 496 FP arithmetical operations:
 - 240: addition or subtraction (176 inside FMA instructions)
 - 224: multiply (176 inside FMA instructions)
 - 16: divide
 - 16: square root
The binary loop is loading 352 bytes (88 single precision FP elements).


      6.1.1.1.10  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 1.41 FP operations per loaded or stored byte.




      6.1.1.2  -  Path 2
  ----------------------------------------------------------------------------------------------------------

22% of peak computational performance is used (21.57 out of 96.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.2.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using 56% register length (average across all SSE/AVX instructions).


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.1.2.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 23.00 to 17.00 cycles (1.35x speedup).


Workaround
Reduce the number of division or square root instructions:
 - If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast





      6.1.1.2.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 23.00 to 16.00 cycles (1.44x speedup).


      6.1.1.2.4  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.1.2.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 176 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.2.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - KORTESTW: 1 occurrences<<list_path_2_complex_1>>
 - VCVTPD2PS: 2 occurrences<<list_path_2_complex_2>>
 - VCVTPS2PD: 4 occurrences<<list_path_2_complex_3>>



      6.1.1.2.7  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - VCVTPD2PS (FP64 to FP32, SIMD): 2 occurrences<<list_path_2_cvt_1>>
 - VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences<<list_path_2_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.


      6.1.1.2.8  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

38 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).
8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.1.2.9  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 496 FP arithmetical operations:
 - 240: addition or subtraction (176 inside FMA instructions)
 - 224: multiply (176 inside FMA instructions)
 - 16: divide
 - 16: square root
The binary loop is loading 288 bytes (72 single precision FP elements).


      6.1.1.2.10  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 1.72 FP operations per loaded or stored byte.







      6.1.2  -  Loop 3 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/build/HACCmk/src/main.c:142-149.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.2.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
Detected a function call instruction: ignoring called function instructions.
Rerun with --follow-calls=append to include them to analysis  or with --follow-calls=inline to simulate inlining.
1% of peak computational performance is used (1.09 out of 96.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 5.50 to 5.00 cycles (1.10x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.2.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 6% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 5.50 to 0.34 cycles (16.00x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.2.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.50 to 5.00 cycles (1.10x speedup).


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop
  * use the 'restrict' C99 keyword





      6.1.2.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 3 FMA (fused multiply-add) operations.




      6.1.2.1.5  -  CALL instructions
  ----------------------------------------------------------------------------------------------------------

Detected function call instructions.


Details
Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.
 - Step10_orig: 1 occurrences<<list_path_1_call_1>>



      6.1.2.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - LEA: 1 occurrences<<list_path_1_complex_1>>



      6.1.2.1.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 3 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.2.1.8  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

3 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).



      6.1.2.1.9  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 6 FP arithmetical operations:
 - 3: addition or subtraction (all inside FMA instructions)
 - 3: multiply (all inside FMA instructions)
The binary loop is loading 88 bytes (22 single precision FP elements).
The binary loop is storing 12 bytes (3 single precision FP elements).


      6.1.2.1.10  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.


      6.1.2.1.11  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)







      6.1.3  -  Loop 1 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/build/HACCmk/src/main.c:116-119.

It is main loop of related source loop which is unrolled by 64 (including vectorization).

      6.1.3.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

33% of peak computational performance is used (32.00 out of 96.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is fully vectorized, using full register length.


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.3.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.3.1.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 64 FMA (fused multiply-add) operations.




      6.1.3.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VMOVUPS: 16 occurrences<<list_path_1_complex_1>>



      6.1.3.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 16 optimal vector unaligned load/store instructions.


Details
 - VMOVUPS: 16 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.3.1.6  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - VCVTDQ2PS (INT32 to FP32, SIMD): 4 occurrences<<list_path_1_cvt_1>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.3.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

28 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).



      6.1.3.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 512 FP arithmetical operations:
 - 448: addition or subtraction (64 inside FMA instructions)
 - 64: multiply (all inside FMA instructions)
The binary loop is storing 1024 bytes (256 single precision FP elements).


      6.1.3.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.







      6.1.4  -  Loop 5 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35.

It is intermediate loop of related source loop which is unrolled by 16 (including vectorization).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.4.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

11% of peak computational performance is used (10.78 out of 96.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Unrolling/vectorization cost
  ----------------------------------------------------------------------------------------------------------

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details
The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround
 - recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
 - hardcode most frequent values of loop bounds by adding specialized paths.:
  *  For instance, replace for (i=0; i<n; i++) foo(i) with:
switch (n) {
  case (4): for (i=0; i<4; i++) foo(i); break;
  case (6): for (i=0; i<6; i++) foo(i); break;
  default : for (i=0; i<n; i++) foo(i); break;
}



      6.1.4.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using 29% register length (average across all SSE/AVX instructions).


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.4.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 11.50 to 9.00 cycles (1.28x speedup).


Workaround
Reduce the number of division or square root instructions:
 - If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast





      6.1.4.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 11.50 to 8.00 cycles (1.44x speedup).


      6.1.4.1.5  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.4.1.6  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 44 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.4.1.7  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - KORTESTB: 1 occurrences<<list_path_1_complex_1>>
 - VCVTPD2PS: 1 occurrences<<list_path_1_complex_2>>
 - VCVTPS2PD: 2 occurrences<<list_path_1_complex_3>>



      6.1.4.1.8  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - VCVTPD2PS (FP64 to FP32, SIMD): 1 occurrences<<list_path_1_cvt_1>>
 - VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.


      6.1.4.1.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

18 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time).
4 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.4.1.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 124 FP arithmetical operations:
 - 60: addition or subtraction (44 inside FMA instructions)
 - 56: multiply (44 inside FMA instructions)
 - 4: divide
 - 4: square root
The binary loop is loading 64 bytes (16 single precision FP elements).


      6.1.4.1.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 1.94 FP operations per loaded or stored byte.




      6.1.4.2  -  Path 2
  ----------------------------------------------------------------------------------------------------------

11% of peak computational performance is used (10.78 out of 96.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.2.1  -  Unrolling/vectorization cost
  ----------------------------------------------------------------------------------------------------------

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details
The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround
 - recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
 - hardcode most frequent values of loop bounds by adding specialized paths.:
  *  For instance, replace for (i=0; i<n; i++) foo(i) with:
switch (n) {
  case (4): for (i=0; i<4; i++) foo(i); break;
  case (6): for (i=0; i<6; i++) foo(i); break;
  default : for (i=0; i<n; i++) foo(i); break;
}



      6.1.4.2.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using 29% register length (average across all SSE/AVX instructions).


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.4.2.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 11.50 to 9.00 cycles (1.28x speedup).


Workaround
Reduce the number of division or square root instructions:
 - If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast





      6.1.4.2.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 11.50 to 8.00 cycles (1.44x speedup).


      6.1.4.2.5  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.4.2.6  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 44 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.4.2.7  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - KORTESTB: 1 occurrences<<list_path_2_complex_1>>
 - VCVTPD2PS: 1 occurrences<<list_path_2_complex_2>>
 - VCVTPS2PD: 2 occurrences<<list_path_2_complex_3>>



      6.1.4.2.8  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - VCVTPD2PS (FP64 to FP32, SIMD): 1 occurrences<<list_path_2_cvt_1>>
 - VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences<<list_path_2_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.


      6.1.4.2.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

18 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time).
4 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.4.2.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 124 FP arithmetical operations:
 - 60: addition or subtraction (44 inside FMA instructions)
 - 56: multiply (44 inside FMA instructions)
 - 4: divide
 - 4: square root
The binary loop is loading 48 bytes (12 single precision FP elements).


      6.1.4.2.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 2.58 FP operations per loaded or stored byte.





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/run/oneview_runs/compilers/aocc_6/oneview_run_1786546388"
[MAQAO] Info: 
