Function: main | Module: exec | Source: main.c:50-191 [...] | Coverage: 0.19% |
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Function: main | Module: exec | Source: main.c:50-191 [...] | Coverage: 0.19% |
---|
/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c: 50 - 191 |
-------------------------------------------------------------------------------- |
50: { |
[...] |
73: printf( "count is set %d\n", count ); |
74: printf( "Total MPI ranks %d\n", nprocs ); |
75: } |
76: |
77: if (argc == 2 && strncmp(argv[1], "-s", 2) == 0) |
78: NN = 15000; |
79: |
80: printf( "N is set %ld\n", NN ); |
81: |
82: #pragma omp parallel |
[...] |
97: for ( n = 400; n < NN; n = n + 20 ) |
[...] |
103: dx1 = 1.0f/(float)n; |
104: dy1 = 2.0f/(float)n; |
105: dz1 = 3.0f/(float)n; |
106: xx[0] = 0.f; |
107: yy[0] = 0.f; |
108: zz[0] = 0.f; |
109: mass[0] = 2.f; |
110: |
111: for ( i = 1; i < n; i++ ) |
112: { |
113: xx[i] = xx[i-1] + dx1; |
114: yy[i] = yy[i-1] + dy1; |
115: zz[i] = zz[i-1] + dz1; |
116: mass[i] = (float)i * 0.01f + xx[i]; |
117: } |
118: |
119: for ( i = 0; i < n; i++ ) |
120: { |
121: vx1[i] = 0.f; |
122: vy1[i] = 0.f; |
123: vz1[i] = 0.f; |
[...] |
136: t1 = mysecond(); |
137: #endif |
138: |
139: #pragma omp parallel for private( dx1, dy1, dz1 ) |
[...] |
152: t2 = mysecond(); |
[...] |
166: t3 = (t2 - t1) * 1e6; |
167: #endif |
168: |
169: elapsed = elapsed + t3; |
[...] |
185: printf( "\nKernel elapsed time, s: %18.8lf\n", elapsed*1e-6 ); |
[...] |
191: return 0; |
0x401520 PUSH %RBP |
0x401521 MOV %RSP,%RBP |
0x401524 PUSH %R15 |
0x401526 PUSH %R14 |
0x401528 PUSH %R13 |
0x40152a PUSH %R12 |
0x40152c PUSH %RBX |
0x40152d SUB $0x18,%RSP |
0x401531 VSTMXCSR -0x2c(%RBP) |
0x401536 MOV %RSI,%R14 |
0x401539 MOV %EDI,%R15D |
0x40153c MOV $0x408090,%EDI |
0x401541 MOV $0xbb8,%ESI |
0x401546 XOR %EAX,%EAX |
0x401548 ORL $0x8040,-0x2c(%RBP) |
0x40154f VLDMXCSR -0x2c(%RBP) |
0x401554 CALL 401030 <printf@plt> |
0x401559 MOV $0x4080a1,%EDI |
0x40155e MOV $0x1,%ESI |
0x401563 XOR %EAX,%EAX |
0x401565 CALL 401030 <printf@plt> |
0x40156a MOV $0x186a0,%EBX |
0x40156f CMP $0x2,%R15D |
0x401573 JNE 401593 |
0x401575 MOV 0x8(%R14),%RDI |
0x401579 MOV $0x4080b5,%ESI |
0x40157e MOV $0x2,%EDX |
0x401583 CALL 4010a0 <strncmp@plt> |
0x401588 TEST %EAX,%EAX |
0x40158a MOV $0x3a98,%EAX |
0x40158f CMOVE %RAX,%RBX |
0x401593 MOV $0x4080b8,%EDI |
0x401598 MOV %RBX,%RSI |
0x40159b XOR %EAX,%EAX |
0x40159d CALL 401030 <printf@plt> |
0x4015a2 MOV $0x40c0c0,%EDI |
0x4015a7 MOV $0x401920,%EDX |
0x4015ac MOV $0x1,%ESI |
0x4015b1 XOR %ECX,%ECX |
0x4015b3 XOR %EAX,%EAX |
0x4015b5 CALL 4010e0 <__kmpc_fork_call@plt> |
0x4015ba VBROADCASTSS 0x6a50(%RIP),%YMM17 |
0x4015c4 VMOVSS 0x6a48(%RIP),%XMM15 |
0x4015cc VMOVDQU64 0x6a8a(%RIP),%YMM16 |
0x4015d6 ADD $-0x191,%EBX |
0x4015dc MOV $-0x33333333,%R14D |
0x4015e2 VXORPS %XMM0,%XMM0,%XMM0 |
0x4015e6 MOV $0x190,%R15D |
0x4015ec MOV $0x18c,%R12D |
0x4015f2 XOR %R13D,%R13D |
0x4015f5 IMUL %RBX,%R14 |
0x4015f9 SHR $0x24,%R14 |
0x4015fd INC %R14D |
0x401600 JMP 4016d2 |
0x401605 NOPW %CS:(%RAX,%RAX,1) |
(2) 0x401610 MOV $0x592b90,%EDI |
(2) 0x401615 XOR %ESI,%ESI |
(2) 0x401617 MOV %RBX,%RDX |
(2) 0x40161a VZEROUPPER |
(2) 0x40161d CALL 401fb0 <_intel_fast_memset> |
(2) 0x401622 MOV $0x5f4610,%EDI |
(2) 0x401627 XOR %ESI,%ESI |
(2) 0x401629 MOV %RBX,%RDX |
(2) 0x40162c CALL 401fb0 <_intel_fast_memset> |
(2) 0x401631 MOV $0x656090,%EDI |
(2) 0x401636 XOR %ESI,%ESI |
(2) 0x401638 MOV %RBX,%RDX |
(2) 0x40163b CALL 401fb0 <_intel_fast_memset> |
(2) 0x401640 XOR %EAX,%EAX |
(2) 0x401642 CALL 401ac0 <mysecond> |
(2) 0x401647 VMOVSD %XMM0,-0x38(%RBP) |
(2) 0x40164c SUB $0x8,%RSP |
(2) 0x401650 MOV $0x40c120,%EDI |
(2) 0x401655 MOV $0x401950,%EDX |
(2) 0x40165a MOV $0x3e6b851f,%ECX |
(2) 0x40165f MOV $0x3f000000,%R8D |
(2) 0x401665 MOV $0x3cf5c28f,%R9D |
(2) 0x40166b MOV $0x6,%ESI |
(2) 0x401670 XOR %EAX,%EAX |
(2) 0x401672 PUSH $0xbb7 |
(2) 0x401677 PUSH $0 |
(2) 0x401679 PUSH %R15 |
(2) 0x40167b CALL 4010e0 <__kmpc_fork_call@plt> |
(2) 0x401680 ADD $0x20,%RSP |
(2) 0x401684 XOR %EAX,%EAX |
(2) 0x401686 CALL 401ac0 <mysecond> |
(2) 0x40168b VSUBSD -0x38(%RBP),%XMM0,%XMM0 |
(2) 0x401690 VMOVSD -0x40(%RBP),%XMM1 |
(2) 0x401695 VBROADCASTSS 0x6975(%RIP),%YMM17 |
(2) 0x40169f VMOVSS 0x696d(%RIP),%XMM15 |
(2) 0x4016a7 VMOVDQU64 0x69af(%RIP),%YMM16 |
(2) 0x4016b1 ADD $0x14,%R15 |
(2) 0x4016b5 INC %R13 |
(2) 0x4016b8 ADD $0x14,%R12 |
(2) 0x4016bc VFMADD231SD 0x69bb(%RIP),%XMM0,%XMM1 |
(2) 0x4016c5 VMOVAPD %XMM1,%XMM0 |
(2) 0x4016c9 CMP %R14,%R13 |
(2) 0x4016cc JE 4018fa |
(2) 0x4016d2 VMOVSS 0x6936(%RIP),%XMM1 |
(2) 0x4016da VMOVSD %XMM0,-0x40(%RBP) |
(2) 0x4016df VCVTSI2SS %R15D,%XMM18,%XMM0 |
(2) 0x4016e5 LEA (%R13,%R13,4),%RBX |
(2) 0x4016ea MOV %R12,%RAX |
(2) 0x4016ed SHR $0x3,%RAX |
(2) 0x4016f1 MOV %R12D,%EDX |
(2) 0x4016f4 MOV %R12,%RCX |
(2) 0x4016f7 AND $-0x8,%RCX |
(2) 0x4016fb AND $0x7,%EDX |
(2) 0x4016fe LEA -0x1(%R15),%RSI |
(2) 0x401702 VXORPS %XMM3,%XMM3,%XMM3 |
(2) 0x401706 VXORPS %XMM2,%XMM2,%XMM2 |
(2) 0x40170a MOV $-0x3,%RDI |
(2) 0x401711 MOVL $0,0xaa75(%RIP) |
(2) 0x40171b MOVL $0,0x6c4eb(%RIP) |
(2) 0x401725 MOVL $0,0xcdf61(%RIP) |
(2) 0x40172f MOVL $0x40000000,0x12f9d7(%RIP) |
(2) 0x401739 SAL $0x5,%RAX |
(2) 0x40173d SAL $0x4,%RBX |
(2) 0x401741 ADD $0x640,%RBX |
(2) 0x401748 VDIVSS %XMM0,%XMM1,%XMM0 |
(2) 0x40174c VBROADCASTSS %XMM0,%XMM1 |
(2) 0x401751 VMULPS 0x68d7(%RIP),%XMM1,%XMM1 |
(2) 0x401759 NOPL (%RAX) |
(0) 0x401760 LEA 0x4(%RDI),%R8D |
(0) 0x401764 VADDSS %XMM0,%XMM2,%XMM2 |
(0) 0x401768 VADDPS %XMM1,%XMM3,%XMM3 |
(0) 0x40176c VCVTSI2SS %R8D,%XMM18,%XMM4 |
(0) 0x401772 VMOVSS %XMM2,0x40c1a0(,%RDI,4) |
(0) 0x40177b VEXTRACTPS $0x1,%XMM3,0x46dc20(,%RDI,4) |
(0) 0x401786 VMOVSS %XMM3,0x4cf6a0(,%RDI,4) |
(0) 0x40178f VFMADD132SS %XMM15,%XMM2,%XMM4 |
(0) 0x401794 VMOVSS %XMM4,0x531120(,%RDI,4) |
(0) 0x40179d INC %RDI |
(0) 0x4017a0 JNE 401760 |
(2) 0x4017a2 VMOVSS 0x686e(%RIP),%XMM13 |
(2) 0x4017aa VMOVUPS 0x688e(%RIP),%YMM9 |
(2) 0x4017b2 VMOVSHDUP %XMM1,%XMM6 |
(2) 0x4017b6 VMOVSHDUP %XMM3,%XMM8 |
(2) 0x4017ba VBROADCASTSS %XMM0,%YMM4 |
(2) 0x4017bf VBROADCASTSS %XMM2,%YMM10 |
(2) 0x4017c4 VBROADCASTSS %XMM3,%YMM12 |
(2) 0x4017c9 LEA -0x4(%R15),%R8 |
(2) 0x4017cd MOV $0x3,%R9D |
(2) 0x4017d3 VBROADCASTSD %XMM8,%YMM11 |
(2) 0x4017d8 VBROADCASTSD %XMM6,%YMM5 |
(2) 0x4017dd AND $-0x8,%R8 |
(2) 0x4017e1 LEA 0x3(%R8),%RDI |
(2) 0x4017e5 OR $0x2,%R8 |
(2) 0x4017e9 VMULSS %XMM6,%XMM13,%XMM8 |
(2) 0x4017ed VBROADCASTSS %XMM1,%YMM6 |
(2) 0x4017f2 VMULSS %XMM0,%XMM13,%XMM7 |
(2) 0x4017f6 VFMADD231PS %YMM9,%YMM4,%YMM10 |
(2) 0x4017fb VFMADD231PS %YMM9,%YMM5,%YMM11 |
(2) 0x401800 VFMADD231PS %YMM9,%YMM6,%YMM12 |
(2) 0x401805 VMULSS %XMM1,%XMM13,%XMM9 |
(2) 0x401809 VBROADCASTSS %XMM7,%YMM7 |
(2) 0x40180e VBROADCASTSS %XMM8,%YMM8 |
(2) 0x401813 VBROADCASTSS %XMM9,%YMM9 |
(2) 0x401818 NOPL (%RAX,%RAX,1) |
(1) 0x401820 VADDPS %YMM5,%YMM11,%YMM14 |
(1) 0x401824 VADDPS %YMM4,%YMM10,%YMM13 |
(1) 0x401828 VADDPS %YMM7,%YMM10,%YMM10 |
(1) 0x40182c VADDPS %YMM8,%YMM11,%YMM11 |
(1) 0x401831 VMOVUPS %YMM14,0x46dc14(,%R9,4) |
(1) 0x40183b VADDPS %YMM6,%YMM12,%YMM14 |
(1) 0x40183f VADDPS %YMM9,%YMM12,%YMM12 |
(1) 0x401844 VMOVUPS %YMM13,0x40c194(,%R9,4) |
(1) 0x40184e VMOVUPS %YMM14,0x4cf694(,%R9,4) |
(1) 0x401858 VPBROADCASTD %R9D,%YMM14 |
(1) 0x40185e VPADDD %YMM16,%YMM14,%YMM14 |
(1) 0x401864 VCVTDQ2PS %YMM14,%YMM14 |
(1) 0x401869 VFMADD132PS %YMM17,%YMM13,%YMM14 |
(1) 0x40186f VMOVUPS %YMM14,0x531114(,%R9,4) |
(1) 0x401879 ADD $0x8,%R9 |
(1) 0x40187d CMP %R8,%R9 |
(1) 0x401880 JLE 401820 |
(2) 0x401882 CMP %RDI,%RSI |
(2) 0x401885 JE 401610 |
(2) 0x40188b VCVTSI2SS %RDI,%XMM18,%XMM4 |
(2) 0x401891 VADDSS 0x6783(%RIP),%XMM4,%XMM5 |
(2) 0x401899 XOR %ESI,%ESI |
(2) 0x40189b VBROADCASTSS %XMM5,%XMM4 |
(2) 0x4018a0 VFMADD231SS %XMM5,%XMM0,%XMM2 |
(2) 0x4018a5 VFMADD213PS %XMM3,%XMM1,%XMM4 |
(2) 0x4018aa NOPW (%RAX,%RAX,1) |
(3) 0x4018b0 LEA 0x4(%RCX,%RSI,1),%EDI |
(3) 0x4018b4 VADDSS %XMM0,%XMM2,%XMM2 |
(3) 0x4018b8 VADDPS %XMM1,%XMM4,%XMM4 |
(3) 0x4018bc VCVTSI2SS %EDI,%XMM18,%XMM3 |
(3) 0x4018c2 VMOVSS %XMM2,0x40c1a0(%RAX,%RSI,4) |
(3) 0x4018cb VEXTRACTPS $0x1,%XMM4,0x46dc20(%RAX,%RSI,4) |
(3) 0x4018d6 VMOVSS %XMM4,0x4cf6a0(%RAX,%RSI,4) |
(3) 0x4018df VFMADD132SS %XMM15,%XMM2,%XMM3 |
(3) 0x4018e4 VMOVSS %XMM3,0x531120(%RAX,%RSI,4) |
(3) 0x4018ed INC %RSI |
(3) 0x4018f0 CMP %RSI,%RDX |
(3) 0x4018f3 JNE 4018b0 |
(2) 0x4018f5 JMP 401610 |
0x4018fa VMULSD 0x6786(%RIP),%XMM0,%XMM0 |
0x401902 MOV $0x4080e1,%EDI |
0x401907 MOV $0x1,%AL |
0x401909 CALL 401030 <printf@plt> |
0x40190e XOR %EAX,%EAX |
0x401910 ADD $0x18,%RSP |
0x401914 POP %RBX |
0x401915 POP %R12 |
0x401917 POP %R13 |
0x401919 POP %R14 |
0x40191b POP %R15 |
0x40191d POP %RBP |
0x40191e RET |
0x40191f NOP |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __libc_start_call_main | libc.so.6 |
Path / |
Source file and lines | main.c:50-191 |
Module | exec |
nb instructions | 69 |
nb uops | 75 |
loop length | 278 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 2 |
used zmm registers | 0 |
nb stack references | 1 |
micro-operation queue | 12.50 cycles |
front end | 12.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.00 | 8.00 | 7.75 | 7.75 | 4.50 | 4.33 | 4.33 | 4.33 | 1.50 | 1.50 | 0.00 | 0.00 | 0.50 | 0.50 |
cycles | 8.00 | 8.00 | 7.75 | 7.75 | 4.50 | 4.33 | 4.33 | 4.33 | 1.50 | 1.50 | 0.00 | 0.00 | 0.50 | 0.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 12.50 |
Dispatch | 8.00 |
Overall L1 | 12.50 |
all | 4% |
load | 33% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 25% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 6% |
load | 16% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 4% |
all | 8% |
load | 22% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 12% |
load | 8% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
all | 9% |
load | 15% |
store | 6% |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput | Vectorization |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
SUB $0x18,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
VSTMXCSR -0x2c(%RBP) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 20 | 15 | N/A |
MOV %RSI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
MOV %EDI,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (6.3%) |
MOV $0x408090,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0xbb8,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
ORL $0x8040,-0x2c(%RBP) | 2 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
VLDMXCSR -0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 2 | N/A |
CALL 401030 <printf@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV $0x4080a1,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x1,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
CALL 401030 <printf@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV $0x186a0,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
CMP $0x2,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
JNE 401593 <main+0x73> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV 0x8(%R14),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV $0x4080b5,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x2,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
CALL 4010a0 <strncmp@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
TEST %EAX,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x3a98,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
CMOVE %RAX,%RBX | 1 | 0.50 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV $0x4080b8,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV %RBX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (12.5%) |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
CALL 401030 <printf@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV $0x40c0c0,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x401920,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x1,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
CALL 4010e0 <__kmpc_fork_call@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
VBROADCASTSS 0x6a50(%RIP),%YMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (6.3%) |
VMOVSS 0x6a48(%RIP),%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
VMOVDQU64 0x6a8a(%RIP),%YMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
ADD $-0x191,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $-0x33333333,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
MOV $0x190,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x18c,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
IMUL %RBX,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
SHR $0x24,%R14 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
INC %R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
JMP 4016d2 <main+0x1b2> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
VMULSD 0x6786(%RIP),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
MOV $0x4080e1,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x1,%AL | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
CALL 401030 <printf@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
ADD $0x18,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
Source file and lines | main.c:50-191 |
Module | exec |
nb instructions | 69 |
nb uops | 75 |
loop length | 278 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 2 |
used zmm registers | 0 |
nb stack references | 1 |
micro-operation queue | 12.50 cycles |
front end | 12.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.00 | 8.00 | 7.75 | 7.75 | 4.50 | 4.33 | 4.33 | 4.33 | 1.50 | 1.50 | 0.00 | 0.00 | 0.50 | 0.50 |
cycles | 8.00 | 8.00 | 7.75 | 7.75 | 4.50 | 4.33 | 4.33 | 4.33 | 1.50 | 1.50 | 0.00 | 0.00 | 0.50 | 0.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 12.50 |
Dispatch | 8.00 |
Overall L1 | 12.50 |
all | 4% |
load | 33% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 25% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 6% |
load | 16% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 4% |
all | 8% |
load | 22% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 12% |
load | 8% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
all | 9% |
load | 15% |
store | 6% |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput | Vectorization |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
SUB $0x18,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
VSTMXCSR -0x2c(%RBP) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 20 | 15 | N/A |
MOV %RSI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
MOV %EDI,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (6.3%) |
MOV $0x408090,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0xbb8,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
ORL $0x8040,-0x2c(%RBP) | 2 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
VLDMXCSR -0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 2 | N/A |
CALL 401030 <printf@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV $0x4080a1,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x1,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
CALL 401030 <printf@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV $0x186a0,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
CMP $0x2,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
JNE 401593 <main+0x73> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV 0x8(%R14),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV $0x4080b5,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x2,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
CALL 4010a0 <strncmp@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
TEST %EAX,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x3a98,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
CMOVE %RAX,%RBX | 1 | 0.50 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV $0x4080b8,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV %RBX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (12.5%) |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
CALL 401030 <printf@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV $0x40c0c0,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x401920,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x1,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
CALL 4010e0 <__kmpc_fork_call@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
VBROADCASTSS 0x6a50(%RIP),%YMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (6.3%) |
VMOVSS 0x6a48(%RIP),%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
VMOVDQU64 0x6a8a(%RIP),%YMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
ADD $-0x191,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $-0x33333333,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
MOV $0x190,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x18c,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
IMUL %RBX,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
SHR $0x24,%R14 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
INC %R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
JMP 4016d2 <main+0x1b2> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
VMULSD 0x6786(%RIP),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
MOV $0x4080e1,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x1,%AL | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
CALL 401030 <printf@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
ADD $0x18,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
Name | Coverage (%) | Time (s) |
---|---|---|
▼main– | 0.19 | 0.02 |
▼Loop 2 - main.c:77-169 - exec– | 0.00 | 0.00 |
○Loop 1 - main.c:111-116 - exec | 0.19 | 2.87 |
○Loop 3 - main.c:111-116 - exec | 0.00 | 0.00 |
○Loop 0 - main.c:111-116 - exec | 0.00 | 0.00 |