Function: main | Module: exec | Source: main.c:50-191 [...] | Coverage: 0.05% |
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Function: main | Module: exec | Source: main.c:50-191 [...] | Coverage: 0.05% |
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/home/eoseret/qaas_runs_CPU_9468/171-112-4218/intel/HACCmk/build/HACCmk/src/main.c: 50 - 191 |
-------------------------------------------------------------------------------- |
50: { |
[...] |
73: printf( "count is set %d\n", count ); |
74: printf( "Total MPI ranks %d\n", nprocs ); |
75: } |
76: |
77: if (argc == 2 && strncmp(argv[1], "-s", 2) == 0) |
78: NN = 15000; |
79: |
80: printf( "N is set %ld\n", NN ); |
81: |
82: #pragma omp parallel |
[...] |
97: for ( n = 400; n < NN; n = n + 20 ) |
[...] |
103: dx1 = 1.0f/(float)n; |
104: dy1 = 2.0f/(float)n; |
105: dz1 = 3.0f/(float)n; |
106: xx[0] = 0.f; |
107: yy[0] = 0.f; |
108: zz[0] = 0.f; |
109: mass[0] = 2.f; |
110: |
111: for ( i = 1; i < n; i++ ) |
112: { |
113: xx[i] = xx[i-1] + dx1; |
114: yy[i] = yy[i-1] + dy1; |
115: zz[i] = zz[i-1] + dz1; |
116: mass[i] = (float)i * 0.01f + xx[i]; |
117: } |
118: |
119: for ( i = 0; i < n; i++ ) |
120: { |
121: vx1[i] = 0.f; |
122: vy1[i] = 0.f; |
123: vz1[i] = 0.f; |
[...] |
136: t1 = mysecond(); |
137: #endif |
138: |
139: #pragma omp parallel for private( dx1, dy1, dz1 ) |
[...] |
152: t2 = mysecond(); |
[...] |
166: t3 = (t2 - t1) * 1e6; |
167: #endif |
168: |
169: elapsed = elapsed + t3; |
[...] |
185: printf( "\nKernel elapsed time, s: %18.8lf\n", elapsed*1e-6 ); |
[...] |
191: return 0; |
0x401530 PUSH %RBP |
0x401531 MOV %RSP,%RBP |
0x401534 PUSH %R15 |
0x401536 PUSH %R14 |
0x401538 PUSH %R13 |
0x40153a PUSH %R12 |
0x40153c PUSH %RBX |
0x40153d SUB $0x18,%RSP |
0x401541 MOV %RSI,%R14 |
0x401544 MOV %EDI,%R15D |
0x401547 MOV $0x10111ce4199d9fee,%RSI |
0x401551 MOV $0x3,%EDI |
0x401556 CALL 402270 <__intel_new_feature_proc_init> |
0x40155b MOV $0x406090,%EDI |
0x401560 MOV $0xbb8,%ESI |
0x401565 XOR %EAX,%EAX |
0x401567 CALL 401030 <printf@plt> |
0x40156c MOV $0x4060a1,%EDI |
0x401571 MOV $0x1,%ESI |
0x401576 XOR %EAX,%EAX |
0x401578 CALL 401030 <printf@plt> |
0x40157d MOV $0x186a0,%EBX |
0x401582 CMP $0x2,%R15D |
0x401586 JNE 4015a6 |
0x401588 MOV 0x8(%R14),%RDI |
0x40158c MOV $0x4060b5,%ESI |
0x401591 MOV $0x2,%EDX |
0x401596 CALL 4010b0 <strncmp@plt> |
0x40159b TEST %EAX,%EAX |
0x40159d MOV $0x3a98,%EAX |
0x4015a2 CMOVE %RAX,%RBX |
0x4015a6 MOV $0x4060b8,%EDI |
0x4015ab MOV %RBX,%RSI |
0x4015ae XOR %EAX,%EAX |
0x4015b0 CALL 401030 <printf@plt> |
0x4015b5 MOV $0x40a0e0,%EDI |
0x4015ba MOV $0x401940,%EDX |
0x4015bf MOV $0x1,%ESI |
0x4015c4 XOR %ECX,%ECX |
0x4015c6 XOR %EAX,%EAX |
0x4015c8 CALL 401100 <__kmpc_fork_call@plt> |
0x4015cd ADD $-0x191,%EBX |
0x4015d3 MOV $-0x33333333,%R14D |
0x4015d9 IMUL %RBX,%R14 |
0x4015dd SHR $0x24,%R14 |
0x4015e1 INC %R14D |
0x4015e4 VXORPS %XMM0,%XMM0,%XMM0 |
0x4015e8 MOV $0x190,%R15D |
0x4015ee MOV $0x18c,%R12D |
0x4015f4 VMOVSS 0x4a18(%RIP),%XMM15 |
0x4015fc VMOVDQU64 0x4a5a(%RIP),%YMM16 |
0x401606 VBROADCASTSS 0x4a04(%RIP),%YMM17 |
0x401610 XOR %R13D,%R13D |
0x401613 JMP 4016e2 |
0x401618 NOPL (%RAX,%RAX,1) |
(2) 0x401620 MOV $0x590bb0,%EDI |
(2) 0x401625 XOR %ESI,%ESI |
(2) 0x401627 MOV %RBX,%RDX |
(2) 0x40162a VZEROUPPER |
(2) 0x40162d CALL 4023c0 <__intel_avx_rep_memset> |
(2) 0x401632 MOV $0x5f2630,%EDI |
(2) 0x401637 XOR %ESI,%ESI |
(2) 0x401639 MOV %RBX,%RDX |
(2) 0x40163c CALL 4023c0 <__intel_avx_rep_memset> |
(2) 0x401641 MOV $0x6540b0,%EDI |
(2) 0x401646 XOR %ESI,%ESI |
(2) 0x401648 MOV %RBX,%RDX |
(2) 0x40164b CALL 4023c0 <__intel_avx_rep_memset> |
(2) 0x401650 XOR %EAX,%EAX |
(2) 0x401652 CALL 401ae0 <mysecond> |
(2) 0x401657 VMOVSD %XMM0,-0x30(%RBP) |
(2) 0x40165c SUB $0x8,%RSP |
(2) 0x401660 MOV $0x40a140,%EDI |
(2) 0x401665 MOV $0x401970,%EDX |
(2) 0x40166a MOV $0x3e6b851f,%ECX |
(2) 0x40166f MOV $0x3f000000,%R8D |
(2) 0x401675 MOV $0x3cf5c28f,%R9D |
(2) 0x40167b MOV $0x6,%ESI |
(2) 0x401680 XOR %EAX,%EAX |
(2) 0x401682 PUSH $0xbb7 |
(2) 0x401687 PUSH $0 |
(2) 0x401689 PUSH %R15 |
(2) 0x40168b CALL 401100 <__kmpc_fork_call@plt> |
(2) 0x401690 ADD $0x20,%RSP |
(2) 0x401694 XOR %EAX,%EAX |
(2) 0x401696 CALL 401ae0 <mysecond> |
(2) 0x40169b VMOVSS 0x4971(%RIP),%XMM15 |
(2) 0x4016a3 VSUBSD -0x30(%RBP),%XMM0,%XMM0 |
(2) 0x4016a8 VMOVSD -0x38(%RBP),%XMM1 |
(2) 0x4016ad VFMADD231SD 0x49ca(%RIP),%XMM0,%XMM1 |
(2) 0x4016b6 VMOVAPD %XMM1,%XMM0 |
(2) 0x4016ba ADD $0x14,%R15 |
(2) 0x4016be INC %R13 |
(2) 0x4016c1 ADD $0x14,%R12 |
(2) 0x4016c5 CMP %R14,%R13 |
(2) 0x4016c8 VMOVDQU64 0x498e(%RIP),%YMM16 |
(2) 0x4016d2 VBROADCASTSS 0x4938(%RIP),%YMM17 |
(2) 0x4016dc JE 40190a |
(2) 0x4016e2 VMOVSD %XMM0,-0x38(%RBP) |
(2) 0x4016e7 LEA (,%R12,4),%RAX |
(2) 0x4016ef AND $-0x20,%RAX |
(2) 0x4016f3 MOV %R12,%RCX |
(2) 0x4016f6 AND $-0x8,%RCX |
(2) 0x4016fa MOV %R12D,%EDX |
(2) 0x4016fd AND $0x7,%EDX |
(2) 0x401700 LEA (%R13,%R13,4),%RBX |
(2) 0x401705 SAL $0x4,%RBX |
(2) 0x401709 ADD $0x640,%RBX |
(2) 0x401710 VCVTSI2SS %R15D,%XMM18,%XMM0 |
(2) 0x401716 VMOVSS 0x48f2(%RIP),%XMM1 |
(2) 0x40171e VDIVSS %XMM0,%XMM1,%XMM0 |
(2) 0x401722 VBROADCASTSS %XMM0,%XMM1 |
(2) 0x401727 VMULPS 0x4901(%RIP),%XMM1,%XMM1 |
(2) 0x40172f MOVL $0,0x8a77(%RIP) |
(2) 0x401739 MOVL $0,0x6a4ed(%RIP) |
(2) 0x401743 MOVL $0,0xcbf63(%RIP) |
(2) 0x40174d MOVL $0x40000000,0x12d9d9(%RIP) |
(2) 0x401757 LEA -0x1(%R15),%RSI |
(2) 0x40175b VXORPS %XMM3,%XMM3,%XMM3 |
(2) 0x40175f VXORPS %XMM2,%XMM2,%XMM2 |
(2) 0x401763 MOV $-0x3,%RDI |
(2) 0x40176a NOPW (%RAX,%RAX,1) |
(0) 0x401770 VADDSS %XMM0,%XMM2,%XMM2 |
(0) 0x401774 VMOVSS %XMM2,0x40a1c0(,%RDI,4) |
(0) 0x40177d VADDPS %XMM1,%XMM3,%XMM3 |
(0) 0x401781 VEXTRACTPS $0x1,%XMM3,0x46bc40(,%RDI,4) |
(0) 0x40178c VMOVSS %XMM3,0x4cd6c0(,%RDI,4) |
(0) 0x401795 LEA 0x4(%RDI),%R8D |
(0) 0x401799 VCVTSI2SS %R8D,%XMM18,%XMM4 |
(0) 0x40179f VFMADD132SS %XMM15,%XMM2,%XMM4 |
(0) 0x4017a4 VMOVSS %XMM4,0x52f140(,%RDI,4) |
(0) 0x4017ad INC %RDI |
(0) 0x4017b0 JNE 401770 |
(2) 0x4017b2 LEA -0x4(%R15),%R8 |
(2) 0x4017b6 AND $-0x8,%R8 |
(2) 0x4017ba LEA 0x3(%R8),%RDI |
(2) 0x4017be VBROADCASTSS %XMM0,%YMM4 |
(2) 0x4017c3 VBROADCASTSS %XMM2,%YMM10 |
(2) 0x4017c8 VMOVUPS 0x4870(%RIP),%YMM9 |
(2) 0x4017d0 VFMADD231PS %YMM9,%YMM4,%YMM10 |
(2) 0x4017d5 VMOVSS 0x483b(%RIP),%XMM13 |
(2) 0x4017dd VMULSS %XMM0,%XMM13,%XMM7 |
(2) 0x4017e1 VMOVSHDUP %XMM1,%XMM6 |
(2) 0x4017e5 VBROADCASTSD %XMM6,%YMM5 |
(2) 0x4017ea VBROADCASTSS 0x4829(%RIP),%YMM8 |
(2) 0x4017f3 VPERMPS %YMM3,%YMM8,%YMM11 |
(2) 0x4017f8 VFMADD231PS %YMM9,%YMM5,%YMM11 |
(2) 0x4017fd VMULSS %XMM6,%XMM13,%XMM8 |
(2) 0x401801 VBROADCASTSS %XMM1,%YMM6 |
(2) 0x401806 VBROADCASTSS %XMM3,%YMM12 |
(2) 0x40180b VFMADD231PS %YMM9,%YMM6,%YMM12 |
(2) 0x401810 VMULSS %XMM1,%XMM13,%XMM9 |
(2) 0x401814 OR $0x2,%R8 |
(2) 0x401818 VBROADCASTSS %XMM7,%YMM7 |
(2) 0x40181d VBROADCASTSS %XMM8,%YMM8 |
(2) 0x401822 VBROADCASTSS %XMM9,%YMM9 |
(2) 0x401827 MOV $0x3,%R9D |
(2) 0x40182d NOPL (%RAX) |
(1) 0x401830 VADDPS %YMM4,%YMM10,%YMM13 |
(1) 0x401834 VADDPS %YMM7,%YMM10,%YMM10 |
(1) 0x401838 VMOVUPS %YMM13,0x40a1b4(,%R9,4) |
(1) 0x401842 VADDPS %YMM5,%YMM11,%YMM14 |
(1) 0x401846 VADDPS %YMM8,%YMM11,%YMM11 |
(1) 0x40184b VMOVUPS %YMM14,0x46bc34(,%R9,4) |
(1) 0x401855 VADDPS %YMM6,%YMM12,%YMM14 |
(1) 0x401859 VADDPS %YMM9,%YMM12,%YMM12 |
(1) 0x40185e VMOVUPS %YMM14,0x4cd6b4(,%R9,4) |
(1) 0x401868 VPBROADCASTD %R9D,%YMM14 |
(1) 0x40186e VPADDD %YMM16,%YMM14,%YMM14 |
(1) 0x401874 VCVTDQ2PS %YMM14,%YMM14 |
(1) 0x401879 VFMADD132PS %YMM17,%YMM13,%YMM14 |
(1) 0x40187f VMOVUPS %YMM14,0x52f134(,%R9,4) |
(1) 0x401889 ADD $0x8,%R9 |
(1) 0x40188d CMP %R8,%R9 |
(1) 0x401890 JLE 401830 |
(2) 0x401892 CMP %RDI,%RSI |
(2) 0x401895 JE 401620 |
(2) 0x40189b VCVTSI2SS %RDI,%XMM18,%XMM4 |
(2) 0x4018a1 VADDSS 0x4777(%RIP),%XMM4,%XMM5 |
(2) 0x4018a9 VBROADCASTSS %XMM5,%XMM4 |
(2) 0x4018ae VFMADD213PS %XMM3,%XMM1,%XMM4 |
(2) 0x4018b3 VFMADD231SS %XMM5,%XMM0,%XMM2 |
(2) 0x4018b8 XOR %ESI,%ESI |
(2) 0x4018ba NOPW (%RAX,%RAX,1) |
(3) 0x4018c0 VADDSS %XMM0,%XMM2,%XMM2 |
(3) 0x4018c4 VMOVSS %XMM2,0x40a1c0(%RAX,%RSI,4) |
(3) 0x4018cd VADDPS %XMM1,%XMM4,%XMM4 |
(3) 0x4018d1 VEXTRACTPS $0x1,%XMM4,0x46bc40(%RAX,%RSI,4) |
(3) 0x4018dc VMOVSS %XMM4,0x4cd6c0(%RAX,%RSI,4) |
(3) 0x4018e5 LEA 0x4(%RCX,%RSI,1),%EDI |
(3) 0x4018e9 VCVTSI2SS %EDI,%XMM18,%XMM3 |
(3) 0x4018ef VFMADD132SS %XMM15,%XMM2,%XMM3 |
(3) 0x4018f4 VMOVSS %XMM3,0x52f140(%RAX,%RSI,4) |
(3) 0x4018fd INC %RSI |
(3) 0x401900 CMP %RSI,%RDX |
(3) 0x401903 JNE 4018c0 |
(2) 0x401905 JMP 401620 |
0x40190a VMULSD 0x4776(%RIP),%XMM0,%XMM0 |
0x401912 MOV $0x1,%EAX |
0x401917 MOV $0x4060e1,%EDI |
0x40191c CALL 401030 <printf@plt> |
0x401921 XOR %EAX,%EAX |
0x401923 ADD $0x18,%RSP |
0x401927 POP %RBX |
0x401928 POP %R12 |
0x40192a POP %R13 |
0x40192c POP %R14 |
0x40192e POP %R15 |
0x401930 POP %RBP |
0x401931 RET |
0x401932 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | main.c:50-191 |
Module | exec |
nb instructions | 69 |
nb uops | 76 |
loop length | 294 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 2 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.90 | 5.70 | 4.00 | 4.00 | 6.50 | 5.80 | 5.80 | 6.50 | 6.50 | 6.50 | 5.80 | 4.00 |
cycles | 5.90 | 5.70 | 4.00 | 4.00 | 6.50 | 5.80 | 5.80 | 6.50 | 6.50 | 6.50 | 5.80 | 4.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 11.62 |
Stall cycles | 0.00 |
Front-end | 12.67 |
Dispatch | 6.50 |
Overall L1 | 12.67 |
all | 3% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 25% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 6% |
load | 20% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 3% |
all | 9% |
load | 31% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 12% |
load | 8% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
all | 9% |
load | 17% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x18,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDI,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x10111ce4199d9fee,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV $0x3,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402270 <__intel_new_feature_proc_init> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x406090,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xbb8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 401030 <printf@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x4060a1,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 401030 <printf@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x186a0,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP $0x2,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 4015a6 <main+0x76> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x8(%R14),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x4060b5,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4010b0 <strncmp@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
TEST %EAX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $0x3a98,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVE %RAX,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV $0x4060b8,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 401030 <printf@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x40a0e0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x401940,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 401100 <__kmpc_fork_call@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $-0x191,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $-0x33333333,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
IMUL %RBX,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SHR $0x24,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
INC %R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x190,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x18c,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSS 0x4a18(%RIP),%XMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDQU64 0x4a5a(%RIP),%YMM16 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VBROADCASTSS 0x4a04(%RIP),%YMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4016e2 <main+0x1b2> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMULSD 0x4776(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOV $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x4060e1,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 401030 <printf@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x18,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | main.c:50-191 |
Module | exec |
nb instructions | 69 |
nb uops | 76 |
loop length | 294 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 2 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.90 | 5.70 | 4.00 | 4.00 | 6.50 | 5.80 | 5.80 | 6.50 | 6.50 | 6.50 | 5.80 | 4.00 |
cycles | 5.90 | 5.70 | 4.00 | 4.00 | 6.50 | 5.80 | 5.80 | 6.50 | 6.50 | 6.50 | 5.80 | 4.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 11.62 |
Stall cycles | 0.00 |
Front-end | 12.67 |
Dispatch | 6.50 |
Overall L1 | 12.67 |
all | 3% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 25% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 6% |
load | 20% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 3% |
all | 9% |
load | 31% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 12% |
load | 8% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
all | 9% |
load | 17% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x18,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDI,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x10111ce4199d9fee,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV $0x3,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402270 <__intel_new_feature_proc_init> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x406090,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xbb8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 401030 <printf@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x4060a1,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 401030 <printf@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x186a0,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP $0x2,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 4015a6 <main+0x76> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x8(%R14),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x4060b5,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4010b0 <strncmp@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
TEST %EAX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $0x3a98,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVE %RAX,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV $0x4060b8,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 401030 <printf@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x40a0e0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x401940,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 401100 <__kmpc_fork_call@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $-0x191,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $-0x33333333,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
IMUL %RBX,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SHR $0x24,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
INC %R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x190,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x18c,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSS 0x4a18(%RIP),%XMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDQU64 0x4a5a(%RIP),%YMM16 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VBROADCASTSS 0x4a04(%RIP),%YMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4016e2 <main+0x1b2> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMULSD 0x4776(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOV $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x4060e1,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 401030 <printf@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x18,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼main– | 0.05 | 0.01 |
▼Loop 2 - main.c:77-169 - exec– | 0 | 0 |
○Loop 1 - main.c:111-116 - exec | 0.05 | 0.9 |
○Loop 3 - main.c:111-116 - exec | 0 | 0 |
○Loop 0 - main.c:111-116 - exec | 0 | 0 |