Loop Id: 0 | Module: exec | Source: main.c:111-116 | Coverage: 0.06% |
---|
Loop Id: 0 | Module: exec | Source: main.c:111-116 | Coverage: 0.06% |
---|
0x401291 VADDSS %XMM10,%XMM0,%XMM14 |
0x401296 VADDSS %XMM6,%XMM2,%XMM15 |
0x40129a LEA 0x2(%R14),%RSI |
0x40129e VADDSS %XMM11,%XMM1,%XMM3 |
0x4012a3 LEA 0x1(%R14),%RCX |
0x4012a7 LEA 0x3(%R14),%RDI |
0x4012ab VADDSS %XMM10,%XMM14,%XMM12 |
0x4012b0 VMOVSS %XMM15,0x5ed500(,%R14,4) [1] |
0x4012ba VADDSS %XMM6,%XMM15,%XMM2 |
0x4012be VCVTSI2SS %ESI,%XMM7,%XMM15 |
0x4012c2 VMOVSS %XMM3,0x64ef80(,%R14,4) [1] |
0x4012cc VADDSS %XMM11,%XMM3,%XMM1 |
0x4012d1 VCVTSI2SS %R14D,%XMM7,%XMM5 |
0x4012d6 VMOVSS %XMM14,0x58ba80(,%R14,4) [1] |
0x4012e0 VADDSS %XMM10,%XMM12,%XMM0 |
0x4012e5 VMOVSS %XMM12,0x58ba80(,%RCX,4) [2] |
0x4012ee VADDSS %XMM6,%XMM2,%XMM13 |
0x4012f2 VCVTSI2SS %ECX,%XMM7,%XMM4 |
0x4012f6 VMOVSS %XMM2,0x5ed500(,%RCX,4) [2] |
0x4012ff VCVTSI2SS %EDI,%XMM7,%XMM3 |
0x401303 VMOVSS %XMM1,0x64ef80(,%RCX,4) [2] |
0x40130c VFMADD132SS %XMM8,%XMM0,%XMM15 |
0x401311 VMOVSS %XMM0,0x58ba80(,%RSI,4) [2] |
0x40131a VADDSS %XMM10,%XMM0,%XMM0 |
0x40131f VADDSS %XMM6,%XMM13,%XMM2 |
0x401323 VFMADD132SS %XMM8,%XMM14,%XMM5 |
0x401328 VADDSS %XMM11,%XMM1,%XMM14 |
0x40132d VMOVSS %XMM13,0x5ed500(,%RSI,4) [2] |
0x401336 VFMADD132SS %XMM8,%XMM12,%XMM4 |
0x40133b VFMADD132SS %XMM8,%XMM0,%XMM3 |
0x401340 VMOVSS %XMM0,0x58ba80(,%RDI,4) [2] |
0x401349 VADDSS %XMM11,%XMM14,%XMM1 |
0x40134e VMOVSS %XMM14,0x64ef80(,%RSI,4) [2] |
0x401357 VMOVSS %XMM2,0x5ed500(,%RDI,4) [2] |
0x401360 VMOVSS %XMM5,0x52a000(,%R14,4) [1] |
0x40136a ADD $0x4,%R14 |
0x40136e VMOVSS %XMM4,0x52a000(,%RCX,4) [2] |
0x401377 VMOVSS %XMM1,0x64ef80(,%RDI,4) [2] |
0x401380 VMOVSS %XMM15,0x52a000(,%RSI,4) [2] |
0x401389 VMOVSS %XMM3,0x52a000(,%RDI,4) [2] |
0x401392 CMP %RAX,%R14 |
0x401395 JNE 401291 |
/home/eoseret/qaas_runs_CPU_9468/171-112-4218/intel/HACCmk/build/HACCmk/src/main.c: 111 - 116 |
-------------------------------------------------------------------------------- |
111: for ( i = 1; i < n; i++ ) |
112: { |
113: xx[i] = xx[i-1] + dx1; |
114: yy[i] = yy[i-1] + dy1; |
115: zz[i] = zz[i-1] + dz1; |
116: mass[i] = (float)i * 0.01f + xx[i]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.50 |
CQA speedup if fully vectorized | 16.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.50 |
Bottlenecks | |
Function | main |
Source | main.c:111-116 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.00 |
CQA cycles if no scalar integer | 12.00 |
CQA cycles if FP arith vectorized | 8.00 |
CQA cycles if fully vectorized | 0.75 |
Front-end cycles | 7.50 |
DIV/SQRT cycles | 8.00 |
P0 cycles | 8.00 |
P1 cycles | 0.00 |
P2 cycles | 0.00 |
P3 cycles | 8.00 |
P4 cycles | 8.00 |
P5 cycles | 1.00 |
P6 cycles | 8.00 |
P7 cycles | 8.00 |
P8 cycles | 8.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 12 |
FE+BE cycles (UFS) | 12.11 |
Stall cycles (UFS) | 4.11 |
Nb insns | 42.00 |
Nb uops | 45.00 |
Nb loads | 0.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 1.67 |
Nb FLOP add-sub | 12.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 4.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 5.33 |
Bytes prefetched | 0.00 |
Bytes loaded | 0.00 |
Bytes stored | 64.00 |
Stride 0 | 0.00 |
Stride 1 | 4.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 6.25 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | 6.25 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 6.25 |
Vector-efficiency ratio fma | 6.25 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 6.25 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.50 |
CQA speedup if fully vectorized | 16.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.50 |
Bottlenecks | |
Function | main |
Source | main.c:111-116 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.00 |
CQA cycles if no scalar integer | 12.00 |
CQA cycles if FP arith vectorized | 8.00 |
CQA cycles if fully vectorized | 0.75 |
Front-end cycles | 7.50 |
DIV/SQRT cycles | 8.00 |
P0 cycles | 8.00 |
P1 cycles | 0.00 |
P2 cycles | 0.00 |
P3 cycles | 8.00 |
P4 cycles | 8.00 |
P5 cycles | 1.00 |
P6 cycles | 8.00 |
P7 cycles | 8.00 |
P8 cycles | 8.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 12 |
FE+BE cycles (UFS) | 12.11 |
Stall cycles (UFS) | 4.11 |
Nb insns | 42.00 |
Nb uops | 45.00 |
Nb loads | 0.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 1.67 |
Nb FLOP add-sub | 12.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 4.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 5.33 |
Bytes prefetched | 0.00 |
Bytes loaded | 0.00 |
Bytes stored | 64.00 |
Stride 0 | 0.00 |
Stride 1 | 4.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 6.25 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | 6.25 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 6.25 |
Vector-efficiency ratio fma | 6.25 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 6.25 |
Path / |
Function | main |
Source file and lines | main.c:111-116 |
Module | exec |
nb instructions | 42 |
nb uops | 45 |
loop length | 266 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 15 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 7.50 cycles |
front end | 7.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.00 | 8.00 | 0.00 | 0.00 | 8.00 | 8.00 | 1.00 | 8.00 | 8.00 | 8.00 | 0.00 | 0.00 |
cycles | 8.00 | 8.00 | 0.00 | 0.00 | 8.00 | 8.00 | 1.00 | 8.00 | 8.00 | 8.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 12.00 |
FE+BE cycles | 12.11 |
Stall cycles | 4.11 |
RS full (events) | 10.18 |
Front-end | 7.50 |
Dispatch | 8.00 |
Data deps. | 12.00 |
Overall L1 | 12.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 6% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 6% |
load | NA (no load vectorizable/vectorized instructions) |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 6% |
load | NA (no load vectorizable/vectorized instructions) |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 6% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VADDSS %XMM10,%XMM0,%XMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSS %XMM6,%XMM2,%XMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
LEA 0x2(%R14),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VADDSS %XMM11,%XMM1,%XMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
LEA 0x1(%R14),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3(%R14),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VADDSS %XMM10,%XMM14,%XMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVSS %XMM15,0x5ed500(,%R14,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSS %XMM6,%XMM15,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCVTSI2SS %ESI,%XMM7,%XMM15 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMOVSS %XMM3,0x64ef80(,%R14,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSS %XMM11,%XMM3,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCVTSI2SS %R14D,%XMM7,%XMM5 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMOVSS %XMM14,0x58ba80(,%R14,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSS %XMM10,%XMM12,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVSS %XMM12,0x58ba80(,%RCX,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSS %XMM6,%XMM2,%XMM13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCVTSI2SS %ECX,%XMM7,%XMM4 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMOVSS %XMM2,0x5ed500(,%RCX,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VCVTSI2SS %EDI,%XMM7,%XMM3 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMOVSS %XMM1,0x64ef80(,%RCX,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VFMADD132SS %XMM8,%XMM0,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM0,0x58ba80(,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSS %XMM10,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSS %XMM6,%XMM13,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD132SS %XMM8,%XMM14,%XMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSS %XMM11,%XMM1,%XMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVSS %XMM13,0x5ed500(,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VFMADD132SS %XMM8,%XMM12,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SS %XMM8,%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM0,0x58ba80(,%RDI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSS %XMM11,%XMM14,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVSS %XMM14,0x64ef80(,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS %XMM2,0x5ed500(,%RDI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS %XMM5,0x52a000(,%R14,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD $0x4,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSS %XMM4,0x52a000(,%RCX,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS %XMM1,0x64ef80(,%RDI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS %XMM15,0x52a000(,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS %XMM3,0x52a000(,%RDI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RAX,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 401291 <main+0x1f1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | main |
Source file and lines | main.c:111-116 |
Module | exec |
nb instructions | 42 |
nb uops | 45 |
loop length | 266 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 15 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 7.50 cycles |
front end | 7.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.00 | 8.00 | 0.00 | 0.00 | 8.00 | 8.00 | 1.00 | 8.00 | 8.00 | 8.00 | 0.00 | 0.00 |
cycles | 8.00 | 8.00 | 0.00 | 0.00 | 8.00 | 8.00 | 1.00 | 8.00 | 8.00 | 8.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 12.00 |
FE+BE cycles | 12.11 |
Stall cycles | 4.11 |
RS full (events) | 10.18 |
Front-end | 7.50 |
Dispatch | 8.00 |
Data deps. | 12.00 |
Overall L1 | 12.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 6% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 6% |
load | NA (no load vectorizable/vectorized instructions) |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 6% |
load | NA (no load vectorizable/vectorized instructions) |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 6% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VADDSS %XMM10,%XMM0,%XMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSS %XMM6,%XMM2,%XMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
LEA 0x2(%R14),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VADDSS %XMM11,%XMM1,%XMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
LEA 0x1(%R14),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3(%R14),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VADDSS %XMM10,%XMM14,%XMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVSS %XMM15,0x5ed500(,%R14,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSS %XMM6,%XMM15,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCVTSI2SS %ESI,%XMM7,%XMM15 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMOVSS %XMM3,0x64ef80(,%R14,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSS %XMM11,%XMM3,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCVTSI2SS %R14D,%XMM7,%XMM5 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMOVSS %XMM14,0x58ba80(,%R14,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSS %XMM10,%XMM12,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVSS %XMM12,0x58ba80(,%RCX,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSS %XMM6,%XMM2,%XMM13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCVTSI2SS %ECX,%XMM7,%XMM4 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMOVSS %XMM2,0x5ed500(,%RCX,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VCVTSI2SS %EDI,%XMM7,%XMM3 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMOVSS %XMM1,0x64ef80(,%RCX,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VFMADD132SS %XMM8,%XMM0,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM0,0x58ba80(,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSS %XMM10,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSS %XMM6,%XMM13,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD132SS %XMM8,%XMM14,%XMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSS %XMM11,%XMM1,%XMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVSS %XMM13,0x5ed500(,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VFMADD132SS %XMM8,%XMM12,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SS %XMM8,%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM0,0x58ba80(,%RDI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSS %XMM11,%XMM14,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVSS %XMM14,0x64ef80(,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS %XMM2,0x5ed500(,%RDI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS %XMM5,0x52a000(,%R14,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD $0x4,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSS %XMM4,0x52a000(,%RCX,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS %XMM1,0x64ef80(,%RDI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS %XMM15,0x52a000(,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS %XMM3,0x52a000(,%RDI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RAX,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 401291 <main+0x1f1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |