Function: main.extracted.8 | Module: exec | Source: main.c:139-147 [...] | Coverage: 91.38% |
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Function: main.extracted.8 | Module: exec | Source: main.c:139-147 [...] | Coverage: 91.38% |
---|
/scratch_na/users/xoserete/qaas_runs/171-317-3836/intel/HACCmk/build/HACCmk/src/main.c: 139 - 147 |
-------------------------------------------------------------------------------- |
139: #pragma omp parallel for private( dx1, dy1, dz1 ) |
140: for ( i = 0; i < count; ++i) |
141: { |
142: Step10_orig( n, xx[i], yy[i], zz[i], fsrrmax2, mp_rsm2, xx, yy, zz, mass, &dx1, &dy1, &dz1 ); |
143: |
144: vx1[i] = vx1[i] + dx1 * fcoeff; |
145: vy1[i] = vy1[i] + dy1 * fcoeff; |
146: vz1[i] = vz1[i] + dz1 * fcoeff; |
147: } |
/scratch_na/users/xoserete/qaas_runs/171-317-3836/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 35 |
-------------------------------------------------------------------------------- |
19: for ( j = 0; j < count1; j++ ) |
20: { |
21: dxc = xx1[j] - xxi; |
22: dyc = yy1[j] - yyi; |
23: dzc = zz1[j] - zzi; |
24: |
25: r2 = dxc * dxc + dyc * dyc + dzc * dzc; |
26: |
27: m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f; |
28: |
29: f = pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5))))); |
30: |
31: f = ( r2 > 0.0f ) ? m * f : 0.0f; |
32: |
33: xi = xi + f * dxc; |
34: yi = yi + f * dyc; |
35: zi = zi + f * dzc; |
0x401d20 PUSH %RBP |
0x401d21 MOV %RSP,%RBP |
0x401d24 PUSH %R14 |
0x401d26 PUSH %RBX |
0x401d27 AND $-0x20,%RSP |
0x401d2b SUB $0x60,%RSP |
0x401d2f MOV %R9,%R14 |
0x401d32 MOVL $0,0x1c(%RSP) |
0x401d3a MOV (%RDI),%EBX |
0x401d3c MOVL $0,0x14(%RSP) |
0x401d44 MOVL $0xbb7,0x10(%RSP) |
0x401d4c MOVL $0x1,0x18(%RSP) |
0x401d54 SUB $0x8,%RSP |
0x401d58 LEA 0x20(%RSP),%RAX |
0x401d5d LEA 0x24(%RSP),%RCX |
0x401d62 LEA 0x1c(%RSP),%R8 |
0x401d67 LEA 0x18(%RSP),%R9 |
0x401d6c MOV $0x60b120,%EDI |
0x401d71 MOV %EBX,%ESI |
0x401d73 MOV $0x22,%EDX |
0x401d78 PUSH $0x1 |
0x401d7a PUSH $0x1 |
0x401d7c PUSH %RAX |
0x401d7d CALL 401420 <__kmpc_for_static_init_4@plt> |
0x401d82 ADD $0x20,%RSP |
0x401d86 MOV 0x14(%RSP),%EAX |
0x401d8a MOV 0x10(%RSP),%ECX |
0x401d8e CMP %ECX,%EAX |
0x401d90 JBE 401da9 |
0x401d92 MOV $0x60b140,%EDI |
0x401d97 MOV %EBX,%ESI |
0x401d99 LEA -0x10(%RBP),%RSP |
0x401d9d POP %RBX |
0x401d9e POP %R14 |
0x401da0 POP %RBP |
0x401da1 VZEROUPPER |
0x401da4 JMP 401380 |
0x401da9 MOV %R14D,%EDX |
0x401dac SUB %RAX,%RCX |
0x401daf XOR %EDI,%EDI |
0x401db1 MOV $-0x8,%ESI |
0x401db6 VBROADCASTSS 0x50a5(%RIP),%YMM2 |
0x401dbf VXORPS %XMM3,%XMM3,%XMM3 |
0x401dc3 VBROADCASTSS 0x509c(%RIP),%YMM4 |
0x401dcc VBROADCASTSD 0x515b(%RIP),%YMM5 |
0x401dd5 VBROADCASTSS 0x508e(%RIP),%YMM13 |
0x401dde VBROADCASTSS 0x5089(%RIP),%YMM7 |
0x401de7 VBROADCASTSS 0x5084(%RIP),%YMM8 |
0x401df0 VBROADCASTSS 0x507f(%RIP),%YMM9 |
0x401df9 VBROADCASTSS 0x507a(%RIP),%YMM10 |
0x401e02 VBROADCASTSS 0x5075(%RIP),%YMM11 |
0x401e0b VMOVSS 0x5071(%RIP),%XMM12 |
0x401e13 JMP 401e84 |
0x401e15 NOPW %CS:(%RAX,%RAX,1) |
(4) 0x401e20 VXORPS %XMM16,%XMM16,%XMM16 |
(4) 0x401e26 VXORPS %XMM18,%XMM18,%XMM18 |
(4) 0x401e2c VXORPS %XMM17,%XMM17,%XMM17 |
(4) 0x401e32 VFMADD213SS 0x791bf0(,%R8,4),%XMM12,%XMM17 |
(4) 0x401e3d VMOVSS %XMM17,0x791bf0(,%R8,4) |
(4) 0x401e48 VFMADD213SS 0x7f3670(,%R8,4),%XMM12,%XMM18 |
(4) 0x401e53 VMOVSS %XMM18,0x7f3670(,%R8,4) |
(4) 0x401e5e VFMADD213SS 0x8550f0(,%R8,4),%XMM12,%XMM16 |
(4) 0x401e69 VMOVSS %XMM16,0x8550f0(,%R8,4) |
(4) 0x401e74 LEA 0x1(%RDI),%R8 |
(4) 0x401e78 CMP %RCX,%RDI |
(4) 0x401e7b MOV %R8,%RDI |
(4) 0x401e7e JE 401d92 |
(4) 0x401e84 LEA (%RDI,%RAX,1),%R8 |
(4) 0x401e88 TEST %R14D,%R14D |
(4) 0x401e8b JLE 401e20 |
(4) 0x401e8d VMOVSS 0x60b1f0(,%R8,4),%XMM21 |
(4) 0x401e98 VMOVSS 0x66cc70(,%R8,4),%XMM20 |
(4) 0x401ea3 VMOVSS 0x6ce6f0(,%R8,4),%XMM19 |
(4) 0x401eae MOV %R14,%R9 |
(4) 0x401eb1 AND %RSI,%R9 |
(4) 0x401eb4 JE 402070 |
(4) 0x401eba VBROADCASTSS %XMM21,%YMM22 |
(4) 0x401ec0 VBROADCASTSS %XMM20,%YMM23 |
(4) 0x401ec6 VBROADCASTSS %XMM19,%YMM24 |
(4) 0x401ecc VXORPS %XMM17,%XMM17,%XMM17 |
(4) 0x401ed2 XOR %R10D,%R10D |
(4) 0x401ed5 VXORPS %XMM18,%XMM18,%XMM18 |
(4) 0x401edb VXORPS %XMM16,%XMM16,%XMM16 |
(4) 0x401ee1 NOPW %CS:(%RAX,%RAX,1) |
(5) 0x401ef0 VMOVUPS 0x60b1f0(,%R10,4),%YMM25 |
(5) 0x401efb VSUBPS %YMM22,%YMM25,%YMM25 |
(5) 0x401f01 VMOVUPS 0x66cc70(,%R10,4),%YMM26 |
(5) 0x401f0c VSUBPS %YMM23,%YMM26,%YMM26 |
(5) 0x401f12 VMOVUPS 0x6ce6f0(,%R10,4),%YMM27 |
(5) 0x401f1d VSUBPS %YMM24,%YMM27,%YMM27 |
(5) 0x401f23 VMULPS %YMM25,%YMM25,%YMM28 |
(5) 0x401f29 VFMADD231PS %YMM26,%YMM26,%YMM28 |
(5) 0x401f2f VFMADD231PS %YMM27,%YMM27,%YMM28 |
(5) 0x401f35 VCMPPS $0x1,%YMM2,%YMM28,%K1 |
(5) 0x401f3c VMOVUPS 0x730170(,%R10,4),%YMM29{%K1}{z} |
(5) 0x401f47 VADDPS %YMM4,%YMM28,%YMM30 |
(5) 0x401f4d VEXTRACTF32X4 $0x1,%YMM30,%XMM31 |
(5) 0x401f54 VCVTPS2PD %XMM31,%YMM31 |
(5) 0x401f5a VCVTPS2PD %XMM30,%YMM30 |
(5) 0x401f60 VSQRTPD %YMM30,%YMM0 |
(5) 0x401f66 VSQRTPD %YMM31,%YMM1 |
(5) 0x401f6c VMULPD %YMM30,%YMM30,%YMM30 |
(5) 0x401f72 VDIVPD %YMM30,%YMM5,%YMM30 |
(5) 0x401f78 VMULPD %YMM31,%YMM31,%YMM31 |
(5) 0x401f7e VMOVAPS %YMM13,%YMM6 |
(5) 0x401f82 VFMADD213PS %YMM7,%YMM28,%YMM6 |
(5) 0x401f88 VFMADD213PS %YMM8,%YMM28,%YMM6 |
(5) 0x401f8e VFMADD213PS %YMM9,%YMM28,%YMM6 |
(5) 0x401f94 VFMADD213PS %YMM10,%YMM28,%YMM6 |
(5) 0x401f9a VFMADD213PS %YMM11,%YMM28,%YMM6 |
(5) 0x401fa0 VCVTPS2PD %XMM6,%YMM14 |
(5) 0x401fa4 VDIVPD %YMM31,%YMM5,%YMM31 |
(5) 0x401faa VFMADD231PD %YMM30,%YMM0,%YMM14 |
(5) 0x401fb0 VEXTRACTF128 $0x1,%YMM6,%XMM0 |
(5) 0x401fb6 VCVTPS2PD %XMM0,%YMM0 |
(5) 0x401fba VFMADD231PD %YMM31,%YMM1,%YMM0 |
(5) 0x401fc0 VCVTPD2PS %YMM14,%XMM1 |
(5) 0x401fc5 VCVTPD2PS %YMM0,%XMM0 |
(5) 0x401fc9 VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0 |
(5) 0x401fcf VCMPPS $0x1,%YMM28,%YMM3,%K1 |
(5) 0x401fd6 VMULPS %YMM0,%YMM29,%YMM0{%K1}{z} |
(5) 0x401fdc VFMADD231PS %YMM25,%YMM0,%YMM17 |
(5) 0x401fe2 VFMADD231PS %YMM26,%YMM0,%YMM18 |
(5) 0x401fe8 VFMADD231PS %YMM27,%YMM0,%YMM16 |
(5) 0x401fee ADD $0x8,%R10 |
(5) 0x401ff2 CMP %R9,%R10 |
(5) 0x401ff5 JB 401ef0 |
(4) 0x401ffb VEXTRACTF32X4 $0x1,%YMM17,%XMM0 |
(4) 0x402002 VADDPS %XMM0,%XMM17,%XMM0 |
(4) 0x402008 VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 |
(4) 0x40200d VADDPS %XMM1,%XMM0,%XMM0 |
(4) 0x402011 VMOVSHDUP %XMM0,%XMM1 |
(4) 0x402015 VADDSS %XMM1,%XMM0,%XMM17 |
(4) 0x40201b VEXTRACTF32X4 $0x1,%YMM18,%XMM0 |
(4) 0x402022 VADDPS %XMM0,%XMM18,%XMM0 |
(4) 0x402028 VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 |
(4) 0x40202d VADDPS %XMM1,%XMM0,%XMM0 |
(4) 0x402031 VMOVSHDUP %XMM0,%XMM1 |
(4) 0x402035 VADDSS %XMM1,%XMM0,%XMM18 |
(4) 0x40203b VEXTRACTF32X4 $0x1,%YMM16,%XMM0 |
(4) 0x402042 VADDPS %XMM0,%XMM16,%XMM0 |
(4) 0x402048 VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 |
(4) 0x40204d VADDPS %XMM1,%XMM0,%XMM0 |
(4) 0x402051 VMOVSHDUP %XMM0,%XMM1 |
(4) 0x402055 VADDSS %XMM1,%XMM0,%XMM16 |
(4) 0x40205b CMP %R9,%RDX |
(4) 0x40205e JE 401e32 |
(4) 0x402064 JMP 402085 |
0x402066 NOPW %CS:(%RAX,%RAX,1) |
(4) 0x402070 VXORPS %XMM16,%XMM16,%XMM16 |
(4) 0x402076 XOR %R9D,%R9D |
(4) 0x402079 VXORPS %XMM18,%XMM18,%XMM18 |
(4) 0x40207f VXORPS %XMM17,%XMM17,%XMM17 |
(4) 0x402085 MOV %RDX,%R10 |
(4) 0x402088 SUB %R9,%R10 |
(4) 0x40208b VPBROADCASTQ %R10,%YMM22 |
(4) 0x402091 VPCMPNLEUQ 0x4e44(%RIP),%YMM22,%K0 |
(4) 0x40209c VPCMPNLEUQ 0x4e59(%RIP),%YMM22,%K1 |
(4) 0x4020a7 KORTESTB %K1,%K0 |
(4) 0x4020ab JE 4021f8 |
(4) 0x4020b1 KSHIFTLB $0x4,%K1,%K2 |
(4) 0x4020b7 KORB %K2,%K0,%K2 |
(4) 0x4020bb VMOVUPS 0x60b1f0(,%R9,4),%YMM0{%K2}{z} |
(4) 0x4020c6 VMOVAPS %YMM0,%YMM15{%K2} |
(4) 0x4020cc VBROADCASTSS %XMM21,%YMM0 |
(4) 0x4020d2 VSUBPS %YMM0,%YMM15,%YMM0 |
(4) 0x4020d6 VMOVUPS 0x66cc70(,%R9,4),%YMM1{%K2}{z} |
(4) 0x4020e1 VMOVUPS 0x20(%RSP),%YMM6 |
(4) 0x4020e7 VMOVAPS %YMM1,%YMM6{%K2} |
(4) 0x4020ed VBROADCASTSS %XMM20,%YMM1 |
(4) 0x4020f3 VMOVUPS %YMM6,0x20(%RSP) |
(4) 0x4020f9 VSUBPS %YMM1,%YMM6,%YMM1 |
(4) 0x4020fd VMOVUPS 0x6ce6f0(,%R9,4),%YMM6{%K2}{z} |
(4) 0x402108 VMOVUPS 0x40(%RSP),%YMM14 |
(4) 0x40210e VMOVAPS %YMM6,%YMM14{%K2} |
(4) 0x402114 VBROADCASTSS %XMM19,%YMM6 |
(4) 0x40211a VMOVUPS %YMM14,0x40(%RSP) |
(4) 0x402120 VSUBPS %YMM6,%YMM14,%YMM6 |
(4) 0x402124 VMULPS %YMM0,%YMM0,%YMM14 |
(4) 0x402128 VFMADD231PS %YMM1,%YMM1,%YMM14 |
(4) 0x40212d VFMADD231PS %YMM6,%YMM6,%YMM14 |
(4) 0x402132 VCMPPS $0x1,%YMM2,%YMM14,%K2{%K2} |
(4) 0x402139 VMOVUPS 0x730170(,%R9,4),%YMM19{%K2}{z} |
(4) 0x402144 VADDPS %YMM4,%YMM14,%YMM20 |
(4) 0x40214a VEXTRACTF32X4 $0x1,%YMM20,%XMM21 |
(4) 0x402151 VCVTPS2PD %XMM21,%YMM21 |
(4) 0x402157 VCVTPS2PD %XMM20,%YMM20 |
(4) 0x40215d VSQRTPD %YMM20,%YMM22 |
(4) 0x402163 VSQRTPD %YMM21,%YMM23 |
(4) 0x402169 VMULPD %YMM20,%YMM20,%YMM20 |
(4) 0x40216f VDIVPD %YMM20,%YMM5,%YMM20 |
(4) 0x402175 VMULPD %YMM21,%YMM21,%YMM21 |
(4) 0x40217b VDIVPD %YMM21,%YMM5,%YMM21 |
(4) 0x402181 VMOVAPS %YMM13,%YMM24 |
(4) 0x402187 VFMADD213PS %YMM7,%YMM14,%YMM24 |
(4) 0x40218d VFMADD213PS %YMM8,%YMM14,%YMM24 |
(4) 0x402193 VFMADD213PS %YMM9,%YMM14,%YMM24 |
(4) 0x402199 VFMADD213PS %YMM10,%YMM14,%YMM24 |
(4) 0x40219f VFMADD213PS %YMM11,%YMM14,%YMM24 |
(4) 0x4021a5 VCVTPS2PD %XMM24,%YMM25 |
(4) 0x4021ab VEXTRACTF32X4 $0x1,%YMM24,%XMM24 |
(4) 0x4021b2 VCVTPS2PD %XMM24,%YMM24 |
(4) 0x4021b8 VFMADD231PD %YMM20,%YMM22,%YMM25 |
(4) 0x4021be VFMADD231PD %YMM21,%YMM23,%YMM24 |
(4) 0x4021c4 VCVTPD2PS %YMM25,%XMM20 |
(4) 0x4021ca VCVTPD2PS %YMM24,%XMM21 |
(4) 0x4021d0 VINSERTF32X4 $0x1,%XMM21,%YMM20,%YMM20 |
(4) 0x4021d7 VCMPPS $0x1,%YMM14,%YMM3,%K2 |
(4) 0x4021de VMULPS %YMM20,%YMM19,%YMM14{%K2}{z} |
(4) 0x4021e4 VMULPS %YMM0,%YMM14,%YMM19 |
(4) 0x4021ea VMULPS %YMM1,%YMM14,%YMM20 |
(4) 0x4021f0 VMULPS %YMM6,%YMM14,%YMM21 |
(4) 0x4021f6 JMP 40220a |
(4) 0x4021f8 VXORPS %XMM19,%XMM19,%XMM19 |
(4) 0x4021fe VXORPS %XMM20,%XMM20,%XMM20 |
(4) 0x402204 VXORPS %XMM21,%XMM21,%XMM21 |
(4) 0x40220a KSHIFTLB $0x4,%K1,%K1 |
(4) 0x402210 KORB %K1,%K0,%K1 |
(4) 0x402214 VMOVAPS %YMM19,%YMM0{%K1}{z} |
(4) 0x40221a VMOVAPS %YMM20,%YMM1{%K1}{z} |
(4) 0x402220 VMOVAPS %YMM21,%YMM6{%K1}{z} |
(4) 0x402226 VEXTRACTF128 $0x1,%YMM0,%XMM14 |
(4) 0x40222c VADDPS %XMM0,%XMM14,%XMM0 |
(4) 0x402230 VSHUFPD $0x1,%XMM0,%XMM0,%XMM14 |
(4) 0x402235 VADDPS %XMM0,%XMM14,%XMM0 |
(4) 0x402239 VMOVSHDUP %XMM0,%XMM14 |
(4) 0x40223d VADDSS %XMM0,%XMM14,%XMM0 |
(4) 0x402241 VADDSS %XMM0,%XMM17,%XMM17 |
(4) 0x402247 VEXTRACTF128 $0x1,%YMM1,%XMM0 |
(4) 0x40224d VADDPS %XMM0,%XMM1,%XMM0 |
(4) 0x402251 VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 |
(4) 0x402256 VADDPS %XMM1,%XMM0,%XMM0 |
(4) 0x40225a VMOVSHDUP %XMM0,%XMM1 |
(4) 0x40225e VADDSS %XMM1,%XMM0,%XMM0 |
(4) 0x402262 VADDSS %XMM0,%XMM18,%XMM18 |
(4) 0x402268 VEXTRACTF128 $0x1,%YMM6,%XMM0 |
(4) 0x40226e VADDPS %XMM0,%XMM6,%XMM0 |
(4) 0x402272 VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 |
(4) 0x402277 VADDPS %XMM1,%XMM0,%XMM0 |
(4) 0x40227b VMOVSHDUP %XMM0,%XMM1 |
(4) 0x40227f VADDSS %XMM1,%XMM0,%XMM0 |
(4) 0x402283 VADDSS %XMM0,%XMM16,%XMM16 |
(4) 0x402289 JMP 401e32 |
0x40228e XCHG %AX,%AX |
Path / |
Source file and lines | main.c:139-147 |
Module | exec |
nb instructions | 56 |
nb uops | 58 |
loop length | 268 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 9 |
used zmm registers | 0 |
nb stack references | 7 |
micro-operation queue | 9.67 cycles |
front end | 9.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.70 | 1.60 | 5.33 | 5.33 | 5.50 | 1.60 | 1.50 | 5.50 | 5.50 | 5.50 | 1.60 | 5.33 |
cycles | 1.70 | 1.60 | 5.33 | 5.33 | 5.50 | 1.60 | 1.50 | 5.50 | 5.50 | 5.50 | 1.60 | 5.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 9.43 |
Stall cycles | 0.00 |
Front-end | 9.67 |
Dispatch | 5.50 |
Overall L1 | 9.67 |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
all | 8% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
all | 8% |
load | 6% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 8% |
load | 6% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 8% |
all | 8% |
load | 6% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x60,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R9,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOVL $0,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0xbb7,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x20(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x24(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x1c(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x18(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x60b120,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EBX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 401420 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x14(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RSP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %ECX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 401da9 <main.extracted.8+0x89> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x60b140,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EBX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x10(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 401380 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $-0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VBROADCASTSS 0x50a5(%RIP),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VXORPS %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VBROADCASTSS 0x509c(%RIP),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0x515b(%RIP),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSS 0x508e(%RIP),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSS 0x5089(%RIP),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSS 0x5084(%RIP),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSS 0x507f(%RIP),%YMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSS 0x507a(%RIP),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSS 0x5075(%RIP),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VMOVSS 0x5071(%RIP),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 401e84 <main.extracted.8+0x164> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | main.c:139-147 |
Module | exec |
nb instructions | 56 |
nb uops | 58 |
loop length | 268 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 9 |
used zmm registers | 0 |
nb stack references | 7 |
micro-operation queue | 9.67 cycles |
front end | 9.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.70 | 1.60 | 5.33 | 5.33 | 5.50 | 1.60 | 1.50 | 5.50 | 5.50 | 5.50 | 1.60 | 5.33 |
cycles | 1.70 | 1.60 | 5.33 | 5.33 | 5.50 | 1.60 | 1.50 | 5.50 | 5.50 | 5.50 | 1.60 | 5.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 9.43 |
Stall cycles | 0.00 |
Front-end | 9.67 |
Dispatch | 5.50 |
Overall L1 | 9.67 |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
all | 8% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
all | 8% |
load | 6% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 8% |
load | 6% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 8% |
all | 8% |
load | 6% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x60,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R9,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOVL $0,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0xbb7,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x20(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x24(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x1c(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x18(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x60b120,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EBX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 401420 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x14(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RSP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %ECX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 401da9 <main.extracted.8+0x89> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x60b140,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EBX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x10(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 401380 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $-0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VBROADCASTSS 0x50a5(%RIP),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VXORPS %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VBROADCASTSS 0x509c(%RIP),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0x515b(%RIP),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSS 0x508e(%RIP),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSS 0x5089(%RIP),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSS 0x5084(%RIP),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSS 0x507f(%RIP),%YMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSS 0x507a(%RIP),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSS 0x5075(%RIP),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VMOVSS 0x5071(%RIP),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 401e84 <main.extracted.8+0x164> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼main.extracted.8– | 91.38 | 18.02 |
▼Loop 4 - Step10_orig.c:19-35 - exec– | 0.04 | 0.01 |
○Loop 5 - Step10_orig.c:19-35 - exec | 91.35 | 17.95 |