OV - exec - Loop 1

	Loop Id: 1	Module: exec	Source: main.c:111-116	Coverage: 0.07%

0x4017f0 VADDPS	%YMM4,%YMM10,%YMM13

0x4017f4 VADDPS	%YMM7,%YMM10,%YMM10

0x4017f8 VMOVUPS	%YMM13,0x40b194(,%R9,4)    [1]

0x401802 VADDPS	%YMM5,%YMM12,%YMM14

0x401806 VADDPS	%YMM8,%YMM12,%YMM12

0x40180b VMOVUPS	%YMM14,0x46cc14(,%R9,4)    [1]

0x401815 VADDPS	%YMM6,%YMM11,%YMM14

0x401819 VADDPS	%YMM9,%YMM11,%YMM11

0x40181e VMOVUPS	%YMM14,0x4ce694(,%R9,4)    [1]

0x401828 VPBROADCASTD	%R9D,%YMM14

0x40182e VPADDD	%YMM16,%YMM14,%YMM14

0x401834 VCVTUDQ2PS	%YMM14,%YMM14

0x40183a VFMADD132PS	%YMM17,%YMM13,%YMM14

0x401840 VMOVUPS	%YMM14,0x530114(,%R9,4)    [1]

0x40184a ADD	$0x8,%R9

0x40184e CMP	%R8,%R9

0x401851 JLE	4017f0

/home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c: 111 - 116

--------------------------------------------------------------------------------

111:       for ( i = 1; i < n; i++ )

112:       {

113:           xx[i] = xx[i-1] + dx1;

114:           yy[i] = yy[i-1] + dy1;

115:           zz[i] = zz[i-1] + dz1;

116:           mass[i] = (float)i * 0.01f + xx[i];

Coverage (%)	Name	Source Location	Module
○100.00	__libc_start_call_main		libc.so.6

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P1, P5,
Function	main
Source	main.c:111-116
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	3.50
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	2.33
CQA cycles if fully vectorized	1.75
Front-end cycles	2.67
P0 cycles	3.00
P1 cycles	3.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	2.00
P5 cycles	3.50
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	16.00
Nb loads	0.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	18.29
Nb FLOP add-sub	48.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	36.57
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	92.86
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	46.88
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	28.13

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P1, P5,
Function	main
Source	main.c:111-116
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	3.50
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	2.33
CQA cycles if fully vectorized	1.75
Front-end cycles	2.67
P0 cycles	3.00
P1 cycles	3.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	2.00
P5 cycles	3.50
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	16.00
Nb loads	0.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	18.29
Nb FLOP add-sub	48.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	36.57
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	92.86
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	46.88
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	28.13

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	main.c:111-116
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:111-116.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 46% of vector register length is used (average across all SSE/AVX instructions).

Details

92% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.50 to 3.00 cycles (1.17x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 8 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 4 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:113
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:114
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:115
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUDQ2PS (UINT32 to FP32, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

7 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

56: addition or subtraction (8 inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is storing 128 bytes (32 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

General properties

nb instructions	17
nb uops	16
loop length	99
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	13
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.67 cycles
front end	2.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.00	3.50	0.00	0.00	2.00	3.50	1.00	2.00	2.00	2.00	0.00	0.00
cycles	3.00	3.50	0.00	0.00	2.00	3.50	1.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	2.67
Dispatch	3.50
Data deps.	3.00
Overall L1	3.50

Vectorization ratios

INT

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	92%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	35%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	46%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

28% of peak store performance is reached (36.57 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4017f0

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
VADDPS %YMM4,%YMM10,%YMM13	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPS %YMM7,%YMM10,%YMM10	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPS %YMM13,0x40b194(,%R9,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VADDPS %YMM5,%YMM12,%YMM14	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPS %YMM8,%YMM12,%YMM12	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPS %YMM14,0x46cc14(,%R9,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VADDPS %YMM6,%YMM11,%YMM14	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPS %YMM9,%YMM11,%YMM11	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPS %YMM14,0x4ce694(,%R9,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VPBROADCASTD %R9D,%YMM14	1	0	0	0	1	0	0	0	0	0	3	1	scal (6.3%)
VPADDD %YMM16,%YMM14,%YMM14	1	0.33	0.33	0	0.33	0	0	0	0	0	1	0.33	vect (50.0%)
VCVTUDQ2PS %YMM14,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PS %YMM17,%YMM13,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPS %YMM14,0x530114(,%R9,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
ADD $0x8,%R9	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R9	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
JLE 4017f0 <main+0x2f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	main.c:111-116
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:111-116.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 46% of vector register length is used (average across all SSE/AVX instructions).

Details

92% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 8 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 4 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:113
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:114
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:115
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUDQ2PS (UINT32 to FP32, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

7 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

56: addition or subtraction (8 inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is storing 128 bytes (32 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

General properties

nb instructions	17
nb uops	16
loop length	99
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	13
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.67 cycles
front end	2.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.00	3.50	0.00	0.00	2.00	3.50	1.00	2.00	2.00	2.00	0.00	0.00
cycles	3.00	3.50	0.00	0.00	2.00	3.50	1.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	2.67
Dispatch	3.50
Data deps.	3.00
Overall L1	3.50

Vectorization ratios

INT

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	92%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	35%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	46%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

28% of peak store performance is reached (36.57 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4017f0

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
VADDPS %YMM4,%YMM10,%YMM13	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPS %YMM7,%YMM10,%YMM10	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPS %YMM13,0x40b194(,%R9,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VADDPS %YMM5,%YMM12,%YMM14	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPS %YMM8,%YMM12,%YMM12	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPS %YMM14,0x46cc14(,%R9,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VADDPS %YMM6,%YMM11,%YMM14	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPS %YMM9,%YMM11,%YMM11	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPS %YMM14,0x4ce694(,%R9,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VPBROADCASTD %R9D,%YMM14	1	0	0	0	1	0	0	0	0	0	3	1	scal (6.3%)
VPADDD %YMM16,%YMM14,%YMM14	1	0.33	0.33	0	0.33	0	0	0	0	0	1	0.33	vect (50.0%)
VCVTUDQ2PS %YMM14,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PS %YMM17,%YMM13,%YMM14	1	0.50	0.50	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPS %YMM14,0x530114(,%R9,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
ADD $0x8,%R9	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R9	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
JLE 4017f0 <main+0x2f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code