OV - exec - Function main

	Function: main	Module: exec	Source: main.c:50-191 [...]	Coverage (incl. loops): 0.07% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c: 50 - 191

--------------------------------------------------------------------------------

50: {

[...]

73:       printf( "count is set %d\n", count );

74:       printf( "Total MPI ranks %d\n", nprocs );

75:   }

76:

77:   if (argc == 2 && strncmp(argv[1], "-s", 2) == 0)

78:       NN = 15000;

79:

80:   printf( "N is set %ld\n", NN );

81:

82: #pragma omp parallel

[...]

97:   for ( n = 400; n < NN; n = n + 20 )

[...]

103:       dx1 = 1.0f/(float)n;

104:       dy1 = 2.0f/(float)n;

105:       dz1 = 3.0f/(float)n;

106:       xx[0] = 0.f;

107:       yy[0] = 0.f;

108:       zz[0] = 0.f;

109:       mass[0] = 2.f;

110:

111:       for ( i = 1; i < n; i++ )

112:       {

113:           xx[i] = xx[i-1] + dx1;

114:           yy[i] = yy[i-1] + dy1;

115:           zz[i] = zz[i-1] + dz1;

116:           mass[i] = (float)i * 0.01f + xx[i];

117:       }

118:

119:       for ( i = 0; i < n; i++ )

120:       {

121:           vx1[i] = 0.f;

122:           vy1[i] = 0.f;

123:           vz1[i] = 0.f;

[...]

136:       t1 = mysecond();

137: #endif

138:

139:     #pragma omp parallel for private( dx1, dy1, dz1 )

[...]

152:       t2 = mysecond();

[...]

166:       t3 = (t2 - t1) * 1e6;

167: #endif

168:

169:       elapsed = elapsed + t3;

[...]

185:       printf( "\nKernel elapsed time, s: %18.8lf\n", elapsed*1e-6 );

[...]

191:   return 0;

0x401500 PUSH	%RBP

0x401501 MOV	%RSP,%RBP

0x401504 PUSH	%R15

0x401506 PUSH	%R14

0x401508 PUSH	%R13

0x40150a PUSH	%R12

0x40150c PUSH	%RBX

0x40150d SUB	$0x18,%RSP

0x401511 VSTMXCSR	-0x2c(%RBP)

0x401516 ORL	$0x8040,-0x2c(%RBP)

0x40151d MOV	%RSI,%R14

0x401520 MOV	%EDI,%R15D

0x401523 VLDMXCSR	-0x2c(%RBP)

0x401528 MOV	$0x407098,%EDI

0x40152d MOV	$0xbb8,%ESI

0x401532 XOR	%EAX,%EAX

0x401534 CALL	401030 <printf@plt>

0x401539 MOV	$0x4070a9,%EDI

0x40153e MOV	$0x1,%ESI

0x401543 XOR	%EAX,%EAX

0x401545 CALL	401030 <printf@plt>

0x40154a MOV	$0x186a0,%EBX

0x40154f CMP	$0x2,%R15D

0x401553 JNE	40156b

0x401555 MOV	0x8(%R14),%RAX

0x401559 CMPB	$0x2d,(%RAX)

0x40155c JNE	40156b

0x40155e CMPB	$0x73,0x1(%RAX)

0x401562 MOV	$0x3a98,%EAX

0x401567 CMOVE	%RAX,%RBX

0x40156b MOV	$0x4070bd,%EDI

0x401570 MOV	%RBX,%RSI

0x401573 XOR	%EAX,%EAX

0x401575 CALL	401030 <printf@plt>

0x40157a MOV	$0x40b0c0,%EDI

0x40157f MOV	$0x4018f0,%EDX

0x401584 MOV	$0x1,%ESI

0x401589 XOR	%ECX,%ECX

0x40158b XOR	%EAX,%EAX

0x40158d CALL	4010e0 <__kmpc_fork_call@plt>

0x401592 ADD	$-0x191,%EBX

0x401598 MOV	$-0x33333333,%R14D

0x40159e IMUL	%RBX,%R14

0x4015a2 SHR	$0x24,%R14

0x4015a6 INC	%R14D

0x4015a9 VXORPS	%XMM0,%XMM0,%XMM0

0x4015ad MOV	$0x190,%R15D

0x4015b3 MOV	$0x18c,%R12D

0x4015b9 VMOVSS	0x5a53(%RIP),%XMM15

0x4015c1 VPMOVSXBD	0x5ac5(%RIP),%YMM16

0x4015cb VBROADCASTSS	0x5a3f(%RIP),%YMM17

0x4015d5 XOR	%R13D,%R13D

0x4015d8 JMP	4016a2

0x4015dd NOPL	(%RAX)

(2) 0x4015e0 MOV	$0x591b90,%EDI

(2) 0x4015e5 XOR	%ESI,%ESI

(2) 0x4015e7 MOV	%RBX,%RDX

(2) 0x4015ea VZEROUPPER

(2) 0x4015ed CALL	401f50 <_intel_fast_memset>

(2) 0x4015f2 MOV	$0x5f3610,%EDI

(2) 0x4015f7 XOR	%ESI,%ESI

(2) 0x4015f9 MOV	%RBX,%RDX

(2) 0x4015fc CALL	401f50 <_intel_fast_memset>

(2) 0x401601 MOV	$0x655090,%EDI

(2) 0x401606 XOR	%ESI,%ESI

(2) 0x401608 MOV	%RBX,%RDX

(2) 0x40160b CALL	401f50 <_intel_fast_memset>

(2) 0x401610 XOR	%EAX,%EAX

(2) 0x401612 CALL	401a90 <mysecond>

(2) 0x401617 VMOVSD	%XMM0,-0x38(%RBP)

(2) 0x40161c SUB	$0x8,%RSP

(2) 0x401620 MOV	$0x40b120,%EDI

(2) 0x401625 MOV	$0x401920,%EDX

(2) 0x40162a MOV	$0x3e6b851f,%ECX

(2) 0x40162f MOV	$0x3f000000,%R8D

(2) 0x401635 MOV	$0x3cf5c28f,%R9D

(2) 0x40163b MOV	$0x6,%ESI

(2) 0x401640 XOR	%EAX,%EAX

(2) 0x401642 PUSH	$0xbb7

(2) 0x401647 PUSH	$0

(2) 0x401649 PUSH	%R15

(2) 0x40164b CALL	4010e0 <__kmpc_fork_call@plt>

(2) 0x401650 ADD	$0x20,%RSP

(2) 0x401654 XOR	%EAX,%EAX

(2) 0x401656 CALL	401a90 <mysecond>

(2) 0x40165b VMOVSS	0x59b1(%RIP),%XMM15

(2) 0x401663 VSUBSD	-0x38(%RBP),%XMM0,%XMM0

(2) 0x401668 VMOVSD	-0x40(%RBP),%XMM1

(2) 0x40166d VFMADD231SD	0x5a0a(%RIP),%XMM0,%XMM1

(2) 0x401676 VMOVAPD	%XMM1,%XMM0

(2) 0x40167a ADD	$0x14,%R15

(2) 0x40167e INC	%R13

(2) 0x401681 ADD	$0x14,%R12

(2) 0x401685 CMP	%R14,%R13

(2) 0x401688 VPMOVSXBD	0x59fe(%RIP),%YMM16

(2) 0x401692 VBROADCASTSS	0x5978(%RIP),%YMM17

(2) 0x40169c JE	4018ca

(2) 0x4016a2 VMOVSD	%XMM0,-0x40(%RBP)

(2) 0x4016a7 LEA	(,%R12,4),%RAX

(2) 0x4016af AND	$-0x20,%RAX

(2) 0x4016b3 MOV	%R12,%RCX

(2) 0x4016b6 AND	$-0x8,%RCX

(2) 0x4016ba MOV	%R12D,%EDX

(2) 0x4016bd AND	$0x7,%EDX

(2) 0x4016c0 LEA	(%R13,%R13,4),%RBX

(2) 0x4016c5 SAL	$0x4,%RBX

(2) 0x4016c9 ADD	$0x640,%RBX

(2) 0x4016d0 VCVTSI2SS	%R15D,%XMM18,%XMM0

(2) 0x4016d6 VMOVSS	0x5932(%RIP),%XMM1

(2) 0x4016de VDIVSS	%XMM0,%XMM1,%XMM0

(2) 0x4016e2 VBROADCASTSS	%XMM0,%XMM1

(2) 0x4016e7 VMULPS	0x5941(%RIP),%XMM1,%XMM1

(2) 0x4016ef MOVL	$0,0x9a97(%RIP)

(2) 0x4016f9 MOVL	$0,0x6b50d(%RIP)

(2) 0x401703 MOVL	$0,0xccf83(%RIP)

(2) 0x40170d MOVL	$0x40000000,0x12e9f9(%RIP)

(2) 0x401717 LEA	-0x1(%R15),%RSI

(2) 0x40171b VXORPS	%XMM3,%XMM3,%XMM3

(2) 0x40171f VXORPS	%XMM2,%XMM2,%XMM2

(2) 0x401723 MOV	$-0x3,%RDI

(2) 0x40172a NOPW	(%RAX,%RAX,1)

  (0) 0x401730 VADDSS	%XMM0,%XMM2,%XMM2

  (0) 0x401734 VMOVSS	%XMM2,0x40b1a0(,%RDI,4)

  (0) 0x40173d VADDPS	%XMM1,%XMM3,%XMM3

  (0) 0x401741 VEXTRACTPS	$0x1,%XMM3,0x46cc20(,%RDI,4)

  (0) 0x40174c VMOVSS	%XMM3,0x4ce6a0(,%RDI,4)

  (0) 0x401755 LEA	0x4(%RDI),%R8D

  (0) 0x401759 VCVTUSI2SS	%R8D,%XMM18,%XMM4

  (0) 0x40175f VFMADD132SS	%XMM15,%XMM2,%XMM4

  (0) 0x401764 VMOVSS	%XMM4,0x530120(,%RDI,4)

  (0) 0x40176d INC	%RDI

  (0) 0x401770 JNE	401730

(2) 0x401772 LEA	-0x4(%R15),%R8

(2) 0x401776 AND	$-0x8,%R8

(2) 0x40177a LEA	0x3(%R8),%RDI

(2) 0x40177e VBROADCASTSS	%XMM0,%YMM4

(2) 0x401783 VBROADCASTSS	%XMM2,%YMM10

(2) 0x401788 VMOVUPS	0x58b0(%RIP),%YMM9

(2) 0x401790 VFMADD231PS	%YMM9,%YMM4,%YMM10

(2) 0x401795 VMOVSS	0x587b(%RIP),%XMM13

(2) 0x40179d VMULSS	%XMM0,%XMM13,%XMM7

(2) 0x4017a1 VMOVSHDUP	%XMM1,%XMM6

(2) 0x4017a5 VBROADCASTSD	%XMM6,%YMM5

(2) 0x4017aa VBROADCASTSS	0x5869(%RIP),%YMM8

(2) 0x4017b3 VPERMPS	%YMM3,%YMM8,%YMM12

(2) 0x4017b8 VFMADD231PS	%YMM9,%YMM5,%YMM12

(2) 0x4017bd VMULSS	%XMM6,%XMM13,%XMM8

(2) 0x4017c1 VBROADCASTSS	%XMM1,%YMM6

(2) 0x4017c6 VBROADCASTSS	%XMM3,%YMM11

(2) 0x4017cb VFMADD231PS	%YMM9,%YMM6,%YMM11

(2) 0x4017d0 VMULSS	%XMM1,%XMM13,%XMM9

(2) 0x4017d4 OR	$0x2,%R8

(2) 0x4017d8 VBROADCASTSS	%XMM7,%YMM7

(2) 0x4017dd VBROADCASTSS	%XMM8,%YMM8

(2) 0x4017e2 VBROADCASTSS	%XMM9,%YMM9

(2) 0x4017e7 MOV	$0x3,%R9D

(2) 0x4017ed NOPL	(%RAX)

  (1) 0x4017f0 VADDPS	%YMM4,%YMM10,%YMM13

  (1) 0x4017f4 VADDPS	%YMM7,%YMM10,%YMM10

  (1) 0x4017f8 VMOVUPS	%YMM13,0x40b194(,%R9,4)

  (1) 0x401802 VADDPS	%YMM5,%YMM12,%YMM14

  (1) 0x401806 VADDPS	%YMM8,%YMM12,%YMM12

  (1) 0x40180b VMOVUPS	%YMM14,0x46cc14(,%R9,4)

  (1) 0x401815 VADDPS	%YMM6,%YMM11,%YMM14

  (1) 0x401819 VADDPS	%YMM9,%YMM11,%YMM11

  (1) 0x40181e VMOVUPS	%YMM14,0x4ce694(,%R9,4)

  (1) 0x401828 VPBROADCASTD	%R9D,%YMM14

  (1) 0x40182e VPADDD	%YMM16,%YMM14,%YMM14

  (1) 0x401834 VCVTUDQ2PS	%YMM14,%YMM14

  (1) 0x40183a VFMADD132PS	%YMM17,%YMM13,%YMM14

  (1) 0x401840 VMOVUPS	%YMM14,0x530114(,%R9,4)

  (1) 0x40184a ADD	$0x8,%R9

  (1) 0x40184e CMP	%R8,%R9

  (1) 0x401851 JLE	4017f0

(2) 0x401853 CMP	%RDI,%RSI

(2) 0x401856 JE	4015e0

(2) 0x40185c VCVTSI2SS	%RDI,%XMM18,%XMM4

(2) 0x401862 VADDSS	0x57b6(%RIP),%XMM4,%XMM5

(2) 0x40186a VBROADCASTSS	%XMM5,%XMM4

(2) 0x40186f VFMADD213PS	%XMM3,%XMM1,%XMM4

(2) 0x401874 VFMADD231SS	%XMM5,%XMM0,%XMM2

(2) 0x401879 XOR	%ESI,%ESI

(2) 0x40187b NOPL	(%RAX,%RAX,1)

  (3) 0x401880 VADDSS	%XMM0,%XMM2,%XMM2

  (3) 0x401884 VMOVSS	%XMM2,0x40b1a0(%RAX,%RSI,4)

  (3) 0x40188d VADDPS	%XMM1,%XMM4,%XMM4

  (3) 0x401891 VEXTRACTPS	$0x1,%XMM4,0x46cc20(%RAX,%RSI,4)

  (3) 0x40189c VMOVSS	%XMM4,0x4ce6a0(%RAX,%RSI,4)

  (3) 0x4018a5 LEA	0x4(%RCX,%RSI,1),%EDI

  (3) 0x4018a9 VCVTUSI2SS	%EDI,%XMM18,%XMM3

  (3) 0x4018af VFMADD132SS	%XMM15,%XMM2,%XMM3

  (3) 0x4018b4 VMOVSS	%XMM3,0x530120(%RAX,%RSI,4)

  (3) 0x4018bd INC	%RSI

  (3) 0x4018c0 CMP	%RSI,%RDX

  (3) 0x4018c3 JNE	401880

(2) 0x4018c5 JMP	4015e0

0x4018ca VMULSD	0x57b6(%RIP),%XMM0,%XMM0

0x4018d2 MOV	$0x4070e6,%EDI

0x4018d7 MOV	$0x1,%AL

0x4018d9 CALL	401030 <printf@plt>

0x4018de XOR	%EAX,%EAX

0x4018e0 ADD	$0x18,%RSP

0x4018e4 POP	%RBX

0x4018e5 POP	%R12

0x4018e7 POP	%R13

0x4018e9 POP	%R14

0x4018eb POP	%R15

0x4018ed POP	%RBP

0x4018ee RET

0x4018ef NOP

Coverage (%)	Name	Source Location	Module
○100.00	__libc_start_call_main		libc.so.6

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	main.c:50-191
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:50,73-82,97,103-123,136-139,152,166-169,185,191.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 1.67 cycles (8.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_fork_call@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:82
printf@plt: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:73
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:74
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:80
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:185

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

OR: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:50
VLDMXCSR: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:50
VPMOVSXBD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:97
VSTMXCSR: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:50

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:97

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 42 bytes (5 double precision FP elements). The binary function is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	68
nb uops	87
loop length	262
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.50 cycles
front end	14.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.70	6.60	5.33	5.33	6.50	6.60	6.50	6.50	6.50	6.50	6.60	5.33
cycles	6.70	6.60	5.33	5.33	6.50	6.60	6.50	6.50	6.50	6.50	6.60	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.50
Dispatch	6.70
Overall L1	14.50

Vectorization ratios

INT

all	4%
load	25%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	7%
load	14%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

INT

all	6%
load	5%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	8%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	7%
load	6%
store	6%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.50 cycles. At this rate:

1% of peak load performance is reached (2.90 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.55 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.50 to 6.70 cycles (2.16x speedup).

ASM code

In the binary file, the address of the function is: 401500

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VSTMXCSR -0x2c(%RBP)	3	1.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	12	1	N/A
ORL $0x8040,-0x2c(%RBP)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1-2	1	scal (6.3%)
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VLDMXCSR -0x2c(%RBP)	11	1.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	6	N/A
MOV $0x407098,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xbb8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x4070a9,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x186a0,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP $0x2,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 40156b <main+0x6b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x8(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPB $0x2d,(%RAX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (1.6%)
JNE 40156b <main+0x6b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPB $0x73,0x1(%RAX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (1.6%)
MOV $0x3a98,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMOVE %RAX,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x4070bd,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x40b0c0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x4018f0,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 4010e0 <__kmpc_fork_call@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $-0x191,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $-0x33333333,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RBX,%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
SHR $0x24,%R14	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV $0x190,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x18c,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
VMOVSS 0x5a53(%RIP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VPMOVSXBD 0x5ac5(%RIP),%YMM16	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VBROADCASTSS 0x5a3f(%RIP),%YMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 4016a2 <main+0x1a2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMULSD 0x57b6(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV $0x4070e6,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	main.c:50-191
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:50,73-82,97,103-123,136-139,152,166-169,185,191.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 1.67 cycles (8.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

__kmpc_fork_call@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:82
printf@plt: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:73
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:74
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:80
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:185

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

OR: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:50
VLDMXCSR: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:50
VPMOVSXBD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:97
VSTMXCSR: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:50

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:97

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 42 bytes (5 double precision FP elements). The binary function is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	68
nb uops	87
loop length	262
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.50 cycles
front end	14.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.70	6.60	5.33	5.33	6.50	6.60	6.50	6.50	6.50	6.50	6.60	5.33
cycles	6.70	6.60	5.33	5.33	6.50	6.60	6.50	6.50	6.50	6.50	6.60	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.50
Dispatch	6.70
Overall L1	14.50

Vectorization ratios

INT

all	4%
load	25%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	7%
load	14%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

INT

all	6%
load	5%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	8%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	7%
load	6%
store	6%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.50 cycles. At this rate:

1% of peak load performance is reached (2.90 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.55 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 401500

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VSTMXCSR -0x2c(%RBP)	3	1.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	12	1	N/A
ORL $0x8040,-0x2c(%RBP)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1-2	1	scal (6.3%)
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VLDMXCSR -0x2c(%RBP)	11	1.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	6	N/A
MOV $0x407098,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xbb8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x4070a9,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x186a0,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP $0x2,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 40156b <main+0x6b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x8(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPB $0x2d,(%RAX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (1.6%)
JNE 40156b <main+0x6b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPB $0x73,0x1(%RAX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (1.6%)
MOV $0x3a98,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMOVE %RAX,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x4070bd,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x40b0c0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x4018f0,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 4010e0 <__kmpc_fork_call@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $-0x191,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $-0x33333333,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RBX,%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
SHR $0x24,%R14	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV $0x190,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x18c,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
VMOVSS 0x5a53(%RIP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VPMOVSXBD 0x5ac5(%RIP),%YMM16	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VBROADCASTSS 0x5a3f(%RIP),%YMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 4016a2 <main+0x1a2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMULSD 0x57b6(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV $0x4070e6,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼main–	0.07	0.00
▼Loop 2 - main.c:77-169 - exec–	0.00	0.00
○Loop 1 - main.c:111-116 - exec	0.07	1.18
○Loop 3 - main.c:111-116 - exec	0.00	0.00
○Loop 0 - main.c:111-116 - exec	0.00	0.00

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Code clean check

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Vectorization

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Execution units bottlenecks

512-bits vectorization

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CALL instructions

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

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