OV - exec - Function main

	Function: main	Module: exec	Source: main.c:50-191 [...]	Coverage (incl. loops): 0.07% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c: 50 - 191

--------------------------------------------------------------------------------

50: {

[...]

73:       printf( "count is set %d\n", count );

74:       printf( "Total MPI ranks %d\n", nprocs );

75:   }

76:

77:   if (argc == 2 && strncmp(argv[1], "-s", 2) == 0)

78:       NN = 15000;

79:

80:   printf( "N is set %ld\n", NN );

81:

82: #pragma omp parallel

[...]

97:   for ( n = 400; n < NN; n = n + 20 )

[...]

103:       dx1 = 1.0f/(float)n;

104:       dy1 = 2.0f/(float)n;

105:       dz1 = 3.0f/(float)n;

106:       xx[0] = 0.f;

107:       yy[0] = 0.f;

108:       zz[0] = 0.f;

109:       mass[0] = 2.f;

110:

111:       for ( i = 1; i < n; i++ )

112:       {

113:           xx[i] = xx[i-1] + dx1;

114:           yy[i] = yy[i-1] + dy1;

115:           zz[i] = zz[i-1] + dz1;

116:           mass[i] = (float)i * 0.01f + xx[i];

117:       }

118:

119:       for ( i = 0; i < n; i++ )

120:       {

121:           vx1[i] = 0.f;

122:           vy1[i] = 0.f;

123:           vz1[i] = 0.f;

[...]

136:       t1 = mysecond();

137: #endif

138:

139:     #pragma omp parallel for private( dx1, dy1, dz1 )

[...]

152:       t2 = mysecond();

[...]

166:       t3 = (t2 - t1) * 1e6;

167: #endif

168:

169:       elapsed = elapsed + t3;

[...]

185:       printf( "\nKernel elapsed time, s: %18.8lf\n", elapsed*1e-6 );

[...]

191:   return 0;

0x401540 PUSH	%RBP

0x401541 MOV	%RSP,%RBP

0x401544 PUSH	%R15

0x401546 PUSH	%R14

0x401548 PUSH	%R13

0x40154a PUSH	%R12

0x40154c PUSH	%RBX

0x40154d SUB	$0x18,%RSP

0x401551 MOV	%RSI,%R14

0x401554 MOV	%EDI,%R15D

0x401557 MOV	$0x10111ce4199d9fee,%RSI

0x401561 MOV	$0x3,%EDI

0x401566 CALL	402290 <__intel_new_feature_proc_init>

0x40156b MOV	$0x50,%ESI

0x401570 MOV	$0x1,%EDI

0x401575 CALL	401f80 <__intel_new_feature_proc_init_n>

0x40157a MOV	$0x406098,%EDI

0x40157f MOV	$0xbb8,%ESI

0x401584 XOR	%EAX,%EAX

0x401586 CALL	401030 <printf@plt>

0x40158b MOV	$0x4060a9,%EDI

0x401590 MOV	$0x1,%ESI

0x401595 XOR	%EAX,%EAX

0x401597 CALL	401030 <printf@plt>

0x40159c MOV	$0x186a0,%EBX

0x4015a1 CMP	$0x2,%R15D

0x4015a5 JNE	4015c5

0x4015a7 MOV	0x8(%R14),%RDI

0x4015ab MOV	$0x4060bd,%ESI

0x4015b0 MOV	$0x2,%EDX

0x4015b5 CALL	4010b0 <strncmp@plt>

0x4015ba TEST	%EAX,%EAX

0x4015bc MOV	$0x3a98,%EAX

0x4015c1 CMOVE	%RAX,%RBX

0x4015c5 MOV	$0x4060c0,%EDI

0x4015ca MOV	%RBX,%RSI

0x4015cd XOR	%EAX,%EAX

0x4015cf CALL	401030 <printf@plt>

0x4015d4 MOV	$0x40a0e0,%EDI

0x4015d9 MOV	$0x401960,%EDX

0x4015de MOV	$0x1,%ESI

0x4015e3 XOR	%ECX,%ECX

0x4015e5 XOR	%EAX,%EAX

0x4015e7 CALL	401110 <__kmpc_fork_call@plt>

0x4015ec ADD	$-0x191,%EBX

0x4015f2 MOV	$-0x33333333,%R14D

0x4015f8 IMUL	%RBX,%R14

0x4015fc SHR	$0x24,%R14

0x401600 INC	%R14D

0x401603 VXORPS	%XMM0,%XMM0,%XMM0

0x401607 MOV	$0x190,%R15D

0x40160d MOV	$0x18c,%R12D

0x401613 VMOVSS	0x49f9(%RIP),%XMM15

0x40161b VPMOVSXBD	0x4a6b(%RIP),%YMM16

0x401625 VBROADCASTSS	0x49e5(%RIP),%YMM17

0x40162f XOR	%R13D,%R13D

0x401632 JMP	401702

0x401637 NOPW	(%RAX,%RAX,1)

(2) 0x401640 MOV	$0x590bb0,%EDI

(2) 0x401645 XOR	%ESI,%ESI

(2) 0x401647 MOV	%RBX,%RDX

(2) 0x40164a VZEROUPPER

(2) 0x40164d CALL	403fb0 <__intel_avx_rep_memset>

(2) 0x401652 MOV	$0x5f2630,%EDI

(2) 0x401657 XOR	%ESI,%ESI

(2) 0x401659 MOV	%RBX,%RDX

(2) 0x40165c CALL	403fb0 <__intel_avx_rep_memset>

(2) 0x401661 MOV	$0x6540b0,%EDI

(2) 0x401666 XOR	%ESI,%ESI

(2) 0x401668 MOV	%RBX,%RDX

(2) 0x40166b CALL	403fb0 <__intel_avx_rep_memset>

(2) 0x401670 XOR	%EAX,%EAX

(2) 0x401672 CALL	401b00 <mysecond>

(2) 0x401677 VMOVSD	%XMM0,-0x30(%RBP)

(2) 0x40167c SUB	$0x8,%RSP

(2) 0x401680 MOV	$0x40a140,%EDI

(2) 0x401685 MOV	$0x401990,%EDX

(2) 0x40168a MOV	$0x3e6b851f,%ECX

(2) 0x40168f MOV	$0x3f000000,%R8D

(2) 0x401695 MOV	$0x3cf5c28f,%R9D

(2) 0x40169b MOV	$0x6,%ESI

(2) 0x4016a0 XOR	%EAX,%EAX

(2) 0x4016a2 PUSH	$0xbb7

(2) 0x4016a7 PUSH	$0

(2) 0x4016a9 PUSH	%R15

(2) 0x4016ab CALL	401110 <__kmpc_fork_call@plt>

(2) 0x4016b0 ADD	$0x20,%RSP

(2) 0x4016b4 XOR	%EAX,%EAX

(2) 0x4016b6 CALL	401b00 <mysecond>

(2) 0x4016bb VMOVSS	0x4951(%RIP),%XMM15

(2) 0x4016c3 VSUBSD	-0x30(%RBP),%XMM0,%XMM0

(2) 0x4016c8 VMOVSD	-0x38(%RBP),%XMM1

(2) 0x4016cd VFMADD231SD	0x49aa(%RIP),%XMM0,%XMM1

(2) 0x4016d6 VMOVAPD	%XMM1,%XMM0

(2) 0x4016da ADD	$0x14,%R15

(2) 0x4016de INC	%R13

(2) 0x4016e1 ADD	$0x14,%R12

(2) 0x4016e5 CMP	%R14,%R13

(2) 0x4016e8 VPMOVSXBD	0x499e(%RIP),%YMM16

(2) 0x4016f2 VBROADCASTSS	0x4918(%RIP),%YMM17

(2) 0x4016fc JE	40192a

(2) 0x401702 VMOVSD	%XMM0,-0x38(%RBP)

(2) 0x401707 LEA	(,%R12,4),%RAX

(2) 0x40170f AND	$-0x20,%RAX

(2) 0x401713 MOV	%R12,%RCX

(2) 0x401716 AND	$-0x8,%RCX

(2) 0x40171a MOV	%R12D,%EDX

(2) 0x40171d AND	$0x7,%EDX

(2) 0x401720 LEA	(%R13,%R13,4),%RBX

(2) 0x401725 SAL	$0x4,%RBX

(2) 0x401729 ADD	$0x640,%RBX

(2) 0x401730 VCVTSI2SS	%R15D,%XMM18,%XMM0

(2) 0x401736 VMOVSS	0x48d2(%RIP),%XMM1

(2) 0x40173e VDIVSS	%XMM0,%XMM1,%XMM0

(2) 0x401742 VBROADCASTSS	%XMM0,%XMM1

(2) 0x401747 VMULPS	0x48e1(%RIP),%XMM1,%XMM1

(2) 0x40174f MOVL	$0,0x8a57(%RIP)

(2) 0x401759 MOVL	$0,0x6a4cd(%RIP)

(2) 0x401763 MOVL	$0,0xcbf43(%RIP)

(2) 0x40176d MOVL	$0x40000000,0x12d9b9(%RIP)

(2) 0x401777 LEA	-0x1(%R15),%RSI

(2) 0x40177b VXORPS	%XMM3,%XMM3,%XMM3

(2) 0x40177f VXORPS	%XMM2,%XMM2,%XMM2

(2) 0x401783 MOV	$-0x3,%RDI

(2) 0x40178a NOPW	(%RAX,%RAX,1)

  (0) 0x401790 VADDSS	%XMM0,%XMM2,%XMM2

  (0) 0x401794 VMOVSS	%XMM2,0x40a1c0(,%RDI,4)

  (0) 0x40179d VADDPS	%XMM1,%XMM3,%XMM3

  (0) 0x4017a1 VEXTRACTPS	$0x1,%XMM3,0x46bc40(,%RDI,4)

  (0) 0x4017ac VMOVSS	%XMM3,0x4cd6c0(,%RDI,4)

  (0) 0x4017b5 LEA	0x4(%RDI),%R8D

  (0) 0x4017b9 VCVTUSI2SS	%R8D,%XMM18,%XMM4

  (0) 0x4017bf VFMADD132SS	%XMM15,%XMM2,%XMM4

  (0) 0x4017c4 VMOVSS	%XMM4,0x52f140(,%RDI,4)

  (0) 0x4017cd INC	%RDI

  (0) 0x4017d0 JNE	401790

(2) 0x4017d2 LEA	-0x4(%R15),%R8

(2) 0x4017d6 AND	$-0x8,%R8

(2) 0x4017da LEA	0x3(%R8),%RDI

(2) 0x4017de VBROADCASTSS	%XMM0,%YMM4

(2) 0x4017e3 VBROADCASTSS	%XMM2,%YMM10

(2) 0x4017e8 VMOVUPS	0x4850(%RIP),%YMM9

(2) 0x4017f0 VFMADD231PS	%YMM9,%YMM4,%YMM10

(2) 0x4017f5 VMOVSS	0x481b(%RIP),%XMM13

(2) 0x4017fd VMULSS	%XMM0,%XMM13,%XMM7

(2) 0x401801 VMOVSHDUP	%XMM1,%XMM6

(2) 0x401805 VBROADCASTSD	%XMM6,%YMM5

(2) 0x40180a VBROADCASTSS	0x4809(%RIP),%YMM8

(2) 0x401813 VPERMPS	%YMM3,%YMM8,%YMM12

(2) 0x401818 VFMADD231PS	%YMM9,%YMM5,%YMM12

(2) 0x40181d VMULSS	%XMM6,%XMM13,%XMM8

(2) 0x401821 VBROADCASTSS	%XMM1,%YMM6

(2) 0x401826 VBROADCASTSS	%XMM3,%YMM11

(2) 0x40182b VFMADD231PS	%YMM9,%YMM6,%YMM11

(2) 0x401830 VMULSS	%XMM1,%XMM13,%XMM9

(2) 0x401834 OR	$0x2,%R8

(2) 0x401838 VBROADCASTSS	%XMM7,%YMM7

(2) 0x40183d VBROADCASTSS	%XMM8,%YMM8

(2) 0x401842 VBROADCASTSS	%XMM9,%YMM9

(2) 0x401847 MOV	$0x3,%R9D

(2) 0x40184d NOPL	(%RAX)

  (1) 0x401850 VADDPS	%YMM4,%YMM10,%YMM13

  (1) 0x401854 VADDPS	%YMM7,%YMM10,%YMM10

  (1) 0x401858 VMOVUPS	%YMM13,0x40a1b4(,%R9,4)

  (1) 0x401862 VADDPS	%YMM5,%YMM12,%YMM14

  (1) 0x401866 VADDPS	%YMM8,%YMM12,%YMM12

  (1) 0x40186b VMOVUPS	%YMM14,0x46bc34(,%R9,4)

  (1) 0x401875 VADDPS	%YMM6,%YMM11,%YMM14

  (1) 0x401879 VADDPS	%YMM9,%YMM11,%YMM11

  (1) 0x40187e VMOVUPS	%YMM14,0x4cd6b4(,%R9,4)

  (1) 0x401888 VPBROADCASTD	%R9D,%YMM14

  (1) 0x40188e VPADDD	%YMM16,%YMM14,%YMM14

  (1) 0x401894 VCVTUDQ2PS	%YMM14,%YMM14

  (1) 0x40189a VFMADD132PS	%YMM17,%YMM13,%YMM14

  (1) 0x4018a0 VMOVUPS	%YMM14,0x52f134(,%R9,4)

  (1) 0x4018aa ADD	$0x8,%R9

  (1) 0x4018ae CMP	%R8,%R9

  (1) 0x4018b1 JLE	401850

(2) 0x4018b3 CMP	%RDI,%RSI

(2) 0x4018b6 JE	401640

(2) 0x4018bc VCVTSI2SS	%RDI,%XMM18,%XMM4

(2) 0x4018c2 VADDSS	0x4756(%RIP),%XMM4,%XMM5

(2) 0x4018ca VBROADCASTSS	%XMM5,%XMM4

(2) 0x4018cf VFMADD213PS	%XMM3,%XMM1,%XMM4

(2) 0x4018d4 VFMADD231SS	%XMM5,%XMM0,%XMM2

(2) 0x4018d9 XOR	%ESI,%ESI

(2) 0x4018db NOPL	(%RAX,%RAX,1)

  (3) 0x4018e0 VADDSS	%XMM0,%XMM2,%XMM2

  (3) 0x4018e4 VMOVSS	%XMM2,0x40a1c0(%RAX,%RSI,4)

  (3) 0x4018ed VADDPS	%XMM1,%XMM4,%XMM4

  (3) 0x4018f1 VEXTRACTPS	$0x1,%XMM4,0x46bc40(%RAX,%RSI,4)

  (3) 0x4018fc VMOVSS	%XMM4,0x4cd6c0(%RAX,%RSI,4)

  (3) 0x401905 LEA	0x4(%RCX,%RSI,1),%EDI

  (3) 0x401909 VCVTUSI2SS	%EDI,%XMM18,%XMM3

  (3) 0x40190f VFMADD132SS	%XMM15,%XMM2,%XMM3

  (3) 0x401914 VMOVSS	%XMM3,0x52f140(%RAX,%RSI,4)

  (3) 0x40191d INC	%RSI

  (3) 0x401920 CMP	%RSI,%RDX

  (3) 0x401923 JNE	4018e0

(2) 0x401925 JMP	401640

0x40192a VMULSD	0x4756(%RIP),%XMM0,%XMM0

0x401932 MOV	$0x1,%EAX

0x401937 MOV	$0x4060e9,%EDI

0x40193c CALL	401030 <printf@plt>

0x401941 XOR	%EAX,%EAX

0x401943 ADD	$0x18,%RSP

0x401947 POP	%RBX

0x401948 POP	%R12

0x40194a POP	%R13

0x40194c POP	%R14

0x40194e POP	%R15

0x401950 POP	%RBP

0x401951 RET

0x401952 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○100.00	__libc_start_call_main		libc.so.6

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_6

Source file and lines	main.c:50-191
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:50,73-82,97,103-123,136-139,152,166-169,185,191.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.50 to 1.50 cycles (9.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__intel_new_feature_proc_init: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:50
__intel_new_feature_proc_init_n: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:50
__kmpc_fork_call@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:82
printf@plt: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:73
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:74
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:80
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:185
strncmp@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:77

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMOVSXBD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:97

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:97

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	72
nb uops	81
loop length	310
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.50	6.30	4.00	4.00	7.00	6.40	6.40	7.00	7.00	7.00	6.40	4.00
cycles	6.50	6.30	4.00	4.00	7.00	6.40	6.40	7.00	7.00	7.00	6.40	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.50
Dispatch	7.00
Overall L1	13.50

Vectorization ratios

INT

all	3%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	6%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

Vector efficiency ratios

INT

all	7%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	8%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	8%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.50 cycles. At this rate:

1% of peak load performance is reached (2.37 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.50 to 7.00 cycles (1.93x speedup).

ASM code

In the binary file, the address of the function is: 401540

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x10111ce4199d9fee,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
MOV $0x3,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 402290 <__intel_new_feature_proc_init>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x50,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 401f80 <__intel_new_feature_proc_init_n>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x406098,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xbb8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x4060a9,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x186a0,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP $0x2,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 4015c5 <main+0x85>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x8(%R14),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0x4060bd,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4010b0 <strncmp@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
MOV $0x3a98,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMOVE %RAX,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x4060c0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x40a0e0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x401960,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401110 <__kmpc_fork_call@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $-0x191,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $-0x33333333,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RBX,%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
SHR $0x24,%R14	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV $0x190,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x18c,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
VMOVSS 0x49f9(%RIP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VPMOVSXBD 0x4a6b(%RIP),%YMM16	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VBROADCASTSS 0x49e5(%RIP),%YMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 401702 <main+0x1c2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMULSD 0x4756(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x4060e9,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_6

Source file and lines	main.c:50-191
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:50,73-82,97,103-123,136-139,152,166-169,185,191.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.50 to 1.50 cycles (9.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

__intel_new_feature_proc_init: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:50
__intel_new_feature_proc_init_n: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:50
__kmpc_fork_call@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:82
printf@plt: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:73
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:74
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:80
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:185
strncmp@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:77

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMOVSXBD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:97

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:97

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	72
nb uops	81
loop length	310
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.50	6.30	4.00	4.00	7.00	6.40	6.40	7.00	7.00	7.00	6.40	4.00
cycles	6.50	6.30	4.00	4.00	7.00	6.40	6.40	7.00	7.00	7.00	6.40	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.50
Dispatch	7.00
Overall L1	13.50

Vectorization ratios

INT

all	3%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	6%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

Vector efficiency ratios

INT

all	7%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	8%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	8%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.50 cycles. At this rate:

1% of peak load performance is reached (2.37 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 401540

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x10111ce4199d9fee,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
MOV $0x3,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 402290 <__intel_new_feature_proc_init>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x50,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 401f80 <__intel_new_feature_proc_init_n>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x406098,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xbb8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x4060a9,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x186a0,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP $0x2,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 4015c5 <main+0x85>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x8(%R14),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0x4060bd,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4010b0 <strncmp@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
MOV $0x3a98,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMOVE %RAX,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x4060c0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x40a0e0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x401960,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401110 <__kmpc_fork_call@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $-0x191,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $-0x33333333,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RBX,%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
SHR $0x24,%R14	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV $0x190,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x18c,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
VMOVSS 0x49f9(%RIP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VPMOVSXBD 0x4a6b(%RIP),%YMM16	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VBROADCASTSS 0x49e5(%RIP),%YMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 401702 <main+0x1c2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMULSD 0x4756(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x4060e9,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼main–	0.07	0.00
▼Loop 2 - main.c:77-169 - exec–	0.00	0.00
○Loop 1 - main.c:111-116 - exec	0.07	1.27
○Loop 3 - main.c:111-116 - exec	0.00	0.00
○Loop 0 - main.c:111-116 - exec	0.00	0.00

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512-bits vectorization

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ASM code

Code clean check

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Vectorization

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Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

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Complex instructions

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Conversion instructions

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Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code