OV - exec - Function main.extracted.8

	Function: main.extracted.8	Module: exec	Source: main.c:139-147	Coverage (incl. loops): 0.16% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c: 139 - 147

--------------------------------------------------------------------------------

139:     #pragma omp parallel for private( dx1, dy1, dz1 )

140:       for ( i = 0; i < count; ++i)

141:       {

142:         Step10_orig( n, xx[i], yy[i], zz[i], fsrrmax2, mp_rsm2, xx, yy, zz, mass, &dx1, &dy1, &dz1 );

143:

144:         vx1[i] = vx1[i] + dx1 * fcoeff;

145:         vy1[i] = vy1[i] + dy1 * fcoeff;

146:         vz1[i] = vz1[i] + dz1 * fcoeff;

147:       }

0x401990 PUSH	%RBP

0x401991 MOV	%RSP,%RBP

0x401994 PUSH	%R15

0x401996 PUSH	%R14

0x401998 PUSH	%R13

0x40199a PUSH	%R12

0x40199c PUSH	%RBX

0x40199d SUB	$0x28,%RSP

0x4019a1 MOV	%R9,%R14

0x4019a4 MOVL	$0,-0x3c(%RBP)

0x4019ab MOV	(%RDI),%ESI

0x4019ad MOVL	$0,-0x30(%RBP)

0x4019b4 MOVL	$0xbb7,-0x2c(%RBP)

0x4019bb MOVL	$0x1,-0x38(%RBP)

0x4019c2 SUB	$0x8,%RSP

0x4019c6 LEA	-0x38(%RBP),%RAX

0x4019ca LEA	-0x3c(%RBP),%RCX

0x4019ce LEA	-0x30(%RBP),%R8

0x4019d2 LEA	-0x2c(%RBP),%R9

0x4019d6 MOV	$0x40a100,%EDI

0x4019db MOV	%ESI,-0x34(%RBP)

0x4019de MOV	$0x22,%EDX

0x4019e3 PUSH	$0x1

0x4019e5 PUSH	$0x1

0x4019e7 PUSH	%RAX

0x4019e8 CALL	401130 <__kmpc_for_static_init_4@plt>

0x4019ed ADD	$0x20,%RSP

0x4019f1 MOV	-0x30(%RBP),%R12D

0x4019f5 MOV	-0x2c(%RBP),%R13D

0x4019f9 CMP	%R13D,%R12D

0x4019fc JA	401adb

0x401a02 SUB	%R12,%R13

0x401a05 INC	%R13

0x401a08 XOR	%EBX,%EBX

0x401a0a SAL	$0x2,%R12

0x401a0e LEA	-0x40(%RBP),%R15

0x401a12 NOPW	%CS:(%RAX,%RAX,1)

(4) 0x401a20 VMOVSS	0x40a1b0(%R12,%RBX,4),%XMM0

(4) 0x401a2a VMOVSS	0x46bc30(%R12,%RBX,4),%XMM1

(4) 0x401a34 VMOVSS	0x4cd6b0(%R12,%RBX,4),%XMM2

(4) 0x401a3e MOV	$0x40a1b0,%ESI

(4) 0x401a43 MOV	$0x46bc30,%EDX

(4) 0x401a48 MOV	$0x4cd6b0,%ECX

(4) 0x401a4d MOV	$0x52f130,%R8D

(4) 0x401a53 MOV	%R14D,%EDI

(4) 0x401a56 VMOVSS	0x45c6(%RIP),%XMM3

(4) 0x401a5e VMOVSS	0x45c2(%RIP),%XMM4

(4) 0x401a66 MOV	%R15,%R9

(4) 0x401a69 LEA	-0x48(%RBP),%RAX

(4) 0x401a6d PUSH	%RAX

(4) 0x401a6e LEA	-0x44(%RBP),%RAX

(4) 0x401a72 PUSH	%RAX

(4) 0x401a73 CALL	401b60 <Step10_orig>

(4) 0x401a78 ADD	$0x10,%RSP

(4) 0x401a7c VMOVSS	-0x40(%RBP),%XMM0

(4) 0x401a81 VMOVSS	0x45a3(%RIP),%XMM1

(4) 0x401a89 VFMADD213SS	0x590bb0(%R12,%RBX,4),%XMM1,%XMM0

(4) 0x401a93 VMOVSS	%XMM0,0x590bb0(%R12,%RBX,4)

(4) 0x401a9d VMOVSS	-0x44(%RBP),%XMM0

(4) 0x401aa2 VFMADD213SS	0x5f2630(%R12,%RBX,4),%XMM1,%XMM0

(4) 0x401aac VMOVSS	%XMM0,0x5f2630(%R12,%RBX,4)

(4) 0x401ab6 VMOVSS	-0x48(%RBP),%XMM0

(4) 0x401abb VFMADD213SS	0x6540b0(%R12,%RBX,4),%XMM1,%XMM0

(4) 0x401ac5 VMOVSS	%XMM0,0x6540b0(%R12,%RBX,4)

(4) 0x401acf INC	%RBX

(4) 0x401ad2 CMP	%RBX,%R13

(4) 0x401ad5 JNE	401a20

0x401adb MOV	$0x40a120,%EDI

0x401ae0 MOV	-0x34(%RBP),%ESI

0x401ae3 CALL	4010a0 <__kmpc_for_static_fini@plt>

0x401ae8 ADD	$0x28,%RSP

0x401aec POP	%RBX

0x401aed POP	%R12

0x401aef POP	%R13

0x401af1 POP	%R14

0x401af3 POP	%R15

0x401af5 POP	%RBP

0x401af6 RET

0x401af7 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►99.82+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_6

Source file and lines	main.c:139-147
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:139-147.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.50 to 0.56 cycles (15.08x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:139
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:139

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	49
nb uops	51
loop length	181
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.70	1.60	3.67	3.67	8.00	1.60	1.50	8.00	8.00	8.00	1.60	3.67
cycles	1.70	1.60	3.67	3.67	8.00	1.60	1.50	8.00	8.00	8.00	1.60	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.50
Dispatch	8.00
Overall L1	8.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.50 cycles. At this rate:

0% of peak load performance is reached (1.88 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.35 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.50 to 8.00 cycles (1.06x speedup).

ASM code

In the binary file, the address of the function is: 401990

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0xbb7,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x3c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x40a100,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 401130 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x2c(%RBP),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CMP %R13D,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JA 401adb <main.extracted.8+0x14b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %R12,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
INC %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x2,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
LEA -0x40(%RBP),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x40a120,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CALL 4010a0 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_6

Source file and lines	main.c:139-147
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:139-147.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:139
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:139

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	49
nb uops	51
loop length	181
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.70	1.60	3.67	3.67	8.00	1.60	1.50	8.00	8.00	8.00	1.60	3.67
cycles	1.70	1.60	3.67	3.67	8.00	1.60	1.50	8.00	8.00	8.00	1.60	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.50
Dispatch	8.00
Overall L1	8.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.50 cycles. At this rate:

0% of peak load performance is reached (1.88 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.35 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 401990

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0xbb7,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x3c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x40a100,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 401130 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x2c(%RBP),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CMP %R13D,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JA 401adb <main.extracted.8+0x14b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %R12,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
INC %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x2,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
LEA -0x40(%RBP),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x40a120,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CALL 4010a0 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.8–	0.16	0.01
○Loop 4 - main.c:140-147 - exec	0.16	0.01

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