OV - exec - Loop 2

	Loop Id: 2	Module: exec	Source: main.c:142-146	Coverage: 0.07%

0x401799 VMOVSS	0x64ef80(,%RBX,4),%XMM2    [1]

0x4017a2 VMOVSS	0x5ed500(,%RBX,4),%XMM1    [1]

0x4017ab VMOVSS	0x58ba80(,%RBX,4),%XMM0    [1]

0x4017b4 VMOVSS	%XMM6,-0x58(%RBP)    [2]

0x4017b9 PUSH	%R14

0x4017bb LEA	-0x3c(%RBP),%R9

0x4017bf MOV	$0x52a000,%R8D

0x4017c5 PUSH	%R13

0x4017c7 MOV	$0x64ef80,%ECX

0x4017cc MOV	$0x5ed500,%EDX

0x4017d1 MOV	$0x58ba80,%ESI

0x4017d6 MOV	%R12D,%EDI

0x4017d9 VMOVSS	%XMM4,-0x4c(%RBP)    [2]

0x4017de VMOVSS	%XMM3,-0x48(%RBP)    [2]

0x4017e3 CALL	4019c0 <Step10_orig>

0x4017e8 VMOVSS	-0x58(%RBP),%XMM9    [2]

0x4017ed VMOVSS	-0x3c(%RBP),%XMM8    [2]

0x4017f2 VMOVSS	-0x38(%RBP),%XMM10    [2]

0x4017f7 VMOVSS	-0x34(%RBP),%XMM11    [2]

0x4017fc VFMADD213SS	0x4c8580(,%RBX,4),%XMM9,%XMM8    [1]

0x401806 VFMADD213SS	0x466b00(,%RBX,4),%XMM9,%XMM10    [1]

0x401810 VFMADD213SS	0x405080(,%RBX,4),%XMM9,%XMM11    [1]

0x40181a LEA	0x1(%RBX),%R15

0x40181e VMOVSS	0x64ef80(,%R15,4),%XMM2    [1]

0x401828 VMOVSS	%XMM8,0x4c8580(,%RBX,4)    [1]

0x401831 VMOVSS	%XMM10,0x466b00(,%RBX,4)    [1]

0x40183a VMOVSS	%XMM11,0x405080(,%RBX,4)    [1]

0x401843 POP	%RCX

0x401844 POP	%RSI

0x401845 VMOVSS	0x5ed500(,%R15,4),%XMM1    [1]

0x40184f VMOVSS	0x58ba80(,%R15,4),%XMM0    [1]

0x401859 PUSH	%R14

0x40185b VMOVSS	-0x4c(%RBP),%XMM4    [2]

0x401860 VMOVSS	-0x48(%RBP),%XMM3    [2]

0x401865 PUSH	%R13

0x401867 MOV	$0x52a000,%R8D

0x40186d MOV	%R12D,%EDI

0x401870 LEA	-0x3c(%RBP),%R9

0x401874 MOV	$0x64ef80,%ECX

0x401879 MOV	$0x5ed500,%EDX

0x40187e MOV	$0x58ba80,%ESI

0x401883 CALL	4019c0 <Step10_orig>

0x401888 VMOVSS	-0x58(%RBP),%XMM6    [2]

0x40188d VMOVSS	-0x3c(%RBP),%XMM12    [2]

0x401892 VMOVSS	-0x38(%RBP),%XMM13    [2]

0x401897 VMOVSS	-0x34(%RBP),%XMM14    [2]

0x40189c VFMADD213SS	0x4c8580(,%R15,4),%XMM6,%XMM12    [1]

0x4018a6 VFMADD213SS	0x466b00(,%R15,4),%XMM6,%XMM13    [1]

0x4018b0 VFMADD213SS	0x405080(,%R15,4),%XMM6,%XMM14    [1]

0x4018ba ADD	$0x2,%RBX

0x4018be CMP	%EBX,-0x50(%RBP)    [2]

0x4018c1 VMOVSS	%XMM12,0x4c8580(,%R15,4)    [1]

0x4018cb VMOVSS	%XMM13,0x466b00(,%R15,4)    [1]

0x4018d5 VMOVSS	%XMM14,0x405080(,%R15,4)    [1]

0x4018df POP	%RDI

0x4018e0 VMOVSS	-0x48(%RBP),%XMM3    [2]

0x4018e5 VMOVSS	-0x4c(%RBP),%XMM4    [2]

0x4018ea POP	%R8

0x4018ec JG	401799

/home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c: 142 - 146

--------------------------------------------------------------------------------

142:         Step10_orig( n, xx[i], yy[i], zz[i], fsrrmax2, mp_rsm2, xx, yy, zz, mass, &dx1, &dy1, &dz1 );

143:

144:         vx1[i] = vx1[i] + dx1 * fcoeff;

145:         vy1[i] = vy1[i] + dy1 * fcoeff;

146:         vz1[i] = vz1[i] + dz1 * fcoeff;

Coverage (%)	Name	Source Location	Module
○100.00	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.34
CQA speedup if FP arith vectorized	1.38
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.16
Bottlenecks	micro-operation queue,
Function	main._omp_fn.1
Source	main.c:142-146
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.17
CQA cycles if no scalar integer	8.33
CQA cycles if FP arith vectorized	8.10
CQA cycles if fully vectorized	0.70
Front-end cycles	11.17
P0 cycles	3.20
P1 cycles	3.20
P2 cycles	9.67
P3 cycles	9.67
P4 cycles	7.50
P5 cycles	3.20
P6 cycles	3.20
P7 cycles	7.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	3.20
P11 cycles	9.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	61.00
Nb loads	25.00
Nb stores	9.00
Nb stack references	7.00
FLOP/cycle	1.07
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	6.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.18
Bytes prefetched	0.00
Bytes loaded	100.00
Bytes stored	36.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.34
CQA speedup if FP arith vectorized	1.38
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.16
Bottlenecks	micro-operation queue,
Function	main._omp_fn.1
Source	main.c:142-146
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.17
CQA cycles if no scalar integer	8.33
CQA cycles if FP arith vectorized	8.10
CQA cycles if fully vectorized	0.70
Front-end cycles	11.17
P0 cycles	3.20
P1 cycles	3.20
P2 cycles	9.67
P3 cycles	9.67
P4 cycles	7.50
P5 cycles	3.20
P6 cycles	3.20
P7 cycles	7.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	3.20
P11 cycles	9.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	61.00
Nb loads	25.00
Nb stores	9.00
Nb stack references	7.00
FLOP/cycle	1.07
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	6.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.18
Bytes prefetched	0.00
Bytes loaded	100.00
Bytes stored	36.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.1
Source file and lines	main.c:142-146
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:142-146.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.17 to 8.33 cycles (1.34x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 11.17 to 0.70 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 6 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

Step10_orig: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:142
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:142

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12 FP arithmetical operations:

6: addition or subtraction (all inside FMA instructions)
6: multiply (all inside FMA instructions)

The binary loop is loading 100 bytes (25 single precision FP elements). The binary loop is storing 36 bytes (9 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	59
nb uops	61
loop length	345
used x86 registers	12
used mmx registers	0
used xmm registers	13
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.17 cycles
front end	11.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.20	3.20	9.67	9.67	7.50	3.20	3.20	7.50	7.50	7.50	3.20	9.67
cycles	3.20	3.20	9.67	9.67	7.50	3.20	3.20	7.50	7.50	7.50	3.20	9.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	11.17
Dispatch	9.67
Data deps.	1.00
Overall L1	11.17

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.17 cycles. At this rate:

4% of peak load performance is reached (8.96 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.22 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.17 to 9.67 cycles (1.16x speedup).

ASM code

In the binary file, the address of the loop is: 401799

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSS 0x64ef80(,%RBX,4),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x5ed500(,%RBX,4),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x58ba80(,%RBX,4),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS %XMM6,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
LEA -0x3c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x52a000,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x64ef80,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x5ed500,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x58ba80,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R12D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VMOVSS %XMM4,-0x4c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM3,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 4019c0 <Step10_orig>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS -0x58(%RBP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS -0x3c(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS -0x38(%RBP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS -0x34(%RBP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VFMADD213SS 0x4c8580(,%RBX,4),%XMM9,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x466b00(,%RBX,4),%XMM9,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x405080(,%RBX,4),%XMM9,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
LEA 0x1(%RBX),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSS 0x64ef80(,%R15,4),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS %XMM8,0x4c8580(,%RBX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM10,0x466b00(,%RBX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM11,0x405080(,%RBX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
POP %RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VMOVSS 0x5ed500(,%R15,4),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x58ba80(,%R15,4),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
VMOVSS -0x4c(%RBP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS -0x48(%RBP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x52a000,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R12D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA -0x3c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x64ef80,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x5ed500,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x58ba80,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4019c0 <Step10_orig>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS -0x58(%RBP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS -0x3c(%RBP),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS -0x38(%RBP),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS -0x34(%RBP),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VFMADD213SS 0x4c8580(,%R15,4),%XMM6,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x466b00(,%R15,4),%XMM6,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x405080(,%R15,4),%XMM6,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
ADD $0x2,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EBX,-0x50(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
VMOVSS %XMM12,0x4c8580(,%R15,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM13,0x466b00(,%R15,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM14,0x405080(,%R15,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
POP %RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VMOVSS -0x48(%RBP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS -0x4c(%RBP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
POP %R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JG 401799 <main._omp_fn.1+0x209>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main._omp_fn.1
Source file and lines	main.c:142-146
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:142-146.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.17 to 8.33 cycles (1.34x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 11.17 to 0.70 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 6 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Step10_orig: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:142
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:142

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12 FP arithmetical operations:

6: addition or subtraction (all inside FMA instructions)
6: multiply (all inside FMA instructions)

The binary loop is loading 100 bytes (25 single precision FP elements). The binary loop is storing 36 bytes (9 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	59
nb uops	61
loop length	345
used x86 registers	12
used mmx registers	0
used xmm registers	13
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.17 cycles
front end	11.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.20	3.20	9.67	9.67	7.50	3.20	3.20	7.50	7.50	7.50	3.20	9.67
cycles	3.20	3.20	9.67	9.67	7.50	3.20	3.20	7.50	7.50	7.50	3.20	9.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	11.17
Dispatch	9.67
Data deps.	1.00
Overall L1	11.17

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.17 cycles. At this rate:

4% of peak load performance is reached (8.96 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.22 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 401799

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSS 0x64ef80(,%RBX,4),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x5ed500(,%RBX,4),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x58ba80(,%RBX,4),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS %XMM6,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
LEA -0x3c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x52a000,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x64ef80,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x5ed500,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x58ba80,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R12D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VMOVSS %XMM4,-0x4c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM3,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 4019c0 <Step10_orig>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS -0x58(%RBP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS -0x3c(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS -0x38(%RBP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS -0x34(%RBP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VFMADD213SS 0x4c8580(,%RBX,4),%XMM9,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x466b00(,%RBX,4),%XMM9,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x405080(,%RBX,4),%XMM9,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
LEA 0x1(%RBX),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSS 0x64ef80(,%R15,4),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS %XMM8,0x4c8580(,%RBX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM10,0x466b00(,%RBX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM11,0x405080(,%RBX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
POP %RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VMOVSS 0x5ed500(,%R15,4),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x58ba80(,%R15,4),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
VMOVSS -0x4c(%RBP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS -0x48(%RBP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x52a000,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R12D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA -0x3c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x64ef80,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x5ed500,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x58ba80,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4019c0 <Step10_orig>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS -0x58(%RBP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS -0x3c(%RBP),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS -0x38(%RBP),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS -0x34(%RBP),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VFMADD213SS 0x4c8580(,%R15,4),%XMM6,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x466b00(,%R15,4),%XMM6,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x405080(,%R15,4),%XMM6,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
ADD $0x2,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EBX,-0x50(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
VMOVSS %XMM12,0x4c8580(,%R15,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM13,0x466b00(,%R15,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM14,0x405080(,%R15,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
POP %RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VMOVSS -0x48(%RBP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS -0x4c(%RBP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
POP %R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JG 401799 <main._omp_fn.1+0x209>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

CALL instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

CALL instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code