OV - exec - Loop 0

	Loop Id: 0	Module: exec	Source: main.c:111-116	Coverage: 0.07%

0x401271 VADDSS	%XMM10,%XMM0,%XMM14

0x401276 VADDSS	%XMM6,%XMM2,%XMM15

0x40127a LEA	0x2(%R13),%RSI

0x40127e VADDSS	%XMM10,%XMM14,%XMM12

0x401283 VMOVSS	%XMM15,0x5ed500(,%R13,4)    [1]

0x40128d VADDSS	%XMM6,%XMM15,%XMM2

0x401291 VADDSS	%XMM11,%XMM1,%XMM3

0x401296 VCVTSI2SS	%ESI,%XMM7,%XMM15

0x40129a VADDSS	%XMM10,%XMM12,%XMM0

0x40129f LEA	0x1(%R13),%RCX

0x4012a3 LEA	0x3(%R13),%RDI

0x4012a7 VCVTSI2SS	%R13D,%XMM7,%XMM5

0x4012ac VMOVSS	%XMM3,0x64ef80(,%R13,4)    [1]

0x4012b6 VADDSS	%XMM11,%XMM3,%XMM1

0x4012bb VCVTSI2SS	%ECX,%XMM7,%XMM4

0x4012bf VCVTSI2SS	%EDI,%XMM7,%XMM3

0x4012c3 VMOVSS	%XMM14,0x58ba80(,%R13,4)    [1]

0x4012cd VFMADD132SS	%XMM8,%XMM0,%XMM15

0x4012d2 VMOVSS	%XMM12,0x58ba80(,%RCX,4)    [1]

0x4012db VMOVSS	%XMM0,0x58ba80(,%RSI,4)    [1]

0x4012e4 VADDSS	%XMM10,%XMM0,%XMM0

0x4012e9 VFMADD132SS	%XMM8,%XMM14,%XMM5

0x4012ee VADDSS	%XMM6,%XMM2,%XMM13

0x4012f2 VADDSS	%XMM11,%XMM1,%XMM14

0x4012f7 VFMADD132SS	%XMM8,%XMM12,%XMM4

0x4012fc VFMADD132SS	%XMM8,%XMM0,%XMM3

0x401301 VMOVSS	%XMM2,0x5ed500(,%RCX,4)    [1]

0x40130a VMOVSS	%XMM1,0x64ef80(,%RCX,4)    [1]

0x401313 VADDSS	%XMM6,%XMM13,%XMM2

0x401317 VADDSS	%XMM11,%XMM14,%XMM1

0x40131c VMOVSS	%XMM5,0x52a000(,%R13,4)    [1]

0x401326 ADD	$0x4,%R13

0x40132a VMOVSS	%XMM4,0x52a000(,%RCX,4)    [1]

0x401333 VMOVSS	%XMM13,0x5ed500(,%RSI,4)    [1]

0x40133c VMOVSS	%XMM14,0x64ef80(,%RSI,4)    [1]

0x401345 VMOVSS	%XMM15,0x52a000(,%RSI,4)    [1]

0x40134e VMOVSS	%XMM0,0x58ba80(,%RDI,4)    [1]

0x401357 VMOVSS	%XMM2,0x5ed500(,%RDI,4)    [1]

0x401360 VMOVSS	%XMM1,0x64ef80(,%RDI,4)    [1]

0x401369 VMOVSS	%XMM3,0x52a000(,%RDI,4)    [1]

0x401372 CMP	%RAX,%R13

0x401375 JNE	401271

/home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c: 111 - 116

--------------------------------------------------------------------------------

111:       for ( i = 1; i < n; i++ )

112:       {

113:           xx[i] = xx[i-1] + dx1;

114:           yy[i] = yy[i-1] + dy1;

115:           zz[i] = zz[i-1] + dz1;

116:           mass[i] = (float)i * 0.01f + xx[i];

Coverage (%)	Name	Source Location	Module
○100.00	__libc_start_call_main		libc.so.6

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks
Function	main
Source	main.c:111-116
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	0.75
Front-end cycles	7.50
P0 cycles	7.50
P1 cycles	8.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	8.00
P5 cycles	8.00
P6 cycles	1.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.00
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	12
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	45.00
Nb loads	0.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	1.67
Nb FLOP add-sub	12.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.33
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks
Function	main
Source	main.c:111-116
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	0.75
Front-end cycles	7.50
P0 cycles	7.50
P1 cycles	8.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	8.00
P5 cycles	8.00
P6 cycles	1.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.00
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	12
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	45.00
Nb loads	0.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	1.67
Nb FLOP add-sub	12.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.33
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	main.c:111-116
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:111-116.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 4 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSI2SS: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSI2SS (INT32/64 to FP32, scalar): 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

16 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

16: addition or subtraction (4 inside FMA instructions)
4: multiply (all inside FMA instructions)

The binary loop is storing 64 bytes (16 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	42
nb uops	45
loop length	266
used x86 registers	5
used mmx registers	0
used xmm registers	15
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.50	8.50	0.00	0.00	8.00	8.00	1.00	8.00	8.00	8.00	0.00	0.00
cycles	7.50	8.50	0.00	0.00	8.00	8.00	1.00	8.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	12.00

Cycles summary

Front-end	7.50
Dispatch	8.50
Data deps.	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

4% of peak store performance is reached (5.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401271

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
VADDSS %XMM10,%XMM0,%XMM14	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VADDSS %XMM6,%XMM2,%XMM15	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
LEA 0x2(%R13),%RSI	1	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSS %XMM10,%XMM14,%XMM12	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSS %XMM15,0x5ed500(,%R13,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VADDSS %XMM6,%XMM15,%XMM2	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VADDSS %XMM11,%XMM1,%XMM3	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VCVTSI2SS %ESI,%XMM7,%XMM15	2	0.50	0.50	0	1	0	0	0	0	0	7	1	scal (6.3%)
VADDSS %XMM10,%XMM12,%XMM0	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
LEA 0x1(%R13),%RCX	1	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x3(%R13),%RDI	1	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VCVTSI2SS %R13D,%XMM7,%XMM5	2	0.50	0.50	0	1	0	0	0	0	0	7	1	scal (6.3%)
VMOVSS %XMM3,0x64ef80(,%R13,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VADDSS %XMM11,%XMM3,%XMM1	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VCVTSI2SS %ECX,%XMM7,%XMM4	2	0.50	0.50	0	1	0	0	0	0	0	7	1	scal (6.3%)
VCVTSI2SS %EDI,%XMM7,%XMM3	2	0.50	0.50	0	1	0	0	0	0	0	7	1	scal (6.3%)
VMOVSS %XMM14,0x58ba80(,%R13,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VFMADD132SS %XMM8,%XMM0,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM12,0x58ba80(,%RCX,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM0,0x58ba80(,%RSI,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VADDSS %XMM10,%XMM0,%XMM0	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VFMADD132SS %XMM8,%XMM14,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VADDSS %XMM6,%XMM2,%XMM13	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VADDSS %XMM11,%XMM1,%XMM14	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VFMADD132SS %XMM8,%XMM12,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD132SS %XMM8,%XMM0,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM2,0x5ed500(,%RCX,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM1,0x64ef80(,%RCX,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VADDSS %XMM6,%XMM13,%XMM2	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VADDSS %XMM11,%XMM14,%XMM1	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSS %XMM5,0x52a000(,%R13,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
ADD $0x4,%R13	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS %XMM4,0x52a000(,%RCX,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM13,0x5ed500(,%RSI,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM14,0x64ef80(,%RSI,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM15,0x52a000(,%RSI,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM0,0x58ba80(,%RDI,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM2,0x5ed500(,%RDI,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM1,0x64ef80(,%RDI,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM3,0x52a000(,%RDI,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
CMP %RAX,%R13	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
JNE 401271 <main+0x1d1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	main.c:111-116
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:111-116.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 4 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSI2SS: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSI2SS (INT32/64 to FP32, scalar): 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:116

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

16 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

16: addition or subtraction (4 inside FMA instructions)
4: multiply (all inside FMA instructions)

The binary loop is storing 64 bytes (16 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	42
nb uops	45
loop length	266
used x86 registers	5
used mmx registers	0
used xmm registers	15
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.50	8.50	0.00	0.00	8.00	8.00	1.00	8.00	8.00	8.00	0.00	0.00
cycles	7.50	8.50	0.00	0.00	8.00	8.00	1.00	8.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	12.00

Cycles summary

Front-end	7.50
Dispatch	8.50
Data deps.	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

4% of peak store performance is reached (5.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401271

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
VADDSS %XMM10,%XMM0,%XMM14	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VADDSS %XMM6,%XMM2,%XMM15	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
LEA 0x2(%R13),%RSI	1	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSS %XMM10,%XMM14,%XMM12	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSS %XMM15,0x5ed500(,%R13,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VADDSS %XMM6,%XMM15,%XMM2	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VADDSS %XMM11,%XMM1,%XMM3	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VCVTSI2SS %ESI,%XMM7,%XMM15	2	0.50	0.50	0	1	0	0	0	0	0	7	1	scal (6.3%)
VADDSS %XMM10,%XMM12,%XMM0	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
LEA 0x1(%R13),%RCX	1	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x3(%R13),%RDI	1	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VCVTSI2SS %R13D,%XMM7,%XMM5	2	0.50	0.50	0	1	0	0	0	0	0	7	1	scal (6.3%)
VMOVSS %XMM3,0x64ef80(,%R13,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VADDSS %XMM11,%XMM3,%XMM1	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VCVTSI2SS %ECX,%XMM7,%XMM4	2	0.50	0.50	0	1	0	0	0	0	0	7	1	scal (6.3%)
VCVTSI2SS %EDI,%XMM7,%XMM3	2	0.50	0.50	0	1	0	0	0	0	0	7	1	scal (6.3%)
VMOVSS %XMM14,0x58ba80(,%R13,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VFMADD132SS %XMM8,%XMM0,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM12,0x58ba80(,%RCX,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM0,0x58ba80(,%RSI,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VADDSS %XMM10,%XMM0,%XMM0	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VFMADD132SS %XMM8,%XMM14,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VADDSS %XMM6,%XMM2,%XMM13	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VADDSS %XMM11,%XMM1,%XMM14	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VFMADD132SS %XMM8,%XMM12,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD132SS %XMM8,%XMM0,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM2,0x5ed500(,%RCX,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM1,0x64ef80(,%RCX,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VADDSS %XMM6,%XMM13,%XMM2	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VADDSS %XMM11,%XMM14,%XMM1	1	0	0.50	0	0.50	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSS %XMM5,0x52a000(,%R13,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
ADD $0x4,%R13	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS %XMM4,0x52a000(,%RCX,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM13,0x5ed500(,%RSI,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM14,0x64ef80(,%RSI,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM15,0x52a000(,%RSI,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM0,0x58ba80(,%RDI,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM2,0x5ed500(,%RDI,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM1,0x64ef80(,%RDI,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVSS %XMM3,0x52a000(,%RDI,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
CMP %RAX,%R13	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
JNE 401271 <main+0x1d1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code