OV - exec - Function Step10

	Function: Step10_orig	Module: exec	Source: Step10_orig.c:10-41 [...]	Coverage (incl. loops): 67.22% \| (excl. loops): 0.01%

/home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 10 - 41

--------------------------------------------------------------------------------

10: {

[...]

17:     xi = 0.; yi = 0.; zi = 0.;

18:

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

36:     }

37:

38:     *dxi = xi;

39:     *dyi = yi;

40:     *dzi = zi;

41: }

0x4019c0 PUSH	%RBP

0x4019c1 MOV	%EDI,%R10D

0x4019c4 MOV	%RSP,%RBP

0x4019c7 PUSH	%RBX

0x4019c8 TEST	%EDI,%EDI

0x4019ca JLE	402030

0x4019d0 LEA	-0x1(%R10),%EAX

0x4019d4 MOV	%RSI,%RDI

0x4019d7 VMOVAPS	%XMM0,%XMM27

0x4019dd MOV	%RDX,%RSI

0x4019e0 MOV	%RCX,%RDX

0x4019e3 CMP	$0x6,%EAX

0x4019e6 JBE	40203e

0x4019ec MOV	%R10D,%EBX

0x4019ef VXORPS	%XMM12,%XMM12,%XMM12

0x4019f4 SHR	$0x3,%EBX

0x4019f7 VBROADCASTSS	0x169f(%RIP),%YMM22

0x401a01 VBROADCASTSS	0x1699(%RIP),%YMM21

0x401a0b VBROADCASTSS	0x1693(%RIP),%YMM20

0x401a15 VBROADCASTSS	0x168d(%RIP),%YMM19

0x401a1f VBROADCASTSS	0x1687(%RIP),%YMM18

0x401a29 VBROADCASTSS	0x1681(%RIP),%YMM17

0x401a33 VBROADCASTSD	0x167c(%RIP),%YMM14

0x401a3c VBROADCASTSS	%XMM0,%YMM26

0x401a42 VBROADCASTSS	%XMM1,%YMM25

0x401a48 VBROADCASTSS	%XMM2,%YMM24

0x401a4e VBROADCASTSS	%XMM3,%YMM15

0x401a53 VBROADCASTSS	%XMM4,%YMM23

0x401a59 SAL	$0x5,%RBX

0x401a5d XOR	%R11D,%R11D

0x401a60 VMOVAPS	%YMM12,%YMM11

0x401a65 VMOVAPS	%YMM12,%YMM10

0x401a6a VMOVAPS	%YMM12,%YMM16

0x401a70 VMOVAPS	%XMM1,%XMM31

0x401a76 NOPW	%CS:(%RAX,%RAX,1)

(3) 0x401a80 VMOVUPS	(%RSI,%R11,1),%YMM8

(3) 0x401a86 VMOVUPS	(%RDX,%R11,1),%YMM1

(3) 0x401a8c VSUBPS	%YMM25,%YMM8,%YMM8

(3) 0x401a92 VSUBPS	%YMM24,%YMM1,%YMM7

(3) 0x401a98 VMOVUPS	(%RDI,%R11,1),%YMM9

(3) 0x401a9e VMULPS	%YMM8,%YMM8,%YMM1

(3) 0x401aa3 VSUBPS	%YMM26,%YMM9,%YMM9

(3) 0x401aa9 VFMADD231PS	%YMM9,%YMM9,%YMM1

(3) 0x401aae VFMADD231PS	%YMM7,%YMM7,%YMM1

(3) 0x401ab3 VCMPPS	$0x1,%YMM15,%YMM1,%K1

(3) 0x401aba VADDPS	%YMM23,%YMM1,%YMM5

(3) 0x401ac0 VCMPPS	$0x1,%YMM15,%YMM1,%YMM0

(3) 0x401ac6 VMOVUPS	(%R8,%R11,1),%YMM13{%K1}

(3) 0x401acd VCVTPS2PD	%XMM5,%YMM6

(3) 0x401ad1 VANDPS	%YMM13,%YMM0,%YMM28

(3) 0x401ad7 VEXTRACTF32X4	$0x1,%YMM5,%XMM0

(3) 0x401ade VCVTPS2PD	%XMM0,%YMM5

(3) 0x401ae2 VMOVAPS	%YMM1,%YMM0

(3) 0x401ae6 VFMADD132PS	%YMM22,%YMM21,%YMM0

(3) 0x401aec VSQRTPD	%YMM6,%YMM30

(3) 0x401af2 VCMPPS	$0xe,%YMM16,%YMM1,%K2

(3) 0x401af9 VSQRTPD	%YMM5,%YMM29

(3) 0x401aff ADD	$0x20,%R11

(3) 0x401b03 VFMADD132PS	%YMM1,%YMM20,%YMM0

(3) 0x401b09 VMULPD	%YMM29,%YMM5,%YMM5

(3) 0x401b0f VFMADD132PS	%YMM1,%YMM19,%YMM0

(3) 0x401b15 VFMADD132PS	%YMM1,%YMM18,%YMM0

(3) 0x401b1b VFMADD132PS	%YMM1,%YMM17,%YMM0

(3) 0x401b21 VMULPD	%YMM30,%YMM6,%YMM1

(3) 0x401b27 VCVTPS2PD	%XMM0,%YMM30

(3) 0x401b2d VDIVPD	%YMM1,%YMM14,%YMM6

(3) 0x401b31 VEXTRACTF32X4	$0x1,%YMM0,%XMM0

(3) 0x401b38 VADDPD	%YMM30,%YMM6,%YMM1

(3) 0x401b3e VDIVPD	%YMM5,%YMM14,%YMM6

(3) 0x401b42 VCVTPS2PD	%XMM0,%YMM5

(3) 0x401b46 VCVTPD2PS	%YMM1,%XMM1

(3) 0x401b4a VADDPD	%YMM5,%YMM6,%YMM0

(3) 0x401b4e VCVTPD2PS	%YMM0,%XMM6

(3) 0x401b52 VINSERTF32X4	$0x1,%XMM6,%YMM1,%YMM5

(3) 0x401b59 VMULPS	%YMM28,%YMM5,%YMM0

(3) 0x401b5f VFMADD231PS	%YMM0,%YMM9,%YMM10{%K2}

(3) 0x401b65 VFMADD231PS	%YMM0,%YMM8,%YMM11{%K2}

(3) 0x401b6b VFMADD231PS	%YMM0,%YMM7,%YMM12{%K2}

(3) 0x401b71 CMP	%R11,%RBX

(3) 0x401b74 JNE	401a80

0x401b7a VEXTRACTF32X4	$0x1,%YMM11,%XMM8

0x401b81 VADDPS	%XMM11,%XMM8,%XMM11

0x401b86 VEXTRACTF32X4	$0x1,%YMM12,%XMM13

0x401b8d VADDPS	%XMM12,%XMM13,%XMM15

0x401b92 VMOVHLPS	%XMM11,%XMM11,%XMM7

0x401b97 VADDPS	%XMM11,%XMM7,%XMM6

0x401b9c VEXTRACTF32X4	$0x1,%YMM10,%XMM13

0x401ba3 VMOVHLPS	%XMM15,%XMM15,%XMM12

0x401ba8 VSHUFPS	$0x55,%XMM6,%XMM6,%XMM5

0x401bad VADDPS	%XMM6,%XMM5,%XMM5

0x401bb1 VADDPS	%XMM10,%XMM13,%XMM6

0x401bb6 VADDPS	%XMM15,%XMM12,%XMM14

0x401bbb MOV	%R10D,%EAX

0x401bbe VMOVHLPS	%XMM6,%XMM6,%XMM10

0x401bc2 VADDPS	%XMM6,%XMM10,%XMM12

0x401bc6 AND	$-0x8,%EAX

0x401bc9 VSHUFPS	$0x55,%XMM14,%XMM14,%XMM9

0x401bcf VMOVAPS	%XMM31,%XMM1

0x401bd5 VADDPS	%XMM14,%XMM9,%XMM0

0x401bda MOV	%EAX,%ECX

0x401bdc VSHUFPS	$0x55,%XMM12,%XMM12,%XMM14

0x401be2 VMOVAPS	%XMM15,%XMM10

0x401be7 VADDPS	%XMM12,%XMM14,%XMM7

0x401bec CMP	%EAX,%R10D

0x401bef JE	401ff8

0x401bf5 MOV	%R10D,%R11D

0x401bf8 SUB	%ECX,%R11D

0x401bfb LEA	-0x1(%R11),%EBX

0x401bff CMP	$0x2,%EBX

0x401c02 JBE	401d8b

0x401c08 VMOVUPS	(%RSI,%RCX,4),%XMM7

0x401c0d VBROADCASTSS	%XMM1,%XMM5

0x401c12 VSUBPS	%XMM5,%XMM7,%XMM13

0x401c16 VMOVUPS	(%RDI,%RCX,4),%XMM8

0x401c1b VBROADCASTSS	%XMM27,%XMM0

0x401c21 VMULPS	%XMM13,%XMM13,%XMM5

0x401c26 VSUBPS	%XMM0,%XMM8,%XMM14

0x401c2a VMOVUPS	(%RDX,%RCX,4),%XMM12

0x401c2f VBROADCASTSS	%XMM2,%XMM8

0x401c34 VSUBPS	%XMM8,%XMM12,%XMM12

0x401c39 VFMADD231PS	%XMM14,%XMM14,%XMM5

0x401c3e VBROADCASTSS	%XMM3,%XMM15

0x401c43 VBROADCASTSS	%XMM4,%XMM9

0x401c48 VXORPS	%XMM8,%XMM8,%XMM8

0x401c4d VFMADD231PS	%XMM12,%XMM12,%XMM5

0x401c52 VCMPPS	$0x1,%XMM15,%XMM5,%K0

0x401c59 VCMPPS	$0x1,%XMM15,%XMM5,%XMM15

0x401c5f VADDPS	%XMM9,%XMM5,%XMM9

0x401c64 KMOVB	%K0,%EBX

0x401c68 AND	$0xf,%EBX

0x401c6b KMOVB	%EBX,%K3

0x401c6f VMOVUPS	(%R8,%RCX,4),%XMM0{%K3}{z}

0x401c76 VCMPPS	$0xe,%XMM8,%XMM5,%K4

0x401c7d VANDPS	%XMM0,%XMM15,%XMM7

0x401c81 VXORPS	%XMM15,%XMM15,%XMM15

0x401c86 VMOVHLPS	%XMM9,%XMM15,%XMM8

0x401c8b VCVTPS2PD	%XMM9,%XMM0

0x401c90 VBROADCASTSS	0x1407(%RIP),%XMM9

0x401c99 VCVTPS2PD	%XMM8,%XMM8

0x401c9e VFMADD213PS	0x13fc(%RIP){1to4},%XMM5,%XMM9

0x401ca8 VSQRTPD	%XMM8,%XMM15

0x401cad VMULPD	%XMM15,%XMM8,%XMM8

0x401cb2 KMOVB	%K4,%ECX

0x401cb6 AND	$0xf,%ECX

0x401cb9 VFMADD213PS	0x13e5(%RIP){1to4},%XMM5,%XMM9

0x401cc3 KMOVB	%ECX,%K5

0x401cc7 MOV	%R11D,%EBX

0x401cca AND	$-0x4,%EBX

0x401ccd ADD	%EBX,%EAX

0x401ccf VFMADD213PS	0x13d3(%RIP){1to4},%XMM5,%XMM9

0x401cd9 AND	$0x3,%R11D

0x401cdd VFMADD213PS	0x13c9(%RIP){1to4},%XMM5,%XMM9

0x401ce7 VFMADD213PS	0x13c3(%RIP){1to4},%XMM9,%XMM5

0x401cf1 VSQRTPD	%XMM0,%XMM9

0x401cf5 VMULPD	%XMM9,%XMM0,%XMM0

0x401cfa VMOVDDUP	0x13b6(%RIP),%XMM9

0x401d02 VDIVPD	%XMM8,%XMM9,%XMM15

0x401d07 VCVTPS2PD	%XMM5,%XMM26

0x401d0d VDIVPD	%XMM0,%XMM9,%XMM0

0x401d11 VXORPS	%XMM9,%XMM9,%XMM9

0x401d16 VMOVHLPS	%XMM5,%XMM9,%XMM5

0x401d1a VCVTPS2PD	%XMM5,%XMM8

0x401d1e VADDPD	%XMM8,%XMM15,%XMM15

0x401d23 VADDPD	%XMM26,%XMM0,%XMM0

0x401d29 VINSERTF64X2	$0x1,%XMM15,%YMM0,%YMM0

0x401d30 VCVTPD2PS	%YMM0,%XMM9

0x401d34 VMULPS	%XMM7,%XMM9,%XMM7

0x401d38 VFMADD231PS	%XMM7,%XMM14,%XMM6{%K5}

0x401d3e VFMADD231PS	%XMM7,%XMM13,%XMM11{%K5}

0x401d44 VFMADD231PS	%XMM7,%XMM12,%XMM10{%K5}

0x401d4a VMOVHLPS	%XMM6,%XMM6,%XMM9

0x401d4e VMOVHLPS	%XMM11,%XMM11,%XMM5

0x401d53 VMOVHLPS	%XMM10,%XMM10,%XMM14

0x401d58 VADDPS	%XMM10,%XMM14,%XMM13

0x401d5d VADDPS	%XMM11,%XMM5,%XMM8

0x401d62 VADDPS	%XMM6,%XMM9,%XMM6

0x401d66 VSHUFPS	$0x55,%XMM13,%XMM13,%XMM12

0x401d6c VSHUFPS	$0x55,%XMM8,%XMM8,%XMM15

0x401d72 VSHUFPS	$0x55,%XMM6,%XMM6,%XMM7

0x401d77 VADDPS	%XMM13,%XMM12,%XMM0

0x401d7c VADDPS	%XMM8,%XMM15,%XMM5

0x401d81 VADDPS	%XMM6,%XMM7,%XMM7

0x401d85 JE	401ff8

0x401d8b MOVSXD	%EAX,%RCX

0x401d8e VMOVSS	(%RSI,%RCX,4),%XMM10

0x401d93 VMOVSS	(%RDI,%RCX,4),%XMM11

0x401d98 VSUBSS	%XMM1,%XMM10,%XMM15

0x401d9c VSUBSS	%XMM27,%XMM11,%XMM14

0x401da2 VMOVSS	(%RDX,%RCX,4),%XMM13

0x401da7 VMULSS	%XMM15,%XMM15,%XMM6

0x401dac VSUBSS	%XMM2,%XMM13,%XMM9

0x401db0 LEA	(,%RCX,4),%R11

0x401db8 VXORPS	%XMM11,%XMM11,%XMM11

0x401dbd VFMADD231SS	%XMM14,%XMM14,%XMM6

0x401dc2 VFMADD231SS	%XMM9,%XMM9,%XMM6

0x401dc7 VCOMISS	%XMM6,%XMM3

0x401dcb JBE	401dd3

0x401dcd VMOVSS	(%R8,%RCX,4),%XMM11

0x401dd3 VXORPS	%XMM12,%XMM12,%XMM12

0x401dd8 VCOMISS	%XMM12,%XMM6

0x401ddd JBE	401e55

0x401ddf VMOVSS	0x12b9(%RIP),%XMM13

0x401de7 VADDSS	%XMM4,%XMM6,%XMM8

0x401deb VFMADD213SS	0x12b0(%RIP),%XMM6,%XMM13

0x401df4 VCVTSS2SD	%XMM8,%XMM8,%XMM10

0x401df9 VSQRTSD	%XMM10,%XMM10,%XMM12

0x401dfe VMOVSD	0x12b2(%RIP),%XMM8

0x401e06 VFMADD213SS	0x1299(%RIP),%XMM6,%XMM13

0x401e0f VMULSD	%XMM12,%XMM10,%XMM10

0x401e14 VFMADD213SS	0x128f(%RIP),%XMM6,%XMM13

0x401e1d VFMADD213SS	0x128a(%RIP),%XMM6,%XMM13

0x401e26 VFMADD213SS	0x1285(%RIP),%XMM13,%XMM6

0x401e2f VDIVSD	%XMM10,%XMM8,%XMM13

0x401e34 VCVTSS2SD	%XMM6,%XMM6,%XMM6

0x401e38 VADDSD	%XMM6,%XMM13,%XMM12

0x401e3c VCVTSD2SS	%XMM12,%XMM12,%XMM10

0x401e41 VMULSS	%XMM11,%XMM10,%XMM11

0x401e46 VFMADD231SS	%XMM11,%XMM14,%XMM7

0x401e4b VFMADD231SS	%XMM11,%XMM15,%XMM5

0x401e50 VFMADD231SS	%XMM11,%XMM9,%XMM0

0x401e55 LEA	0x1(%RAX),%EBX

0x401e58 CMP	%R10D,%EBX

0x401e5b JGE	401ff8

0x401e61 VMOVSS	0x4(%RSI,%R11,1),%XMM9

0x401e68 VMOVSS	0x4(%RDI,%R11,1),%XMM14

0x401e6f VSUBSS	%XMM1,%XMM9,%XMM10

0x401e73 VSUBSS	%XMM27,%XMM14,%XMM15

0x401e79 VMOVSS	0x4(%RDX,%R11,1),%XMM8

0x401e80 VMULSS	%XMM10,%XMM10,%XMM6

0x401e85 VSUBSS	%XMM2,%XMM8,%XMM11

0x401e89 VXORPS	%XMM13,%XMM13,%XMM13

0x401e8e VFMADD231SS	%XMM15,%XMM15,%XMM6

0x401e93 VFMADD231SS	%XMM11,%XMM11,%XMM6

0x401e98 VCOMISS	%XMM6,%XMM3

0x401e9c JBE	401ea5

0x401e9e VMOVSS	0x4(%R8,%R11,1),%XMM13

0x401ea5 VXORPS	%XMM12,%XMM12,%XMM12

0x401eaa VCOMISS	%XMM12,%XMM6

0x401eaf JBE	401f27

0x401eb1 VMOVSS	0x11e7(%RIP),%XMM8

0x401eb9 VADDSS	%XMM6,%XMM4,%XMM14

0x401ebd VFMADD213SS	0x11de(%RIP),%XMM6,%XMM8

0x401ec6 VCVTSS2SD	%XMM14,%XMM14,%XMM9

0x401ecb VSQRTSD	%XMM9,%XMM9,%XMM12

0x401ed0 VFMADD213SS	0x11cf(%RIP),%XMM6,%XMM8

0x401ed9 VMULSD	%XMM12,%XMM9,%XMM14

0x401ede VMOVSD	0x11d2(%RIP),%XMM9

0x401ee6 VFMADD213SS	0x11bd(%RIP),%XMM6,%XMM8

0x401eef VFMADD213SS	0x11b8(%RIP),%XMM6,%XMM8

0x401ef8 VFMADD213SS	0x11b3(%RIP),%XMM8,%XMM6

0x401f01 VDIVSD	%XMM14,%XMM9,%XMM8

0x401f06 VCVTSS2SD	%XMM6,%XMM6,%XMM6

0x401f0a VADDSD	%XMM6,%XMM8,%XMM12

0x401f0e VCVTSD2SS	%XMM12,%XMM12,%XMM14

0x401f13 VMULSS	%XMM13,%XMM14,%XMM13

0x401f18 VFMADD231SS	%XMM15,%XMM13,%XMM7

0x401f1d VFMADD231SS	%XMM10,%XMM13,%XMM5

0x401f22 VFMADD231SS	%XMM11,%XMM13,%XMM0

0x401f27 ADD	$0x2,%EAX

0x401f2a CMP	%EAX,%R10D

0x401f2d JLE	401ff8

0x401f33 VMOVSS	0x8(%RSI,%R11,1),%XMM11

0x401f3a VMOVSS	0x8(%RDI,%R11,1),%XMM15

0x401f41 VSUBSS	%XMM1,%XMM11,%XMM8

0x401f45 VSUBSS	%XMM27,%XMM15,%XMM10

0x401f4b VMOVSS	0x8(%RDX,%R11,1),%XMM1

0x401f52 VMULSS	%XMM8,%XMM8,%XMM6

0x401f57 VSUBSS	%XMM2,%XMM1,%XMM9

0x401f5b VFMADD231SS	%XMM10,%XMM10,%XMM6

0x401f60 VFMADD231SS	%XMM9,%XMM9,%XMM6

0x401f65 VCOMISS	%XMM6,%XMM3

0x401f69 JA	402020

0x401f6f VXORPS	%XMM3,%XMM3,%XMM3

0x401f73 VXORPS	%XMM2,%XMM2,%XMM2

0x401f77 VCOMISS	%XMM2,%XMM6

0x401f7b JBE	401ff8

0x401f7d VADDSS	%XMM6,%XMM4,%XMM4

0x401f81 VMOVSD	0x112f(%RIP),%XMM11

0x401f89 VMOVSS	0x110f(%RIP),%XMM14

0x401f91 VCVTSS2SD	%XMM4,%XMM4,%XMM12

0x401f95 VSQRTSD	%XMM12,%XMM12,%XMM13

0x401f9a VFMADD213SS	0x1101(%RIP),%XMM6,%XMM14

0x401fa3 VMULSD	%XMM13,%XMM12,%XMM15

0x401fa8 VFMADD213SS	0x10f7(%RIP),%XMM6,%XMM14

0x401fb1 VDIVSD	%XMM15,%XMM11,%XMM2

0x401fb6 VFMADD213SS	0x10ed(%RIP),%XMM6,%XMM14

0x401fbf VFMADD213SS	0x10e8(%RIP),%XMM6,%XMM14

0x401fc8 VFMADD213SS	0x10e3(%RIP),%XMM14,%XMM6

0x401fd1 VCVTSS2SD	%XMM6,%XMM6,%XMM1

0x401fd5 VADDSD	%XMM1,%XMM2,%XMM6

0x401fd9 VCVTSD2SS	%XMM6,%XMM6,%XMM4

0x401fdd VMULSS	%XMM3,%XMM4,%XMM3

0x401fe1 VFMADD231SS	%XMM3,%XMM10,%XMM7

0x401fe6 VFMADD231SS	%XMM3,%XMM8,%XMM5

0x401feb VFMADD231SS	%XMM3,%XMM9,%XMM0

0x401ff0 VZEROUPPER

0x401ff3 JMP	401ffb

0x401ff5 NOPL	(%RAX)

0x401ff8 VZEROUPPER

0x401ffb VMOVSS	%XMM7,(%R9)

0x402000 MOV	0x10(%RBP),%R8

0x402004 MOV	0x18(%RBP),%R9

0x402008 VMOVSS	%XMM5,(%R8)

0x40200d VMOVSS	%XMM0,(%R9)

0x402012 MOV	-0x8(%RBP),%RBX

0x402016 LEAVE

0x402017 RET

0x402018 NOPL	(%RAX,%RAX,1)

0x402020 VMOVSS	0x8(%R8,%R11,1),%XMM3

0x402027 JMP	401f73

0x40202c NOPL	(%RAX)

0x402030 VXORPS	%XMM0,%XMM0,%XMM0

0x402034 VMOVAPS	%XMM0,%XMM5

0x402038 VMOVAPS	%XMM0,%XMM7

0x40203c JMP	401ffb

0x40203e VXORPS	%XMM10,%XMM10,%XMM10

0x402043 VXORPS	%XMM0,%XMM0,%XMM0

0x402047 VMOVAPS	%XMM10,%XMM11

0x40204c VMOVAPS	%XMM10,%XMM6

0x402050 XOR	%ECX,%ECX

0x402052 XOR	%EAX,%EAX

0x402054 VMOVAPS	%XMM0,%XMM5

0x402058 VMOVAPS	%XMM0,%XMM7

0x40205c JMP	401bf5

Coverage (%)	Name	Source Location	Module
►38.46+	main._omp_fn.1	main.c:144	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►38.08+	main._omp_fn.1	main.c:144	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►17.51+	main._omp_fn.1	main.c:144	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►5.53+	main._omp_fn.1	main.c:144	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_3

Source file and lines	Step10_orig.c:10-41
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:10,17-41.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is poorly vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions).

Details

43% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

17% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
58% of SSE/AVX addition or subtraction instructions are used in vector version.
30% of SSE/AVX multiply instructions are used in vector version.
25% of SSE/AVX fused multiply-add instructions are used in vector version.
40% of SSE/AVX divide and square root instructions are used in vector version.
55% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 59.00 to 51.00 cycles (1.16x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 70 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEAVE: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:41
VCVTPD2PS: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTPS2PD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTSD2SS: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTSS2SD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VZEROUPPER: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:35
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:35

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPD2PS (FP64 to FP32, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTSD2SS (FP64 to FP32, scalar): 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTSS2SD (FP32 to FP64, scalar): 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

54 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 34 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 270 FP arithmetical operations:

165: addition or subtraction (70 inside FMA instructions)
91: multiply (70 inside FMA instructions)
7: divide
7: square root

The binary function is loading 296 bytes (74 single precision FP elements). The binary function is storing 12 bytes (3 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.88 FP operations per loaded or stored byte.

General properties

nb instructions	279
nb uops	297
loop length	1447
used x86 registers	12
used mmx registers	0
used xmm registers	19
used ymm registers	17
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	2.77

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	49.50 cycles
front end	49.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	59.00	59.00	18.67	18.67	2.50	51.00	18.40	2.50	2.50	2.50	18.60	18.67
cycles	59.00	59.00	18.67	18.67	2.50	51.00	18.40	2.50	2.50	2.50	18.60	18.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

42.50

Cycles summary

Front-end	49.50
Dispatch	59.00
DIV/SQRT	42.50
Overall L1	59.00

Vectorization ratios

INT

all	14%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	45%
load	17%
store	0%
mul	30%
add-sub	58%
fma	25%
div/sqrt	40%
other	61%

INT+FP

all	43%
load	17%
store	0%
mul	30%
add-sub	58%
fma	25%
div/sqrt	40%
other	55%

Vector efficiency ratios

INT

all	9%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	15%
load	10%
store	6%
mul	13%
add-sub	17%
fma	10%
div/sqrt	17%
other	17%

INT+FP

all	14%
load	10%
store	6%
mul	13%
add-sub	17%
fma	10%
div/sqrt	17%
other	16%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 59.00 cycles. At this rate:

2% of peak load performance is reached (5.02 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4019c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %EDI,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
TEST %EDI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 402030 <Step10_orig+0x670>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%R10),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %XMM0,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 40203e <Step10_orig+0x67e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VXORPS %XMM12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SHR $0x3,%EBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
VBROADCASTSS 0x169f(%RIP),%YMM22	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VBROADCASTSS 0x1699(%RIP),%YMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VBROADCASTSS 0x1693(%RIP),%YMM20	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VBROADCASTSS 0x168d(%RIP),%YMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VBROADCASTSS 0x1687(%RIP),%YMM18	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VBROADCASTSS 0x1681(%RIP),%YMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VBROADCASTSD 0x167c(%RIP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSS %XMM0,%YMM26	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%YMM25	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM2,%YMM24	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM3,%YMM15	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM4,%YMM23	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
SAL $0x5,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPS %YMM12,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPS %YMM12,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPS %YMM12,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPS %XMM1,%XMM31	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTF32X4 $0x1,%YMM11,%XMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPS %XMM11,%XMM8,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VEXTRACTF32X4 $0x1,%YMM12,%XMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPS %XMM12,%XMM13,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVHLPS %XMM11,%XMM11,%XMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VADDPS %XMM11,%XMM7,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VEXTRACTF32X4 $0x1,%YMM10,%XMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVHLPS %XMM15,%XMM15,%XMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VSHUFPS $0x55,%XMM6,%XMM6,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDPS %XMM6,%XMM5,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPS %XMM10,%XMM13,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPS %XMM15,%XMM12,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVHLPS %XMM6,%XMM6,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VADDPS %XMM6,%XMM10,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
AND $-0x8,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VSHUFPS $0x55,%XMM14,%XMM14,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMOVAPS %XMM31,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VADDPS %XMM14,%XMM9,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VSHUFPS $0x55,%XMM12,%XMM12,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMOVAPS %XMM15,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VADDPS %XMM12,%XMM14,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
CMP %EAX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 401ff8 <Step10_orig+0x638>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ECX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%R11),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x2,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 401d8b <Step10_orig+0x3cb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPS (%RSI,%RCX,4),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VBROADCASTSS %XMM1,%XMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VSUBPS %XMM5,%XMM7,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPS (%RDI,%RCX,4),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VBROADCASTSS %XMM27,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VMULPS %XMM13,%XMM13,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSUBPS %XMM0,%XMM8,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPS (%RDX,%RCX,4),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VBROADCASTSS %XMM2,%XMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VSUBPS %XMM8,%XMM12,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PS %XMM14,%XMM14,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VBROADCASTSS %XMM3,%XMM15	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM4,%XMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD231PS %XMM12,%XMM12,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VCMPPS $0x1,%XMM15,%XMM5,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VCMPPS $0x1,%XMM15,%XMM5,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VADDPS %XMM9,%XMM5,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
KMOVB %K0,%EBX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
AND $0xf,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
KMOVB %EBX,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	N/A
VMOVUPS (%R8,%RCX,4),%XMM0{%K3}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VCMPPS $0xe,%XMM8,%XMM5,%K4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VANDPS %XMM0,%XMM15,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VXORPS %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVHLPS %XMM9,%XMM15,%XMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VCVTPS2PD %XMM9,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	vect (12.5%)
VBROADCASTSS 0x1407(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VCVTPS2PD %XMM8,%XMM8	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	vect (12.5%)
VFMADD213PS 0x13fc(%RIP){1to4},%XMM5,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VSQRTPD %XMM8,%XMM15	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	vect (25.0%)
VMULPD %XMM15,%XMM8,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
KMOVB %K4,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
AND $0xf,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VFMADD213PS 0x13e5(%RIP){1to4},%XMM5,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
KMOVB %ECX,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	N/A
MOV %R11D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $-0x4,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
ADD %EBX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VFMADD213PS 0x13d3(%RIP){1to4},%XMM5,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
AND $0x3,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VFMADD213PS 0x13c9(%RIP){1to4},%XMM5,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD213PS 0x13c3(%RIP){1to4},%XMM9,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VSQRTPD %XMM0,%XMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	vect (25.0%)
VMULPD %XMM9,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVDDUP 0x13b6(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VDIVPD %XMM8,%XMM9,%XMM15	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
VCVTPS2PD %XMM5,%XMM26	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	vect (12.5%)
VDIVPD %XMM0,%XMM9,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
VXORPS %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVHLPS %XMM5,%XMM9,%XMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VCVTPS2PD %XMM5,%XMM8	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	vect (12.5%)
VADDPD %XMM8,%XMM15,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM26,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTF64X2 $0x1,%XMM15,%YMM0,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VCVTPD2PS %YMM0,%XMM9	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VMULPS %XMM7,%XMM9,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PS %XMM7,%XMM14,%XMM6{%K5}	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PS %XMM7,%XMM13,%XMM11{%K5}	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PS %XMM7,%XMM12,%XMM10{%K5}	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVHLPS %XMM6,%XMM6,%XMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VMOVHLPS %XMM11,%XMM11,%XMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VMOVHLPS %XMM10,%XMM10,%XMM14	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VADDPS %XMM10,%XMM14,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPS %XMM11,%XMM5,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPS %XMM6,%XMM9,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM13,%XMM13,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM8,%XMM8,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM6,%XMM6,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDPS %XMM13,%XMM12,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPS %XMM8,%XMM15,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPS %XMM6,%XMM7,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
JE 401ff8 <Step10_orig+0x638>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
VMOVSS (%RSI,%RCX,4),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS (%RDI,%RCX,4),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VSUBSS %XMM1,%XMM10,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VSUBSS %XMM27,%XMM11,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSS (%RDX,%RCX,4),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMULSS %XMM15,%XMM15,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VSUBSS %XMM2,%XMM13,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
LEA (,%RCX,4),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPS %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD231SS %XMM14,%XMM14,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM9,%XMM9,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VCOMISS %XMM6,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JBE 401dd3 <Step10_orig+0x413>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS (%R8,%RCX,4),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VXORPS %XMM12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCOMISS %XMM12,%XMM6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JBE 401e55 <Step10_orig+0x495>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS 0x12b9(%RIP),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VADDSS %XMM4,%XMM6,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VFMADD213SS 0x12b0(%RIP),%XMM6,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VCVTSS2SD %XMM8,%XMM8,%XMM10	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	4-5	1	scal (6.3%)
VSQRTSD %XMM10,%XMM10,%XMM12	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMOVSD 0x12b2(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SS 0x1299(%RIP),%XMM6,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VMULSD %XMM12,%XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SS 0x128f(%RIP),%XMM6,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x128a(%RIP),%XMM6,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x1285(%RIP),%XMM13,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VDIVSD %XMM10,%XMM8,%XMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VCVTSS2SD %XMM6,%XMM6,%XMM6	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	4-5	1	scal (6.3%)
VADDSD %XMM6,%XMM13,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCVTSD2SS %XMM12,%XMM12,%XMM10	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM11,%XMM10,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM11,%XMM14,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM11,%XMM15,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM11,%XMM9,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x1(%RAX),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R10D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 401ff8 <Step10_orig+0x638>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS 0x4(%RSI,%R11,1),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x4(%RDI,%R11,1),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VSUBSS %XMM1,%XMM9,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VSUBSS %XMM27,%XMM14,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSS 0x4(%RDX,%R11,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMULSS %XMM10,%XMM10,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VSUBSS %XMM2,%XMM8,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VXORPS %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD231SS %XMM15,%XMM15,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM11,%XMM11,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VCOMISS %XMM6,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JBE 401ea5 <Step10_orig+0x4e5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS 0x4(%R8,%R11,1),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VXORPS %XMM12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCOMISS %XMM12,%XMM6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JBE 401f27 <Step10_orig+0x567>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS 0x11e7(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VADDSS %XMM6,%XMM4,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VFMADD213SS 0x11de(%RIP),%XMM6,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VCVTSS2SD %XMM14,%XMM14,%XMM9	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	4-5	1	scal (6.3%)
VSQRTSD %XMM9,%XMM9,%XMM12	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VFMADD213SS 0x11cf(%RIP),%XMM6,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VMULSD %XMM12,%XMM9,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0x11d2(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SS 0x11bd(%RIP),%XMM6,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x11b8(%RIP),%XMM6,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x11b3(%RIP),%XMM8,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VDIVSD %XMM14,%XMM9,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VCVTSS2SD %XMM6,%XMM6,%XMM6	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	4-5	1	scal (6.3%)
VADDSD %XMM6,%XMM8,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCVTSD2SS %XMM12,%XMM12,%XMM14	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM13,%XMM14,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM15,%XMM13,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM10,%XMM13,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM11,%XMM13,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADD $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JLE 401ff8 <Step10_orig+0x638>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS 0x8(%RSI,%R11,1),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x8(%RDI,%R11,1),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VSUBSS %XMM1,%XMM11,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VSUBSS %XMM27,%XMM15,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSS 0x8(%RDX,%R11,1),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMULSS %XMM8,%XMM8,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VSUBSS %XMM2,%XMM1,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VFMADD231SS %XMM10,%XMM10,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM9,%XMM9,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VCOMISS %XMM6,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JA 402020 <Step10_orig+0x660>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCOMISS %XMM2,%XMM6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JBE 401ff8 <Step10_orig+0x638>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VADDSS %XMM6,%XMM4,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSD 0x112f(%RIP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSS 0x110f(%RIP),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM4,%XMM4,%XMM12	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	4-5	1	scal (6.3%)
VSQRTSD %XMM12,%XMM12,%XMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VFMADD213SS 0x1101(%RIP),%XMM6,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VMULSD %XMM13,%XMM12,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SS 0x10f7(%RIP),%XMM6,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VDIVSD %XMM15,%XMM11,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VFMADD213SS 0x10ed(%RIP),%XMM6,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x10e8(%RIP),%XMM6,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x10e3(%RIP),%XMM14,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VCVTSS2SD %XMM6,%XMM6,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	4-5	1	scal (6.3%)
VADDSD %XMM1,%XMM2,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCVTSD2SS %XMM6,%XMM6,%XMM4	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM3,%XMM4,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM3,%XMM10,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM3,%XMM8,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM3,%XMM9,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 401ffb <Step10_orig+0x63b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
VMOVSS %XMM7,(%R9)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x10(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM5,(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM0,(%R9)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEAVE	3	0.60	0.60	0.33	0.33	0	0.60	0.60	0	0	0	0.60	0.33	2-6	2	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSS 0x8(%R8,%R11,1),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JMP 401f73 <Step10_orig+0x5b3>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPS %XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 401ffb <Step10_orig+0x63b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VXORPS %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPS %XMM10,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPS %XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPS %XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 401bf5 <Step10_orig+0x235>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_3

Source file and lines	Step10_orig.c:10-41
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:10,17-41.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is poorly vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions).

Details

43% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

17% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
58% of SSE/AVX addition or subtraction instructions are used in vector version.
30% of SSE/AVX multiply instructions are used in vector version.
25% of SSE/AVX fused multiply-add instructions are used in vector version.
40% of SSE/AVX divide and square root instructions are used in vector version.
55% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 70 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEAVE: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:41
VCVTPD2PS: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTPS2PD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTSD2SS: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTSS2SD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VZEROUPPER: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:35
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:35

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPD2PS (FP64 to FP32, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTSD2SS (FP64 to FP32, scalar): 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTSS2SD (FP32 to FP64, scalar): 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 270 FP arithmetical operations:

165: addition or subtraction (70 inside FMA instructions)
91: multiply (70 inside FMA instructions)
7: divide
7: square root

The binary function is loading 296 bytes (74 single precision FP elements). The binary function is storing 12 bytes (3 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.88 FP operations per loaded or stored byte.

General properties

nb instructions	279
nb uops	297
loop length	1447
used x86 registers	12
used mmx registers	0
used xmm registers	19
used ymm registers	17
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	2.77

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	49.50 cycles
front end	49.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	59.00	59.00	18.67	18.67	2.50	51.00	18.40	2.50	2.50	2.50	18.60	18.67
cycles	59.00	59.00	18.67	18.67	2.50	51.00	18.40	2.50	2.50	2.50	18.60	18.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

42.50

Cycles summary

Front-end	49.50
Dispatch	59.00
DIV/SQRT	42.50
Overall L1	59.00

Vectorization ratios

INT

all	14%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	45%
load	17%
store	0%
mul	30%
add-sub	58%
fma	25%
div/sqrt	40%
other	61%

INT+FP

all	43%
load	17%
store	0%
mul	30%
add-sub	58%
fma	25%
div/sqrt	40%
other	55%

Vector efficiency ratios

INT

all	9%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	15%
load	10%
store	6%
mul	13%
add-sub	17%
fma	10%
div/sqrt	17%
other	17%

INT+FP

all	14%
load	10%
store	6%
mul	13%
add-sub	17%
fma	10%
div/sqrt	17%
other	16%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 59.00 cycles. At this rate:

2% of peak load performance is reached (5.02 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4019c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %EDI,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
TEST %EDI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 402030 <Step10_orig+0x670>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%R10),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %XMM0,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 40203e <Step10_orig+0x67e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VXORPS %XMM12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SHR $0x3,%EBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
VBROADCASTSS 0x169f(%RIP),%YMM22	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VBROADCASTSS 0x1699(%RIP),%YMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VBROADCASTSS 0x1693(%RIP),%YMM20	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VBROADCASTSS 0x168d(%RIP),%YMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VBROADCASTSS 0x1687(%RIP),%YMM18	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VBROADCASTSS 0x1681(%RIP),%YMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VBROADCASTSD 0x167c(%RIP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VBROADCASTSS %XMM0,%YMM26	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%YMM25	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM2,%YMM24	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM3,%YMM15	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM4,%YMM23	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
SAL $0x5,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPS %YMM12,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPS %YMM12,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPS %YMM12,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPS %XMM1,%XMM31	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTF32X4 $0x1,%YMM11,%XMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPS %XMM11,%XMM8,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VEXTRACTF32X4 $0x1,%YMM12,%XMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPS %XMM12,%XMM13,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVHLPS %XMM11,%XMM11,%XMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VADDPS %XMM11,%XMM7,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VEXTRACTF32X4 $0x1,%YMM10,%XMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVHLPS %XMM15,%XMM15,%XMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VSHUFPS $0x55,%XMM6,%XMM6,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDPS %XMM6,%XMM5,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPS %XMM10,%XMM13,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPS %XMM15,%XMM12,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVHLPS %XMM6,%XMM6,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VADDPS %XMM6,%XMM10,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
AND $-0x8,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VSHUFPS $0x55,%XMM14,%XMM14,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMOVAPS %XMM31,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VADDPS %XMM14,%XMM9,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VSHUFPS $0x55,%XMM12,%XMM12,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMOVAPS %XMM15,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VADDPS %XMM12,%XMM14,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
CMP %EAX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 401ff8 <Step10_orig+0x638>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ECX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%R11),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x2,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 401d8b <Step10_orig+0x3cb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPS (%RSI,%RCX,4),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VBROADCASTSS %XMM1,%XMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VSUBPS %XMM5,%XMM7,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPS (%RDI,%RCX,4),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VBROADCASTSS %XMM27,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VMULPS %XMM13,%XMM13,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSUBPS %XMM0,%XMM8,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPS (%RDX,%RCX,4),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VBROADCASTSS %XMM2,%XMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VSUBPS %XMM8,%XMM12,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PS %XMM14,%XMM14,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VBROADCASTSS %XMM3,%XMM15	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM4,%XMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD231PS %XMM12,%XMM12,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VCMPPS $0x1,%XMM15,%XMM5,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VCMPPS $0x1,%XMM15,%XMM5,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VADDPS %XMM9,%XMM5,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
KMOVB %K0,%EBX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
AND $0xf,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
KMOVB %EBX,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	N/A
VMOVUPS (%R8,%RCX,4),%XMM0{%K3}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VCMPPS $0xe,%XMM8,%XMM5,%K4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VANDPS %XMM0,%XMM15,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VXORPS %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVHLPS %XMM9,%XMM15,%XMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VCVTPS2PD %XMM9,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	vect (12.5%)
VBROADCASTSS 0x1407(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VCVTPS2PD %XMM8,%XMM8	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	vect (12.5%)
VFMADD213PS 0x13fc(%RIP){1to4},%XMM5,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VSQRTPD %XMM8,%XMM15	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	vect (25.0%)
VMULPD %XMM15,%XMM8,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
KMOVB %K4,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
AND $0xf,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VFMADD213PS 0x13e5(%RIP){1to4},%XMM5,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
KMOVB %ECX,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	N/A
MOV %R11D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $-0x4,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
ADD %EBX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VFMADD213PS 0x13d3(%RIP){1to4},%XMM5,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
AND $0x3,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VFMADD213PS 0x13c9(%RIP){1to4},%XMM5,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD213PS 0x13c3(%RIP){1to4},%XMM9,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VSQRTPD %XMM0,%XMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	vect (25.0%)
VMULPD %XMM9,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVDDUP 0x13b6(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VDIVPD %XMM8,%XMM9,%XMM15	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
VCVTPS2PD %XMM5,%XMM26	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	vect (12.5%)
VDIVPD %XMM0,%XMM9,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
VXORPS %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVHLPS %XMM5,%XMM9,%XMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VCVTPS2PD %XMM5,%XMM8	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	vect (12.5%)
VADDPD %XMM8,%XMM15,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM26,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTF64X2 $0x1,%XMM15,%YMM0,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VCVTPD2PS %YMM0,%XMM9	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VMULPS %XMM7,%XMM9,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PS %XMM7,%XMM14,%XMM6{%K5}	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PS %XMM7,%XMM13,%XMM11{%K5}	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PS %XMM7,%XMM12,%XMM10{%K5}	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVHLPS %XMM6,%XMM6,%XMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VMOVHLPS %XMM11,%XMM11,%XMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VMOVHLPS %XMM10,%XMM10,%XMM14	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VADDPS %XMM10,%XMM14,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPS %XMM11,%XMM5,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPS %XMM6,%XMM9,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM13,%XMM13,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM8,%XMM8,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM6,%XMM6,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDPS %XMM13,%XMM12,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPS %XMM8,%XMM15,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPS %XMM6,%XMM7,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
JE 401ff8 <Step10_orig+0x638>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
VMOVSS (%RSI,%RCX,4),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS (%RDI,%RCX,4),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VSUBSS %XMM1,%XMM10,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VSUBSS %XMM27,%XMM11,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSS (%RDX,%RCX,4),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMULSS %XMM15,%XMM15,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VSUBSS %XMM2,%XMM13,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
LEA (,%RCX,4),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPS %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD231SS %XMM14,%XMM14,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM9,%XMM9,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VCOMISS %XMM6,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JBE 401dd3 <Step10_orig+0x413>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS (%R8,%RCX,4),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VXORPS %XMM12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCOMISS %XMM12,%XMM6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JBE 401e55 <Step10_orig+0x495>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS 0x12b9(%RIP),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VADDSS %XMM4,%XMM6,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VFMADD213SS 0x12b0(%RIP),%XMM6,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VCVTSS2SD %XMM8,%XMM8,%XMM10	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	4-5	1	scal (6.3%)
VSQRTSD %XMM10,%XMM10,%XMM12	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMOVSD 0x12b2(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SS 0x1299(%RIP),%XMM6,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VMULSD %XMM12,%XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SS 0x128f(%RIP),%XMM6,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x128a(%RIP),%XMM6,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x1285(%RIP),%XMM13,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VDIVSD %XMM10,%XMM8,%XMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VCVTSS2SD %XMM6,%XMM6,%XMM6	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	4-5	1	scal (6.3%)
VADDSD %XMM6,%XMM13,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCVTSD2SS %XMM12,%XMM12,%XMM10	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM11,%XMM10,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM11,%XMM14,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM11,%XMM15,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM11,%XMM9,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x1(%RAX),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R10D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 401ff8 <Step10_orig+0x638>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS 0x4(%RSI,%R11,1),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x4(%RDI,%R11,1),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VSUBSS %XMM1,%XMM9,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VSUBSS %XMM27,%XMM14,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSS 0x4(%RDX,%R11,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMULSS %XMM10,%XMM10,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VSUBSS %XMM2,%XMM8,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VXORPS %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD231SS %XMM15,%XMM15,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM11,%XMM11,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VCOMISS %XMM6,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JBE 401ea5 <Step10_orig+0x4e5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS 0x4(%R8,%R11,1),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VXORPS %XMM12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCOMISS %XMM12,%XMM6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JBE 401f27 <Step10_orig+0x567>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS 0x11e7(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VADDSS %XMM6,%XMM4,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VFMADD213SS 0x11de(%RIP),%XMM6,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VCVTSS2SD %XMM14,%XMM14,%XMM9	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	4-5	1	scal (6.3%)
VSQRTSD %XMM9,%XMM9,%XMM12	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VFMADD213SS 0x11cf(%RIP),%XMM6,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VMULSD %XMM12,%XMM9,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0x11d2(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SS 0x11bd(%RIP),%XMM6,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x11b8(%RIP),%XMM6,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x11b3(%RIP),%XMM8,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VDIVSD %XMM14,%XMM9,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VCVTSS2SD %XMM6,%XMM6,%XMM6	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	4-5	1	scal (6.3%)
VADDSD %XMM6,%XMM8,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCVTSD2SS %XMM12,%XMM12,%XMM14	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM13,%XMM14,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM15,%XMM13,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM10,%XMM13,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM11,%XMM13,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADD $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JLE 401ff8 <Step10_orig+0x638>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS 0x8(%RSI,%R11,1),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x8(%RDI,%R11,1),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VSUBSS %XMM1,%XMM11,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VSUBSS %XMM27,%XMM15,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSS 0x8(%RDX,%R11,1),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMULSS %XMM8,%XMM8,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VSUBSS %XMM2,%XMM1,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VFMADD231SS %XMM10,%XMM10,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM9,%XMM9,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VCOMISS %XMM6,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JA 402020 <Step10_orig+0x660>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCOMISS %XMM2,%XMM6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JBE 401ff8 <Step10_orig+0x638>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VADDSS %XMM6,%XMM4,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSD 0x112f(%RIP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSS 0x110f(%RIP),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM4,%XMM4,%XMM12	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	4-5	1	scal (6.3%)
VSQRTSD %XMM12,%XMM12,%XMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VFMADD213SS 0x1101(%RIP),%XMM6,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VMULSD %XMM13,%XMM12,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SS 0x10f7(%RIP),%XMM6,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VDIVSD %XMM15,%XMM11,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VFMADD213SS 0x10ed(%RIP),%XMM6,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x10e8(%RIP),%XMM6,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VFMADD213SS 0x10e3(%RIP),%XMM14,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VCVTSS2SD %XMM6,%XMM6,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	4-5	1	scal (6.3%)
VADDSD %XMM1,%XMM2,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCVTSD2SS %XMM6,%XMM6,%XMM4	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM3,%XMM4,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM3,%XMM10,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM3,%XMM8,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMADD231SS %XMM3,%XMM9,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 401ffb <Step10_orig+0x63b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
VMOVSS %XMM7,(%R9)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x10(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM5,(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM0,(%R9)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEAVE	3	0.60	0.60	0.33	0.33	0	0.60	0.60	0	0	0	0.60	0.33	2-6	2	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSS 0x8(%R8,%R11,1),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JMP 401f73 <Step10_orig+0x5b3>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPS %XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 401ffb <Step10_orig+0x63b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VXORPS %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPS %XMM10,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPS %XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPS %XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 401bf5 <Step10_orig+0x235>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Name	Coverage (%)	Time (s)
▼Step10_orig–	67.22	5.16
○Loop 3 - Step10_orig.c:19-31 - exec	67.21	5.15

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code