OV - exec - Function main

	Function: main	Module: exec	Source: main.c:50-192 [...]	Coverage (incl. loops): 0.07% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c: 50 - 192

--------------------------------------------------------------------------------

50: {

[...]

57:   double t3, elapsed = 0.0, validation, final, t1, t2;

[...]

63:   long NN = N;

[...]

73:       printf( "count is set %d\n", count );

74:       printf( "Total MPI ranks %d\n", nprocs );

75:   }

76:

77:   if (argc == 2 && strncmp(argv[1], "-s", 2) == 0)

78:       NN = 15000;

79:

80:   printf( "N is set %ld\n", NN );

81:

82: #pragma omp parallel

[...]

97:   for ( n = 400; n < NN; n = n + 20 )

[...]

103:       dx1 = 1.0f/(float)n;

104:       dy1 = 2.0f/(float)n;

105:       dz1 = 3.0f/(float)n;

106:       xx[0] = 0.f;

107:       yy[0] = 0.f;

108:       zz[0] = 0.f;

109:       mass[0] = 2.f;

110:

111:       for ( i = 1; i < n; i++ )

112:       {

113:           xx[i] = xx[i-1] + dx1;

114:           yy[i] = yy[i-1] + dy1;

115:           zz[i] = zz[i-1] + dz1;

116:           mass[i] = (float)i * 0.01f + xx[i];

117:       }

118:

119:       for ( i = 0; i < n; i++ )

120:       {

121:           vx1[i] = 0.f;

122:           vy1[i] = 0.f;

123:           vz1[i] = 0.f;

[...]

136:       t1 = mysecond();

137: #endif

138:

139:     #pragma omp parallel for private( dx1, dy1, dz1 )

[...]

152:       t2 = mysecond();

[...]

166:       t3 = (t2 - t1) * 1e6;

167: #endif

168:

169:       elapsed = elapsed + t3;

[...]

185:       printf( "\nKernel elapsed time, s: %18.8lf\n", elapsed*1e-6 );

[...]

192: }

0x4010a0 PUSH	%RBP

0x4010a1 XOR	%EAX,%EAX

0x4010a3 MOV	%RSP,%RBP

0x4010a6 PUSH	%R15

0x4010a8 PUSH	%R14

0x4010aa PUSH	%R13

0x4010ac MOV	%RSI,%R13

0x4010af MOV	$0xbb8,%ESI

0x4010b4 PUSH	%R12

0x4010b6 MOV	$0x186a0,%R12D

0x4010bc PUSH	%RBX

0x4010bd MOV	%EDI,%EBX

0x4010bf MOV	$0x40301f,%EDI

0x4010c4 SUB	$0x38,%RSP

0x4010c8 CALL	401030 <printf@plt>

0x4010cd MOV	$0x1,%ESI

0x4010d2 MOV	$0x403030,%EDI

0x4010d7 XOR	%EAX,%EAX

0x4010d9 CALL	401030 <printf@plt>

0x4010de CMP	$0x2,%EBX

0x4010e1 JE	401447

0x4010e7 MOV	%R12,%RSI

0x4010ea MOV	$0x403047,%EDI

0x4010ef XOR	%EAX,%EAX

0x4010f1 CALL	401030 <printf@plt>

0x4010f6 XOR	%ECX,%ECX

0x4010f8 XOR	%EDX,%EDX

0x4010fa LEA	-0x50(%RBP),%RSI

0x4010fe MOV	$0x401920,%EDI

0x401103 MOVL	$0,-0x50(%RBP)

0x40110a CALL	401090 <GOMP_parallel@plt>

0x40110f VMOVSS	0x1f6d(%RIP),%XMM8

0x401117 MOV	0x1f6a(%RIP),%R14

0x40111e MOV	$0x190,%EAX

0x401123 VXORPD	%XMM9,%XMM9,%XMM9

0x401128 VXORPS	%XMM7,%XMM7,%XMM7

0x40112c NOPL	(%RAX)

(1) 0x401130 VCVTSI2SS	%EAX,%XMM7,%XMM3

(1) 0x401134 VMOVSS	0x1f40(%RIP),%XMM5

(1) 0x40113c VXORPS	%XMM0,%XMM0,%XMM0

(1) 0x401140 LEA	-0x1(%RAX),%RDX

(1) 0x401144 VDIVSS	%XMM3,%XMM5,%XMM10

(1) 0x401148 MOVL	$0,0x18a92e(%RIP)

(1) 0x401152 MOVL	$0,0x1ec3a4(%RIP)

(1) 0x40115c MOVL	$0,0x24de1a(%RIP)

(1) 0x401166 MOVL	$0x40000000,0x128e90(%RIP)

(1) 0x401170 MOV	%EAX,%EBX

(1) 0x401172 MOV	$0x1,%R13D

(1) 0x401178 VMOVAPS	%XMM0,%XMM2

(1) 0x40117c VMOVAPS	%XMM0,%XMM1

(1) 0x401180 VMULSS	0x1ef8(%RIP),%XMM10,%XMM11

(1) 0x401188 VADDSS	%XMM10,%XMM10,%XMM6

(1) 0x40118d AND	$0x3,%EDX

(1) 0x401190 JE	401271

(1) 0x401196 CMP	$0x1,%RDX

(1) 0x40119a JE	401225

(1) 0x4011a0 CMP	$0x2,%RDX

(1) 0x4011a4 JE	4011e2

(1) 0x4011a6 VCVTSI2SS	%R13D,%XMM7,%XMM4

(1) 0x4011ab VMOVAPS	%XMM10,%XMM0

(1) 0x4011af VMOVSS	%XMM10,0x18a8cd(%RIP)

(1) 0x4011b7 VMOVAPS	%XMM6,%XMM2

(1) 0x4011bb VFMADD132SS	%XMM8,%XMM10,%XMM4

(1) 0x4011c0 VMOVSS	%XMM6,0x1ec33c(%RIP)

(1) 0x4011c8 VMOVAPS	%XMM11,%XMM1

(1) 0x4011cc VMOVSS	%XMM11,0x24ddb0(%RIP)

(1) 0x4011d4 MOV	$0x2,%R13D

(1) 0x4011da VMOVSS	%XMM4,0x128e22(%RIP)

(1) 0x4011e2 VCVTSI2SS	%R13D,%XMM7,%XMM12

(1) 0x4011e7 VADDSS	%XMM10,%XMM0,%XMM0

(1) 0x4011ec VADDSS	%XMM6,%XMM2,%XMM2

(1) 0x4011f0 VADDSS	%XMM11,%XMM1,%XMM1

(1) 0x4011f5 VFMADD132SS	%XMM8,%XMM0,%XMM12

(1) 0x4011fa VMOVSS	%XMM0,0x58ba80(,%R13,4)

(1) 0x401204 VMOVSS	%XMM2,0x5ed500(,%R13,4)

(1) 0x40120e VMOVSS	%XMM1,0x64ef80(,%R13,4)

(1) 0x401218 VMOVSS	%XMM12,0x52a000(,%R13,4)

(1) 0x401222 INC	%R13

(1) 0x401225 VCVTSI2SS	%R13D,%XMM7,%XMM13

(1) 0x40122a VADDSS	%XMM10,%XMM0,%XMM0

(1) 0x40122f VADDSS	%XMM6,%XMM2,%XMM2

(1) 0x401233 VADDSS	%XMM11,%XMM1,%XMM1

(1) 0x401238 VFMADD132SS	%XMM8,%XMM0,%XMM13

(1) 0x40123d VMOVSS	%XMM0,0x58ba80(,%R13,4)

(1) 0x401247 VMOVSS	%XMM2,0x5ed500(,%R13,4)

(1) 0x401251 VMOVSS	%XMM1,0x64ef80(,%R13,4)

(1) 0x40125b VMOVSS	%XMM13,0x52a000(,%R13,4)

(1) 0x401265 INC	%R13

(1) 0x401268 CMP	%RAX,%R13

(1) 0x40126b JE	40137b

  (0) 0x401271 VADDSS	%XMM10,%XMM0,%XMM14

  (0) 0x401276 VADDSS	%XMM6,%XMM2,%XMM15

  (0) 0x40127a LEA	0x2(%R13),%RSI

  (0) 0x40127e VADDSS	%XMM10,%XMM14,%XMM12

  (0) 0x401283 VMOVSS	%XMM15,0x5ed500(,%R13,4)

  (0) 0x40128d VADDSS	%XMM6,%XMM15,%XMM2

  (0) 0x401291 VADDSS	%XMM11,%XMM1,%XMM3

  (0) 0x401296 VCVTSI2SS	%ESI,%XMM7,%XMM15

  (0) 0x40129a VADDSS	%XMM10,%XMM12,%XMM0

  (0) 0x40129f LEA	0x1(%R13),%RCX

  (0) 0x4012a3 LEA	0x3(%R13),%RDI

  (0) 0x4012a7 VCVTSI2SS	%R13D,%XMM7,%XMM5

  (0) 0x4012ac VMOVSS	%XMM3,0x64ef80(,%R13,4)

  (0) 0x4012b6 VADDSS	%XMM11,%XMM3,%XMM1

  (0) 0x4012bb VCVTSI2SS	%ECX,%XMM7,%XMM4

  (0) 0x4012bf VCVTSI2SS	%EDI,%XMM7,%XMM3

  (0) 0x4012c3 VMOVSS	%XMM14,0x58ba80(,%R13,4)

  (0) 0x4012cd VFMADD132SS	%XMM8,%XMM0,%XMM15

  (0) 0x4012d2 VMOVSS	%XMM12,0x58ba80(,%RCX,4)

  (0) 0x4012db VMOVSS	%XMM0,0x58ba80(,%RSI,4)

  (0) 0x4012e4 VADDSS	%XMM10,%XMM0,%XMM0

  (0) 0x4012e9 VFMADD132SS	%XMM8,%XMM14,%XMM5

  (0) 0x4012ee VADDSS	%XMM6,%XMM2,%XMM13

  (0) 0x4012f2 VADDSS	%XMM11,%XMM1,%XMM14

  (0) 0x4012f7 VFMADD132SS	%XMM8,%XMM12,%XMM4

  (0) 0x4012fc VFMADD132SS	%XMM8,%XMM0,%XMM3

  (0) 0x401301 VMOVSS	%XMM2,0x5ed500(,%RCX,4)

  (0) 0x40130a VMOVSS	%XMM1,0x64ef80(,%RCX,4)

  (0) 0x401313 VADDSS	%XMM6,%XMM13,%XMM2

  (0) 0x401317 VADDSS	%XMM11,%XMM14,%XMM1

  (0) 0x40131c VMOVSS	%XMM5,0x52a000(,%R13,4)

  (0) 0x401326 ADD	$0x4,%R13

  (0) 0x40132a VMOVSS	%XMM4,0x52a000(,%RCX,4)

  (0) 0x401333 VMOVSS	%XMM13,0x5ed500(,%RSI,4)

  (0) 0x40133c VMOVSS	%XMM14,0x64ef80(,%RSI,4)

  (0) 0x401345 VMOVSS	%XMM15,0x52a000(,%RSI,4)

  (0) 0x40134e VMOVSS	%XMM0,0x58ba80(,%RDI,4)

  (0) 0x401357 VMOVSS	%XMM2,0x5ed500(,%RDI,4)

  (0) 0x401360 VMOVSS	%XMM1,0x64ef80(,%RDI,4)

  (0) 0x401369 VMOVSS	%XMM3,0x52a000(,%RDI,4)

  (0) 0x401372 CMP	%RAX,%R13

  (0) 0x401375 JNE	401271

(1) 0x40137b LEA	(,%R13,4),%R15

(1) 0x401383 MOV	%R15,%RDX

(1) 0x401386 XOR	%ESI,%ESI

(1) 0x401388 MOV	$0x4c8580,%EDI

(1) 0x40138d VMOVSD	%XMM9,-0x58(%RBP)

(1) 0x401392 CALL	401040 <memset@plt>

(1) 0x401397 MOV	%R15,%RDX

(1) 0x40139a XOR	%ESI,%ESI

(1) 0x40139c MOV	$0x466b00,%EDI

(1) 0x4013a1 CALL	401040 <memset@plt>

(1) 0x4013a6 MOV	%R15,%RDX

(1) 0x4013a9 XOR	%ESI,%ESI

(1) 0x4013ab MOV	$0x405080,%EDI

(1) 0x4013b0 CALL	401040 <memset@plt>

(1) 0x4013b5 XOR	%EAX,%EAX

(1) 0x4013b7 CALL	401960 <mysecond>

(1) 0x4013bc XOR	%ECX,%ECX

(1) 0x4013be XOR	%EDX,%EDX

(1) 0x4013c0 LEA	-0x50(%RBP),%RSI

(1) 0x4013c4 MOV	$0x401590,%EDI

(1) 0x4013c9 VMOVQ	%XMM0,%R15

(1) 0x4013ce MOVL	$0xbb8,-0x40(%RBP)

(1) 0x4013d5 MOV	%EBX,-0x44(%RBP)

(1) 0x4013d8 MOVL	$0x3e6b851f,-0x48(%RBP)

(1) 0x4013df MOV	%R14,-0x50(%RBP)

(1) 0x4013e3 CALL	401090 <GOMP_parallel@plt>

(1) 0x4013e8 XOR	%EAX,%EAX

(1) 0x4013ea CALL	401960 <mysecond>

(1) 0x4013ef VMOVQ	%R15,%XMM7

(1) 0x4013f4 VSUBSD	%XMM7,%XMM0,%XMM8

(1) 0x4013f8 VMOVSD	-0x58(%RBP),%XMM9

(1) 0x4013fd LEA	0x14(%R13),%RAX

(1) 0x401401 CMP	%RAX,%R12

(1) 0x401404 VFMADD231SD	0x1c83(%RIP),%XMM8,%XMM9

(1) 0x40140d VXORPS	%XMM7,%XMM7,%XMM7

(1) 0x401411 VMOVSS	0x1c6b(%RIP),%XMM8

(1) 0x401419 JG	401130

0x40141f VMULSD	0x1c71(%RIP),%XMM9,%XMM0

0x401427 MOV	$0x403058,%EDI

0x40142c MOV	$0x1,%EAX

0x401431 CALL	401030 <printf@plt>

0x401436 ADD	$0x38,%RSP

0x40143a POP	%RBX

0x40143b POP	%R12

0x40143d POP	%R13

0x40143f POP	%R14

0x401441 POP	%R15

0x401443 XOR	%EAX,%EAX

0x401445 POP	%RBP

0x401446 RET

0x401447 MOV	0x8(%R13),%RDI

0x40144b MOV	$0x2,%EDX

0x401450 MOV	$0x403044,%ESI

0x401455 CALL	401070 <strncmp@plt>

0x40145a MOV	$0x3a98,%R12D

0x401460 TEST	%EAX,%EAX

0x401462 JE	4010e7

0x401468 MOV	$0x186a0,%R12D

0x40146e JMP	4010e7

0x401473 NOPW	%CS:(%RAX,%RAX,1)

0x40147d NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○100.00	__libc_start_call_main		libc.so.6

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	main.c:50-192
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:50,57,63,73-82,97,103-123,136-139,152,166-169,185,192.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.17 to 2.00 cycles (5.58x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 11.17 to 0.76 cycles (14.79x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

GOMP_parallel@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:82
printf@plt: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:73
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:74
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:80
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:185
strncmp@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:77

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 28 bytes (3 double precision FP elements). The binary function is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	61
nb uops	67
loop length	241
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.17 cycles
front end	11.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	4.10	3.67	3.67	6.50	4.00	3.90	6.50	6.50	6.50	4.00	3.67
cycles	4.00	4.10	3.67	3.67	6.50	4.00	3.90	6.50	6.50	6.50	4.00	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.17
Dispatch	6.50
Overall L1	11.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	7%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

INT

all	7%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	17%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	9%
load	10%
store	6%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.17 cycles. At this rate:

1% of peak load performance is reached (2.51 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.17 to 6.50 cycles (1.72x speedup).

ASM code

In the binary file, the address of the function is: 4010a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0xbb8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x186a0,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %EDI,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x40301f,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
SUB $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x403030,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CMP $0x2,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 401447 <main+0x3a7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x403047,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA -0x50(%RBP),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x401920,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVL $0,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 401090 <GOMP_parallel@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS 0x1f6d(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x1f6a(%RIP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0x190,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VXORPD %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMULSD 0x1c71(%RIP),%XMM9,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV $0x403058,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV 0x8(%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x403044,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 401070 <strncmp@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x3a98,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4010e7 <main+0x47>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x186a0,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JMP 4010e7 <main+0x47>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	main.c:50-192
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:50,57,63,73-82,97,103-123,136-139,152,166-169,185,192.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.17 to 2.00 cycles (5.58x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

GOMP_parallel@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:82
printf@plt: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:73
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:74
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:80
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:185
strncmp@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2357/intel/HACCmk/build/HACCmk/src/main.c:77

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 28 bytes (3 double precision FP elements). The binary function is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	61
nb uops	67
loop length	241
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.17 cycles
front end	11.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	4.10	3.67	3.67	6.50	4.00	3.90	6.50	6.50	6.50	4.00	3.67
cycles	4.00	4.10	3.67	3.67	6.50	4.00	3.90	6.50	6.50	6.50	4.00	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.17
Dispatch	6.50
Overall L1	11.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	7%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

INT

all	7%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	17%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	9%
load	10%
store	6%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.17 cycles. At this rate:

1% of peak load performance is reached (2.51 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4010a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0xbb8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x186a0,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %EDI,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x40301f,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
SUB $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x403030,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CMP $0x2,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 401447 <main+0x3a7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x403047,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA -0x50(%RBP),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x401920,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVL $0,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 401090 <GOMP_parallel@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS 0x1f6d(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x1f6a(%RIP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0x190,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VXORPD %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMULSD 0x1c71(%RIP),%XMM9,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV $0x403058,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 401030 <printf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV 0x8(%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x403044,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 401070 <strncmp@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x3a98,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4010e7 <main+0x47>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x186a0,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JMP 4010e7 <main+0x47>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼main–	0.07	0.01
▼Loop 1 - main.c:97-169 - exec–	0.00	0.00
○Loop 0 - main.c:111-116 - exec	0.07	1.47

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code