	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/run/oneview_runs/defaults/icx/oneview_results_1786633223 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/run/oneview_runs/defaults/icx/oneview_results_1786633223


+====================================================================================================================+
+                                                    1  -  GLOBAL                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             1.1  -  Experiment Summary                                             +
+--------------------------------------------------------------------------------------------------------------------+

  Application:			/beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/run/base_runs/defaults/icx/exec
  Timestamp:			2026-08-13 17:00:23
  Universal Timestamp:		1786633223
  Experiment Type:		MPI; OpenMP; Throughput; 
  Machine:			gmz17.benchmarkcenter.megware.com
  Architecture:			x86_64
  Micro Architecture:		ZEN_V5
  Model Name:			AMD EPYC 9655 96-Core Processor
  Cache Size:			1024 KB
  Number of Cores:		96
  OS Version:			Linux 5.14.0-687.29.1.el9_8.x86_64 #1 SMP PREEMPT_DYNAMIC Thu Jul 23 16:18:48 EDT 2026
  Compilation Options:		
		exec:  --intel -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/build/CoMD/CoMD/src-openmp -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/build/icx -O3 -march=native -D DO_MPI -g -fno-omit-frame-pointer -fcf-protection=none -no-pie -grecord-command-line -fiopenmp -MD -MT CMakeFiles/CoMD-openmp-mpi.dir/CoMD/src-openmp/ljForce.c.o -MF CMakeFiles/CoMD-openmp-mpi.dir/CoMD/src-openmp/ljForce.c.o.d -o CMakeFiles/CoMD-openmp-mpi.dir/CoMD/src-openmp/ljForce.c.o -c /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c -I /cluster/hpcx/2.22/ompi5-ifx-mt/include -I /cluster/hpcx/2.22/ompi5-ifx-mt/include/openmpi -fveclib=SVML 
  Number of processes observed:	1
  Number of threads observed:	191
  MAQAO version:		2026.1.0
  MAQAO build:			6d1be1d51c1e63266254997eb301734a7264775d::20260810-150026




+--------------------------------------------------------------------------------------------------------------------+
+                                               1.2  -  Global Metrics                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Total Time:				12.69 s
  Max (Thread Active Time):		12.36 s
  Average Active Time:			12.24 s
  Activity Ratio:			99.4 %
  Average number of active threads:	184.271
  Affinity Stability:			99.3 %
  Time spent in analyzed loops:		30.8 %
  Time spent in analyzed innermost loops: 29.7 %
  Time spent in user code:		30.9 %
  Compilation Options Score:		100
  Array Access Efficiency:		87.1 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.23
  Perfect OpenMP/MPI/Pthread/TBB:	1.24
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	3.05
  If No Scalar Integer:
      Potential Speedup:		1.01
      Nb Loops to get 80%:		2
  If FP Vectorized:
      Potential Speedup:		1.15
      Nb Loops to get 80%:		1
  If Fully Vectorized:
      Potential Speedup:		1.30
      Nb Loops to get 80%:		2
  If Only FP Arithmetic:
      Potential Speedup:		1.09
      Nb Loops to get 80%:		4




+--------------------------------------------------------------------------------------------------------------------+
+                                             1.3  -  Potential Speedups                                             +
+--------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 4      | 9      | 12     | 17     | 
      Cumulated Speedup | 1.0056 | 1.0082 | 1.0086 | 1.0086 | 1.0086 | 
  Top 5 loops:
    exec - 101:	1.0056
    exec - 92:	1.0071
    exec - 109:	1.0078
    exec - 106:	1.0082
    exec - 67:	1.0084

  If FP Vectorized:
      Number of loops   | 1      | 4      | 9      | 12     | 17     | 
      Cumulated Speedup | 1.1472 | 1.1505 | 1.1507 | 1.1507 | 1.1507 | 
  Top 5 loops:
    exec - 99:	1.1472
    exec - 110:	1.1487
    exec - 92:	1.1501
    exec - 117:	1.1505
    exec - 83:	1.1506

  If Fully Vectorized:
      Number of loops   | 1      | 4      | 9      | 12     | 17     | 
      Cumulated Speedup | 1.2316 | 1.2821 | 1.2947 | 1.2965 | 1.2973 | 
  Top 5 loops:
    exec - 99:	1.2316
    exec - 68:	1.257
    exec - 101:	1.2779
    exec - 105:	1.2821
    exec - 98:	1.286

  If Only FP Arithmetic:
      Number of loops   | 1      | 4      | 9      | 12     | 17     | 
      Cumulated Speedup | 1.0328 | 1.0746 | 1.0891 | 1.0906 | 1.0909 | 
  Top 5 loops:
    exec - 68:	1.0328
    exec - 106:	1.0491
    exec - 101:	1.0637
    exec - 99:	1.0746
    exec - 109:	1.0819



+====================================================================================================================+
+                                                   2  -  SUMMARY                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             2.1  -  EXPERIMENT QUALITY                                             +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (12.36 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [2.9974690196828 / 3] Most of time spent in analyzed modules (99.92%) comes from functions compiled with architecture specialization option
-march=native


  [3 / 3] Most of time spent in analyzed modules comes from functions with compilation options informations and
-fno-omit-frame-pointer is present
-fno-omit-frame-pointer improves the accuracy of callchains found during the application profiling.

  [3 / 3] Optimization level option is correctly used


  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.07 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the execution
time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+--------------------------------------------------------------------------------------------------------------------+
+                                                2.2  -  CODE QUALITY                                                +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (30.81%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [4 / 4] Threads activity is good
On average, more than 96.48% of observed threads are actually active 

  [4 / 4] CPU activity is good
CPU cores are active 99.41% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (22.07%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (29.73%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (99.28%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [0 / 3] Too many functions do not use all threads
Functions running on a reduced number of threads (typically sequential code) cover at least 10% of application
walltime (56.70%). Check both "Max Inclusive Time Over Threads" and "Nb Threads" in Functions or Loops tabs and
consider parallelizing sequential regions or improving parallelization of regions running on a reduced number of
threads

  [3 / 3] Cumulative Outermost/In between loops coverage (1.07%) lower than cumulative innermost loop coverage (29.73%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+--------------------------------------------------------------------------------------------------------------------+
+                                               2.3  -  LOOPS OVERVIEW                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 99  :
     analysis: Execution Time: 22 % - Vectorization Ratio: 35.93 % - Vector Length Use: 16.99 %
     Loop Computation Issues: 4
        [4] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 1
            issues (= instructions) costing 4 points each.
     Control Flow Issues: 3
        [3] [SA] Several paths (3 paths) - Simplify control structure or force the compiler to use masked
            instructions. There are 3 issues ( = paths) costing 1 point each.
     Data Access Issues: 4
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [2] [SA] Presence of special instructions executing on a single port (SHUFFLE/PERM, BROADCAST) - Simplify data
            access and try to get stride 1 access. There are 2 issues (= instructions) costing 1 point each.
     Vectorization Roadblocks: 5
        [3] [SA] Several paths (3 paths) - Simplify control structure or force the compiler to use masked
            instructions. There are 3 issues ( = paths) costing 1 point each.
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
     Inefficient Vectorization: 2
        [2] [SA] Presence of special instructions executing on a single port (SHUFFLE/PERM, BROADCAST) - Simplify data
            access and try to get stride 1 access. There are 2 issues (= instructions) costing 1 point each.

   + exec - 68  :
     analysis: Execution Time: 3 % - Vectorization Ratio: 97.22 % - Vector Length Use: 60.07 %
     Data Access Issues: 43
        [4] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 1 issues ( = indirect data accesses) costing 4 point each.
        [0] [SA] Inefficient vectorization: more than 10% of the vector loads instructions are unaligned - When
            allocating arrays, don’t forget to align them. There are 0 issues ( = arrays) costing 2 points each
        [32] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 8 issues (=
            instructions) costing 4 points each.
        [7] [SA] Presence of special instructions executing on a single port (SHUFFLE/PERM, BROADCAST) - Simplify data
            access and try to get stride 1 access. There are 7 issues (= instructions) costing 1 point each.
     Vectorization Roadblocks: 4
        [4] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 1 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 41
        [32] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 8 issues (=
            instructions) costing 4 points each.
        [7] [SA] Presence of special instructions executing on a single port (SHUFFLE/PERM, BROADCAST) - Simplify data
            access and try to get stride 1 access. There are 7 issues (= instructions) costing 1 point each.
        [2] [SA] Inefficient vectorization: use of masked instructions - Simplify control structure. The issue costs 2
            points.

   + exec - 106 :
     analysis: Execution Time: 1 % - Vectorization Ratio: 96.67 % - Vector Length Use: 82.08 %
     Data Access Issues: 39
        [8] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 2 issues ( = indirect data accesses) costing 4 point each.
        [24] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 6 issues (=
            instructions) costing 4 points each.
        [7] [SA] Presence of special instructions executing on a single port (SHUFFLE/PERM, BROADCAST) - Simplify data
            access and try to get stride 1 access. There are 7 issues (= instructions) costing 1 point each.
     Vectorization Roadblocks: 8
        [8] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 2 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 31
        [24] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 6 issues (=
            instructions) costing 4 points each.
        [7] [SA] Presence of special instructions executing on a single port (SHUFFLE/PERM, BROADCAST) - Simplify data
            access and try to get stride 1 access. There are 7 issues (= instructions) costing 1 point each.

   + exec - 101 :
     analysis: Execution Time: 1 % - Vectorization Ratio: 33.33 % - Vector Length Use: 12.50 %
     Loop Computation Issues: 2
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.

   + exec - 109 :
     analysis: Execution Time: 0 % - Vectorization Ratio: 82.18 % - Vector Length Use: 67.57 %
     Loop Computation Issues: 10
        [8] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 2
            issues (= instructions) costing 4 points each.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Control Flow Issues: 20
        [18] [SA] Too many paths (14 paths) - Simplify control structure. There are 14 issues ( = paths) costing 1
            point each with a malus of 4 points.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Data Access Issues: 77
        [56] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 14 issues (=
            instructions) costing 4 points each.
        [19] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM, BROADCAST,
            MASKMOV/MOV2M) - Simplify data access and try to get stride 1 access. There are 19 issues (=
            instructions) costing 1 point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 20
        [18] [SA] Too many paths (14 paths) - Simplify control structure. There are 14 issues ( = paths) costing 1
            point each with a malus of 4 points.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Inefficient Vectorization: 77
        [56] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 14 issues (=
            instructions) costing 4 points each.
        [19] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM, BROADCAST,
            MASKMOV/MOV2M) - Simplify data access and try to get stride 1 access. There are 19 issues (=
            instructions) costing 1 point each.
        [2] [SA] Inefficient vectorization: use of masked instructions - Simplify control structure. The issue costs 2
            points.



+====================================================================================================================+
+                                                 3  -  APPLICATION                                                  +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                               3.1  -  Categorization                                               +
+--------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others  | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+---------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 30.92  | 2.02    | 0.07    | 0.00   | 0.03   | 0.00  | 0.00  | 66.96 | 0.00    | 0.00  |




+--------------------------------------------------------------------------------------------------------------------+
+                                          3.2  -  Function Based Profiling                                          +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 2                         | 87.71                     | 87.71                     |
   4% to 8%                   | 0                         | 0.00                      | 87.71                     |
   2% to 4%                   | 1                         | 3.38                      | 91.08                     |
   1% to 2%                   | 5                         | 8.01                      | 99.09                     |
   0.5% to 1%                 | 0                         | 0.00                      | 99.09                     |
   0.25% to 0.5%              | 1                         | 0.28                      | 99.38                     |
   0.125% to 0.25%            | 1                         | 0.22                      | 99.59                     |
   < 0.125%                   | 51                        | 0.41                      | 100.00                    |




+--------------------------------------------------------------------------------------------------------------------+
+                                            3.3  -  Loop Based Profiling                                            +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 1                         | 22.07                     | 22.07                     |
   4% to 8%                   | 0                         | 0.00                      | 22.07                     |
   2% to 4%                   | 1                         | 3.25                      | 25.33                     |
   1% to 2%                   | 2                         | 3.13                      | 28.45                     |
   0.5% to 1%                 | 0                         | 0.00                      | 28.45                     |
   0.25% to 0.5%              | 2                         | 0.63                      | 29.09                     |
   0.125% to 0.25%            | 2                         | 0.41                      | 29.50                     |
   < 0.125%                   | 19                        | 0.23                      | 29.73                     |


+====================================================================================================================+
+                                                  4  -  FUNCTIONS                                                   +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                              4.1  -  Top 10 Functions                                              +
+--------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module              | Coverage (%)   | Time (s)       |
  --------------------------------------------------------+---------------------+----------------+----------------+
   kmp_flag_64<false, true>::wait(kmp_info*, int, void*)  | libiomp5.so         | 65.25          | 7.99           |
   ljForce.extracted                                      | exec                | 22.46          | 2.75           |
   sortAtomsInCell                                        | exec                | 3.38           | 0.41           |
   advanceVelocity.extracted                              | exec                | 1.89           | 0.23           |
   unknown_kernel_region                                  | kernel              | 1.74           | 0.21           |
   kmp_flag_native<unsigned long long, (flag_type)1, t... | libiomp5.so         | 1.62           | 0.20           |
   ljForce.extracted.27                                   | exec                | 1.55           | 0.19           |
   advancePosition.extracted                              | exec                | 1.20           | 0.15           |
   __GI___sched_yield                                     | libc.so.6           | 0.28           | 0.03           |
   updateLinkCells                                        | exec                | 0.22           | 5.04           |


+====================================================================================================================+
+                                                    5  -  LOOPS                                                     +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                5.1  -  Top 10 Loops                                                +
+--------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module              | Source Location                                        | Coverage (%)   |
  ----------------+---------------------+--------------------------------------------------------+----------------+
   99             | exec                | ljForce.c:191-191,ljForce.c:197-216                    | 22.07          |
   68             | exec                | haloExchange.c:621-630                                 | 3.25           |
   106            | exec                | timestep.c:74-78                                       | 1.57           |
   101            | exec                | mytype.h:23-23,ljForce.c:158-162                       | 1.55           |
   109            | exec                | timestep.c:85-96                                       | 0.68           |
   111            | exec                | timestep.c:88-94                                       | 0.32           |
   105            | exec                | timestep.c:74-77                                       | 0.31           |
   98             | exec                | ljForce.c:187-187,ljForce.c:197-197                    | 0.27           |
   92             | exec                | linkCells.c:211-237,linkCells.c:246-247,linkCells.c... | 0.22           |
   110            | exec                | timestep.c:88-93                                       | 0.20           |





+====================================================================================================================+
+                                                     6  -  CQA                                                      +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                    +
+--------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 99 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:191,197-216.

The related source loop is not unrolled or unrolled with no peel/tail loop.
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.1.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

8% of peak computational performance is used (4.00 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 18% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.33 cycles (6.12x speedup).

Details
44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 50% of SSE/AVX loads are used in vector version.
 - 33% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 0% of SSE/AVX fused multiply-add instructions are used in vector version.
 - 50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.1.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of FP add operations (the FP add unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 2.00 to 1.75 cycles (1.14x speedup).


Workaround
Reduce the number of FP add instructions




      6.1.1.1.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VUCOMISD: 1 occurrences<<list_path_1_complex_1>>



      6.1.1.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).



      6.1.1.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 8 FP arithmetical operations:
 - 5: addition or subtraction (1 inside FMA instructions)
 - 3: multiply (1 inside FMA instructions)
The binary loop is loading 48 bytes (6 double precision FP elements).


      6.1.1.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.


      6.1.1.1.8  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)




      6.1.1.2  -  Path 2
  ----------------------------------------------------------------------------------------------------------

8% of peak computational performance is used (4.14 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.2.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 15% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 7.00 to 1.00 cycles (7.00x speedup).

Details
23% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 42% of SSE/AVX loads are used in vector version.
 - 33% of SSE/AVX stores are used in vector version.
 - 16% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 12% of SSE/AVX multiply instructions are used in vector version.
 - 20% of SSE/AVX fused multiply-add instructions are used in vector version.
 - 0% of SSE/AVX divide and square root instructions are used in vector version.
 - 40% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.1.2.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 7.00 to 5.00 cycles (1.40x speedup).


Workaround
Reduce the number of FP multiply/FMA instructions




      6.1.1.2.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 6.50 cycles (1.08x speedup).


      6.1.1.2.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 6 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.2.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VUCOMISD: 2 occurrences<<list_path_2_complex_1>>



      6.1.1.2.6  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 2 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.1.2.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

19 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).



      6.1.1.2.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 29 FP arithmetical operations:
 - 13: addition or subtraction (6 inside FMA instructions)
 - 15: multiply (6 inside FMA instructions)
 - 1: divide
The binary loop is loading 96 bytes (12 double precision FP elements).
The binary loop is storing 32 bytes (4 double precision FP elements).


      6.1.1.2.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.23 FP operations per loaded or stored byte.




      6.1.1.3  -  Path 3
  ----------------------------------------------------------------------------------------------------------

6% of peak computational performance is used (3.20 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.3.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 17% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.37 cycles (6.67x speedup).

Details
40% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 50% of SSE/AVX loads are used in vector version.
 - 33% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 0% of SSE/AVX fused multiply-add instructions are used in vector version.
 - 33% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.1.3.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of FP add operations (the FP add unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 2.50 to 2.13 cycles (1.18x speedup).


Workaround
Reduce the number of FP add instructions




      6.1.1.3.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.18x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.3.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VUCOMISD: 2 occurrences<<list_path_3_complex_1>>



      6.1.1.3.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).



      6.1.1.3.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 8 FP arithmetical operations:
 - 5: addition or subtraction (1 inside FMA instructions)
 - 3: multiply (1 inside FMA instructions)
The binary loop is loading 48 bytes (6 double precision FP elements).


      6.1.1.3.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.







      6.1.2  -  Loop 68 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621-630.

The related source loop is multi-versionned.

      6.1.2.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 96.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
Only 60% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 40.00 to 19.86 cycles (2.01x speedup).

Details
97% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 95% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.



      6.1.2.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.2.1.3  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.




      6.1.2.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VPBROADCASTQ: 1 occurrences<<list_path_1_complex_1>>
 - VPSCATTERQD: 2 occurrences<<list_path_1_complex_2>>
 - VSCATTERQPD: 6 occurrences<<list_path_1_complex_3>>



      6.1.2.1.5  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.2.1.6  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 4 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 4 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.2.1.7  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 40.00 to 5.00 cycles (8.00x speedup).

Details
 - VPSCATTERQD: 2 occurrences<<list_path_1_gather_scatter_1>>
 - VSCATTERQPD: 6 occurrences<<list_path_1_gather_scatter_2>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.2.1.8  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------




      6.1.2.1.9  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 288 bytes.
The binary loop is storing 256 bytes.







      6.1.3  -  Loop 106 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74-78.

It is intermediate loop of related source loop which is unrolled by 32 (including vectorization).

      6.1.3.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

2% of peak computational performance is used (1.39 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Unrolling/vectorization cost
  ----------------------------------------------------------------------------------------------------------

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details
The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround
 - recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
 - hardcode most frequent values of loop bounds by adding specialized paths.:
  *  For instance, replace for (i=0; i<n; i++) foo(i) with:
switch (n) {
  case (4): for (i=0; i<4; i++) foo(i); break;
  case (6): for (i=0; i<6; i++) foo(i); break;
  default : for (i=0; i<n; i++) foo(i); break;
}



      6.1.3.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
82% of vector register length is used (average across all SSE/AVX instructions).


Details
96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 95% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.



      6.1.3.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.3.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 24 FMA (fused multiply-add) operations.




      6.1.3.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VGATHERQPD: 6 occurrences<<list_path_1_complex_1>>
 - VMOVUPD: 3 occurrences<<list_path_1_complex_2>>
 - VPBROADCASTQ: 1 occurrences<<list_path_1_complex_3>>



      6.1.3.1.6  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 2 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.3.1.7  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 3 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 3 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.3.1.8  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 34.63 to 5.38 cycles (6.44x speedup).

Details
 - VGATHERQPD: 6 occurrences<<list_path_1_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.3.1.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

3 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.3.1.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 48 FP arithmetical operations:
 - 24: addition or subtraction (all inside FMA instructions)
 - 24: multiply (all inside FMA instructions)
The binary loop is loading 384 bytes (48 double precision FP elements).
The binary loop is storing 192 bytes (24 double precision FP elements).


      6.1.3.1.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.4  -  Loop 101 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:23
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:158-162


It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.4.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 96.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 6.25 to 4.00 cycles (1.56x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.4.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 12% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 6.25 to 1.00 cycles (6.25x speedup).

Details
33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 33% of SSE/AVX stores are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.4.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 6.25 to 4.00 cycles (1.56x speedup).


Workaround
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop
  * use the 'restrict' C99 keyword




No data for this section



      6.1.4.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - LEA: 1 occurrences<<list_path_1_complex_1>>



      6.1.4.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.4.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is storing 256 bytes.







      6.1.5  -  Loop 109 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-96.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Too many paths. Rerun with max-paths=14
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 14 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.5.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
 - The number of fused uops of the instruction [VPCMPNLEUD	%ZMM2,%ZMM19,%K1] is unknown
 - The number of fused uops of the instruction [VPCMPNLEUD	%YMM2,%YMM19,%K3] is unknown
 - The number of fused uops of the instruction [VPCMPNLEUD	%YMM3,%YMM19,%K2] is unknown

2% of peak computational performance is used (1.21 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 92.38 to 82.75 cycles (1.12x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.5.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 67% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 92.38 to 85.40 cycles (1.08x speedup).

Details
82% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 93% of SSE/AVX loads are used in vector version.
 - 88% of SSE/AVX stores are used in vector version.
 - 90% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 77% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.



      6.1.5.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.5.1.4  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.5.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 48 FMA (fused multiply-add) operations.




      6.1.5.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - LEA: 4 occurrences<<list_path_1_complex_1>>
 - VGATHERQPD: 14 occurrences<<list_path_1_complex_2>>
 - VMOVUPD: 8 occurrences<<list_path_1_complex_3>>
 - VPBROADCASTQ: 1 occurrences<<list_path_1_complex_4>>



      6.1.5.1.7  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 8 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 8 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.5.1.8  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 92.38 to 24.13 cycles (3.83x speedup).

Details
 - VGATHERQPD: 14 occurrences<<list_path_1_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.5.1.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.5.1.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 112 FP arithmetical operations:
 - 48: addition or subtraction (all inside FMA instructions)
 - 48: multiply (all inside FMA instructions)
 - 16: divide
The binary loop is loading 1060 bytes (132 double precision FP elements).
The binary loop is storing 520 bytes (65 double precision FP elements).


      6.1.5.1.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.







      6.1.6  -  Loop 111 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88-94.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

      6.1.6.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

10% of peak computational performance is used (5.09 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using 96% register length (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 22.00 to 21.50 cycles (1.02x speedup).

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.



      6.1.6.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).


Workaround
Reduce the number of FP multiply/FMA instructions




      6.1.6.1.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 48 FMA (fused multiply-add) operations.




      6.1.6.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - LEA: 1 occurrences<<list_path_1_complex_1>>
 - VGATHERQPD: 2 occurrences<<list_path_1_complex_2>>
 - VMOVUPD: 6 occurrences<<list_path_1_complex_3>>



      6.1.6.1.5  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.6.1.6  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 18 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 18 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.6.1.7  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 22.00 to 19.00 cycles (1.16x speedup).

Details
 - VGATHERQPD: 2 occurrences<<list_path_1_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.6.1.8  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.6.1.9  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 112 FP arithmetical operations:
 - 48: addition or subtraction (all inside FMA instructions)
 - 48: multiply (all inside FMA instructions)
 - 16: divide
The binary loop is loading 960 bytes (120 double precision FP elements).
The binary loop is storing 384 bytes (48 double precision FP elements).


      6.1.6.1.10  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.7  -  Loop 105 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74-77.

It is peel/tail loop of related source loop which is unrolled by 32 (including vectorization).

      6.1.7.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

8% of peak computational performance is used (4.00 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.1.1  -  Unrolling/vectorization cost
  ----------------------------------------------------------------------------------------------------------

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details
The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround
 - recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
 - hardcode most frequent values of loop bounds by adding specialized paths.:
  *  For instance, replace for (i=0; i<n; i++) foo(i) with:
switch (n) {
  case (4): for (i=0; i<4; i++) foo(i); break;
  case (6): for (i=0; i<6; i++) foo(i); break;
  default : for (i=0; i<n; i++) foo(i); break;
}



      6.1.7.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 18% of vector register length is used (average across all SSE/AVX instructions).


Details
50% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 50% of SSE/AVX loads are used in vector version.
 - 50% of SSE/AVX stores are used in vector version.
 - 50% of SSE/AVX fused multiply-add instructions are used in vector version.



      6.1.7.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 1.50 to 1.00 cycles (1.50x speedup).


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop
  * use the 'restrict' C99 keyword





      6.1.7.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 3 FMA (fused multiply-add) operations.




      6.1.7.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).



      6.1.7.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 6 FP arithmetical operations:
 - 3: addition or subtraction (all inside FMA instructions)
 - 3: multiply (all inside FMA instructions)
The binary loop is loading 48 bytes (6 double precision FP elements).
The binary loop is storing 24 bytes (3 double precision FP elements).


      6.1.7.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.8  -  Loop 98 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187-191,197-216.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187,197.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.8.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
This path is accessible from 3 CFG paths (including child blocks)

0% of peak computational performance is used (0.00 out of 96.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.
By vectorizing your loop, you can lower the cost of an iteration from 1.17 to 0.15 cycles (8.00x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.8.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.8.1.3  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.8.1.4  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.8.1.5  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop does not load or store any data.







      6.1.9  -  Loop 92 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-237,246-247,258-269,293-301,327-334,352-365,371-373.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:
 - Ignoring paths for analysis
 - Too many paths. If you really need to analyze all of the 330 paths individually, rerun with max-paths=330
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 330 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.9.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.22 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 27.50 to 9.50 cycles (2.89x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.9.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 12% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 27.50 to 2.37 cycles (11.58x speedup).

Details
16% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 22% of SSE/AVX loads are used in vector version.
 - 26% of SSE/AVX stores are used in vector version.
 - 0% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 0% of SSE/AVX multiply instructions are used in vector version.
 - 0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.9.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.9.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).





      6.1.9.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - CMOVBE: 1 occurrences<<list_path_1_complex_1>>
 - LEA: 5 occurrences<<list_path_1_complex_2>>
 - VCVTTSD2SI: 3 occurrences<<list_path_1_complex_3>>
 - VUCOMISD: 4 occurrences<<list_path_1_complex_4>>



      6.1.9.1.6  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - VCVTTSD2SI (FP64 to INT32/64, scalar): 3 occurrences<<list_path_1_cvt_1>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.9.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

13 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.9.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 6 FP arithmetical operations:
 - 3: addition or subtraction
 - 3: multiply
The binary loop is loading 500 bytes (62 double precision FP elements).
The binary loop is storing 204 bytes (25 double precision FP elements).


      6.1.9.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.


      6.1.9.1.10  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)







      6.1.10  -  Loop 110 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88-93.

It is peel/tail loop of related source loop which is unrolled by 16 (including vectorization).

      6.1.10.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.75 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.10.1.1  -  Unrolling/vectorization cost
  ----------------------------------------------------------------------------------------------------------

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details
The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround
 - recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
 - hardcode most frequent values of loop bounds by adding specialized paths.:
  *  For instance, replace for (i=0; i<n; i++) foo(i) with:
switch (n) {
  case (4): for (i=0; i<4; i++) foo(i); break;
  case (6): for (i=0; i<6; i++) foo(i); break;
  default : for (i=0; i<n; i++) foo(i); break;
}



      6.1.10.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 17% of vector register length is used (average across all SSE/AVX instructions).


Details
37% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 40% of SSE/AVX loads are used in vector version.
 - 50% of SSE/AVX stores are used in vector version.
 - 50% of SSE/AVX fused multiply-add instructions are used in vector version.
 - 0% of SSE/AVX divide and square root instructions are used in vector version.
 - 0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.



      6.1.10.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 4.00 to 2.00 cycles (2.00x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.10.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.75 cycles (2.29x speedup).


      6.1.10.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 3 FMA (fused multiply-add) operations.




      6.1.10.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).



      6.1.10.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 7 FP arithmetical operations:
 - 3: addition or subtraction (all inside FMA instructions)
 - 3: multiply (all inside FMA instructions)
 - 1: divide
The binary loop is loading 60 bytes (7 double precision FP elements).
The binary loop is storing 24 bytes (3 double precision FP elements).


      6.1.10.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3091/intel/CoMD/run/oneview_runs/defaults/icx/oneview_run_1786633223"
[MAQAO] Info: 
