OV - exec - Loop 66

	Loop Id: 66	Module: exec	Source: haloExchange.c:621-630	Coverage: 1.22%

0x408380 VMOVDQU	(%R10,%RSI,4),%XMM4    [1]

0x408386 VPBROADCASTQ	%RSI,%YMM5

0x40838c VPCMPEQB	%XMM0,%XMM0,%K2

0x408392 VPADDQ	%YMM0,%YMM5,%YMM5

0x408396 VPSLLQ	$0x3,%YMM5,%YMM6

0x40839b VPSUBQ	%YMM5,%YMM6,%YMM5

0x40839f VPSCATTERQD	%XMM4,(%RBX,%YMM5,8){%K2}    [3]

0x4083a6 VPCMPEQB	%XMM0,%XMM0,%K2

0x4083ac VMOVDQU	(%R13,%RSI,4),%XMM4    [2]

0x4083b3 ADD	$0x4,%RSI

0x4083b7 VPSCATTERQD	%XMM4,0x4(%RBX,%YMM5,8){%K2}    [3]

0x4083bf VPCMPEQB	%XMM0,%XMM0,%K2

0x4083c5 VMOVUPD	(%RCX,%R11,1),%ZMM6    [4]

0x4083cc VMOVUPD	0x40(%RCX,%R11,1),%ZMM4{%K1}{z}    [4]

0x4083d4 VMOVAPD	%ZMM6,%ZMM7

0x4083da VPERMT2PD	%ZMM4,%ZMM1,%ZMM7

0x4083e0 VMOVAPD	%ZMM6,%ZMM8

0x4083e6 VPERMT2PD	%ZMM4,%ZMM2,%ZMM8

0x4083ec VPERMT2PD	%ZMM4,%ZMM3,%ZMM6

0x4083f2 VSCATTERQPD	%YMM7,0x8(%RBX,%YMM5,8){%K2}    [3]

0x4083fa VPCMPEQB	%XMM0,%XMM0,%K2

0x408400 VSCATTERQPD	%YMM8,0x10(%RBX,%YMM5,8){%K2}    [3]

0x408408 VPCMPEQB	%XMM0,%XMM0,%K2

0x40840e VSCATTERQPD	%YMM6,0x18(%RBX,%YMM5,8){%K2}    [3]

0x408416 VPCMPEQB	%XMM0,%XMM0,%K2

0x40841c VMOVUPD	(%RDX,%R11,1),%ZMM6    [5]

0x408423 VMOVUPD	0x40(%RDX,%R11,1),%ZMM4{%K1}{z}    [5]

0x40842b ADD	$0x60,%R11

0x40842f VMOVAPD	%ZMM6,%ZMM7

0x408435 VPERMT2PD	%ZMM4,%ZMM1,%ZMM7

0x40843b VMOVAPD	%ZMM6,%ZMM8

0x408441 VPERMT2PD	%ZMM4,%ZMM2,%ZMM8

0x408447 VPERMT2PD	%ZMM4,%ZMM3,%ZMM6

0x40844d VSCATTERQPD	%YMM7,0x20(%RBX,%YMM5,8){%K2}    [3]

0x408455 VPCMPEQB	%XMM0,%XMM0,%K2

0x40845b VSCATTERQPD	%YMM8,0x28(%RBX,%YMM5,8){%K2}    [3]

0x408463 VPCMPEQB	%XMM0,%XMM0,%K2

0x408469 VSCATTERQPD	%YMM6,0x30(%RBX,%YMM5,8){%K2}    [3]

0x408471 CMP	%R14,%RSI

0x408474 JLE	408380

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 621 - 630

--------------------------------------------------------------------------------

621:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

622:    {

623:       tmp[iTmp].gid  = atoms->gid[ii];

624:       tmp[iTmp].type = atoms->iSpecies[ii];

625:       tmp[iTmp].rx =   atoms->r[ii][0];

626:       tmp[iTmp].ry =   atoms->r[ii][1];

627:       tmp[iTmp].rz =   atoms->r[ii][2];

628:       tmp[iTmp].px =   atoms->p[ii][0];

629:       tmp[iTmp].py =   atoms->p[ii][1];

630:       tmp[iTmp].pz =   atoms->p[ii][2];

Coverage (%)	Name	Source Location	Module
►13.14+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:47	exec
○	main	CoMD.c:125	exec
►12.82+	redistributeAtoms.extracted	timestep.c:153	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:47	exec
○	main	CoMD.c:125	exec
►12.45+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:47	exec
○	main	CoMD.c:125	exec
►12.25+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:47	exec
○	main	CoMD.c:125	exec
►12.24+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:47	exec
○	main	CoMD.c:125	exec
►12.18+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:47	exec
○	main	CoMD.c:125	exec
►11.59+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:47	exec
○	main	CoMD.c:125	exec
►11.50+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:47	exec
○	main	CoMD.c:125	exec

Coverage (%)	Name	Source Location	Module
►13.05+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.92+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.69+	redistributeAtoms.extracted	timestep.c:153	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.66+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.43+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.39+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►11.95+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►11.91+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►12.86+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.85+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.76+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.70+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.47+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.25+	redistributeAtoms.extracted	timestep.c:153	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.17+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►11.92+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►12.85+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.81+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.73+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.73+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.41+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.40+	redistributeAtoms.extracted	timestep.c:153	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.12+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►11.96+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►12.82+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.70+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.69+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.68+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.52+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.27+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.21+	redistributeAtoms.extracted	timestep.c:153	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.09+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►13.02+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.77+	redistributeAtoms.extracted	timestep.c:153	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.76+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.55+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.35+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.29+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.28+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►11.94+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	P14, P15,
Function	sortAtomsInCell
Source	haloExchange.c:621-630
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	40.00
CQA cycles if no scalar integer	40.00
CQA cycles if FP arith vectorized	40.00
CQA cycles if fully vectorized	19.86
Front-end cycles	31.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	9.50
P7 cycles	9.50
P8 cycles	9.50
P9 cycles	9.50
P10 cycles	2.00
P11 cycles	13.33
P12 cycles	13.33
P13 cycles	13.33
P14 cycles	40.00
P15 cycles	40.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	248.00
Nb loads	6.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.60
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	97.22
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	95.00
Vector-efficiency ratio all	60.07
Vector-efficiency ratio load	75.00
Vector-efficiency ratio store	43.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	63.13

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	P14, P15,
Function	sortAtomsInCell
Source	haloExchange.c:621-630
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	40.00
CQA cycles if no scalar integer	40.00
CQA cycles if FP arith vectorized	40.00
CQA cycles if fully vectorized	19.86
Front-end cycles	31.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	9.50
P7 cycles	9.50
P8 cycles	9.50
P9 cycles	9.50
P10 cycles	2.00
P11 cycles	13.33
P12 cycles	13.33
P13 cycles	13.33
P14 cycles	40.00
P15 cycles	40.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	248.00
Nb loads	6.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.60
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	97.22
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	95.00
Vector-efficiency ratio all	60.07
Vector-efficiency ratio load	75.00
Vector-efficiency ratio store	43.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	63.13

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	sortAtomsInCell
Source file and lines	haloExchange.c:621-630
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621-630.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 60% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 40.00 to 19.86 cycles (2.01x speedup).

Details

97% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

95% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPBROADCASTQ: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621
VPSCATTERQD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:623
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
VSCATTERQPD: 6 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:625
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:626
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:627
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:628
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:629
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:630

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 4 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 4 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VPSCATTERQD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:623
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
VSCATTERQPD: 6 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:625
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:626
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:627
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:628
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:629
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:630

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 288 bytes. The binary loop is storing 256 bytes.

General properties

nb instructions	40
nb uops	248
loop length	250
used x86 registers	8
used mmx registers	0
used xmm registers	2
used ymm registers	5
used zmm registers	7
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	31.00 cycles
front end	31.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	0.50	0.50	0.50	9.50	9.50	9.50	9.50	2.00	13.33	13.33	13.33	40.00	40.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	9.50	9.50	9.50	9.50	2.00	13.33	13.33	13.33	40.00	40.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	31.00
Dispatch	40.00
Data deps.	1.00
Overall L1	40.00

Vectorization ratios

INT

all	93%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	90%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	97%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	95%

Vector efficiency ratios

INT

all	28%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	26%

all	85%
load	100%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	60%
load	75%
store	43%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	63%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

2% of peak load performance is reached (7.20 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 408380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVDQU (%R10,%RSI,4),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPBROADCASTQ %RSI,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPCMPEQB %XMM0,%XMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPADDQ %YMM0,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPSLLQ $0x3,%YMM5,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (50.0%)
VPSUBQ %YMM5,%YMM6,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPSCATTERQD %XMM4,(%RBX,%YMM5,8){%K2}	27	0	0	0	0	0	0	1	1	1	1	0	0.67	1.17	1.17	5	5	3-42	5	vect (25.0%)
VPCMPEQB %XMM0,%XMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVDQU (%R13,%RSI,4),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPSCATTERQD %XMM4,0x4(%RBX,%YMM5,8){%K2}	27	0	0	0	0	0	0	1	1	1	1	0	0.67	1.17	1.17	5	5	3-42	5	vect (25.0%)
VPCMPEQB %XMM0,%XMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RCX,%R11,1),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RCX,%R11,1),%ZMM4{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM4,%ZMM1,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM4,%ZMM2,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM4,%ZMM3,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VSCATTERQPD %YMM7,0x8(%RBX,%YMM5,8){%K2}	27	0	0	0	0	0	0	1	1	1	1	0	0.83	1.33	0.83	5	5	1-40	5	vect (50.0%)
VPCMPEQB %XMM0,%XMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VSCATTERQPD %YMM8,0x10(%RBX,%YMM5,8){%K2}	27	0	0	0	0	0	0	1	1	1	1	0	0.83	1.33	0.83	5	5	1-40	5	vect (50.0%)
VPCMPEQB %XMM0,%XMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VSCATTERQPD %YMM6,0x18(%RBX,%YMM5,8){%K2}	27	0	0	0	0	0	0	1	1	1	1	0	0.83	1.33	0.83	5	5	1-40	5	vect (50.0%)
VPCMPEQB %XMM0,%XMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RDX,%R11,1),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RDX,%R11,1),%ZMM4{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
ADD $0x60,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPD %ZMM6,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM4,%ZMM1,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM4,%ZMM2,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM4,%ZMM3,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VSCATTERQPD %YMM7,0x20(%RBX,%YMM5,8){%K2}	27	0	0	0	0	0	0	1	1	1	1	0	0.83	1.33	0.83	5	5	1-40	5	vect (50.0%)
VPCMPEQB %XMM0,%XMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VSCATTERQPD %YMM8,0x28(%RBX,%YMM5,8){%K2}	27	0	0	0	0	0	0	1	1	1	1	0	0.83	1.33	0.83	5	5	1-40	5	vect (50.0%)
VPCMPEQB %XMM0,%XMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VSCATTERQPD %YMM6,0x30(%RBX,%YMM5,8){%K2}	27	0	0	0	0	0	0	1	1	1	1	0	0.83	1.33	0.83	5	5	1-40	5	vect (50.0%)
CMP %R14,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 408380 <sortAtomsInCell+0x130>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A

Function	sortAtomsInCell
Source file and lines	haloExchange.c:621-630
Module	exec

gain
potential
hint
expert

Vectorization

Details

97% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

95% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPBROADCASTQ: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621
VPSCATTERQD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:623
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
VSCATTERQPD: 6 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:625
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:626
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:627
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:628
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:629
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:630

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 4 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 4 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VPSCATTERQD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:623
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
VSCATTERQPD: 6 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:625
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:626
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:627
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:628
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:629
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:630

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 288 bytes. The binary loop is storing 256 bytes.

General properties

nb instructions	40
nb uops	248
loop length	250
used x86 registers	8
used mmx registers	0
used xmm registers	2
used ymm registers	5
used zmm registers	7
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	31.00 cycles
front end	31.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	0.50	0.50	0.50	9.50	9.50	9.50	9.50	2.00	13.33	13.33	13.33	40.00	40.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	9.50	9.50	9.50	9.50	2.00	13.33	13.33	13.33	40.00	40.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	31.00
Dispatch	40.00
Data deps.	1.00
Overall L1	40.00

Vectorization ratios

INT

all	93%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	90%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	97%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	95%

Vector efficiency ratios

INT

all	28%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	26%

all	85%
load	100%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	60%
load	75%
store	43%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	63%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

2% of peak load performance is reached (7.20 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 408380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVDQU (%R10,%RSI,4),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPBROADCASTQ %RSI,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPCMPEQB %XMM0,%XMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPADDQ %YMM0,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPSLLQ $0x3,%YMM5,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (50.0%)
VPSUBQ %YMM5,%YMM6,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPSCATTERQD %XMM4,(%RBX,%YMM5,8){%K2}	27	0	0	0	0	0	0	1	1	1	1	0	0.67	1.17	1.17	5	5	3-42	5	vect (25.0%)
VPCMPEQB %XMM0,%XMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVDQU (%R13,%RSI,4),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPSCATTERQD %XMM4,0x4(%RBX,%YMM5,8){%K2}	27	0	0	0	0	0	0	1	1	1	1	0	0.67	1.17	1.17	5	5	3-42	5	vect (25.0%)
VPCMPEQB %XMM0,%XMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RCX,%R11,1),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RCX,%R11,1),%ZMM4{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM4,%ZMM1,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM4,%ZMM2,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM4,%ZMM3,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VSCATTERQPD %YMM7,0x8(%RBX,%YMM5,8){%K2}	27	0	0	0	0	0	0	1	1	1	1	0	0.83	1.33	0.83	5	5	1-40	5	vect (50.0%)
VPCMPEQB %XMM0,%XMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VSCATTERQPD %YMM8,0x10(%RBX,%YMM5,8){%K2}	27	0	0	0	0	0	0	1	1	1	1	0	0.83	1.33	0.83	5	5	1-40	5	vect (50.0%)
VPCMPEQB %XMM0,%XMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VSCATTERQPD %YMM6,0x18(%RBX,%YMM5,8){%K2}	27	0	0	0	0	0	0	1	1	1	1	0	0.83	1.33	0.83	5	5	1-40	5	vect (50.0%)
VPCMPEQB %XMM0,%XMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RDX,%R11,1),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RDX,%R11,1),%ZMM4{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
ADD $0x60,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPD %ZMM6,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM4,%ZMM1,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM4,%ZMM2,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM4,%ZMM3,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VSCATTERQPD %YMM7,0x20(%RBX,%YMM5,8){%K2}	27	0	0	0	0	0	0	1	1	1	1	0	0.83	1.33	0.83	5	5	1-40	5	vect (50.0%)
VPCMPEQB %XMM0,%XMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VSCATTERQPD %YMM8,0x28(%RBX,%YMM5,8){%K2}	27	0	0	0	0	0	0	1	1	1	1	0	0.83	1.33	0.83	5	5	1-40	5	vect (50.0%)
VPCMPEQB %XMM0,%XMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VSCATTERQPD %YMM6,0x30(%RBX,%YMM5,8){%K2}	27	0	0	0	0	0	0	1	1	1	1	0	0.83	1.33	0.83	5	5	1-40	5	vect (50.0%)
CMP %R14,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 408380 <sortAtomsInCell+0x130>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A

▶Scalability Runs Description

Run 8x1	Number processes: 8Number nodes: NANumber processes per node: 8Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=24 --rank-by fill --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/run/oneview_runs/multicore/icx_1/oneview_run_1773746383OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threadsOMP_NUM_THREADS: 1
Run 8x8	Number processes: 8Number processes per node: 8Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=24 --rank-by fill --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/run/oneview_runs/multicore/icx_1/oneview_run_1773746383OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 8x12	Number processes: 8Number processes per node: 8Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=24 --rank-by fill --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/run/oneview_runs/multicore/icx_1/oneview_run_1773746383OMP_NUM_THREADS: 12OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 8x16	Number processes: 8Number processes per node: 8Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=24 --rank-by fill --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/run/oneview_runs/multicore/icx_1/oneview_run_1773746383OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 8x20	Number processes: 8Number processes per node: 8Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=24 --rank-by fill --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/run/oneview_runs/multicore/icx_1/oneview_run_1773746383OMP_NUM_THREADS: 20OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 8x24	Number processes: 8Number processes per node: 8Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=24 --rank-by fill --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/run/oneview_runs/multicore/icx_1/oneview_run_1773746383OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(8x1) Efficiency	(8x1) Potential Speed-Up (%)	(8x8) Efficiency	(8x8) Potential Speed-Up (%)	(8x12) Efficiency	(8x12) Potential Speed-Up (%)	(8x16) Efficiency	(8x16) Potential Speed-Up (%)	(8x20) Efficiency	(8x20) Potential Speed-Up (%)	(8x24) Efficiency	(8x24) Potential Speed-Up (%)
1	0	1.28	0	0.9	0.14	0.72	0.42	0.58	0.63	0.5	0.75

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
8x1	8	1	1	1	5.0600008964539	1.2152216434479
8x8	40	1.28	6.41	5	0.9099999666214	1.3365603685379
8x12	72	0.9	8.08	9	0.72000002861023	1.4042023420334
8x16	104	0.72	9.31	13	0.60500001907349	1.4640947580338
8x20	136	0.58	9.81	17	0.58000004291534	1.4924184083939
8x24	168	0.5	10.58	21	0.52499997615814	1.510435461998

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency