OV - exec - Loop 103

0x40f290 VMOVSD	(%R10,%R11,1),%XMM9    [2]

0x40f296 VFMADD213SD	(%R9,%R11,1),%XMM0,%XMM9    [1]

0x40f29c VMOVSD	%XMM9,(%R9,%R11,1)    [1]

0x40f2a2 VMOVUPD	0x8(%R10,%R11,1),%XMM9    [2]

0x40f2a9 VFMADD213PD	0x8(%R9,%R11,1),%XMM1,%XMM9    [1]

0x40f2b0 VMOVUPD	%XMM9,0x8(%R9,%R11,1)    [1]

0x40f2b7 ADD	$0x18,%R11

0x40f2bb DEC	%R8D

0x40f2be JNE	40f290

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 74 - 77

--------------------------------------------------------------------------------

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

Coverage (%)	Name	Source Location	Module
►49.87+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:71	exec
○	main	CoMD.c:125	exec
►49.66+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:39	exec
○	main	CoMD.c:125	exec

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P6, P7, P8, P9,
Function	advanceVelocity.extracted
Source	timestep.c:74-77
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	max
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	1.50
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	0.28
Front-end cycles	1.00
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	8.00
Nb loads	4.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	4.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	24.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	50.00
Vectorization ratio load	50.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	18.75
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P6, P7, P8, P9,
Function	advanceVelocity.extracted
Source	timestep.c:74-77
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	max
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	1.50
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	0.28
Front-end cycles	1.00
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	8.00
Nb loads	4.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	4.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	24.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	50.00
Vectorization ratio load	50.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	18.75
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advanceVelocity.extracted
Source file and lines	timestep.c:74-77
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74-77.

It is peel/tail loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions).

Details

50% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 1.50 to 1.00 cycles (1.50x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

FMA

Detected 3 FMA (fused multiply-add) operations.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 48 bytes (6 double precision FP elements). The binary loop is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	9
nb uops	8
loop length	48
used x86 registers	4
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.00 cycles
front end	1.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	1.50	1.50	1.50	1.50	1.00	1.00	0.00	0.00	1.00	1.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	1.50	1.50	1.50	1.50	1.00	1.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.00
Dispatch	1.50
Data deps.	1.00
Overall L1	1.50

Vectorization ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	18%
load	18%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.50 cycles. At this rate:

12% of peak load performance is reached (32.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (16.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40f290

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSD (%R10,%R11,1),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%R9,%R11,1),%XMM0,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM9,(%R9,%R11,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD 0x8(%R10,%R11,1),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD213PD 0x8(%R9,%R11,1),%XMM1,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM9,0x8(%R9,%R11,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
ADD $0x18,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 40f290 <advanceVelocity.extracted+0x480>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A

Function	advanceVelocity.extracted
Source file and lines	timestep.c:74-77
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74-77.

It is peel/tail loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions).

Details

50% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 1.50 to 1.00 cycles (1.50x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

FMA

Detected 3 FMA (fused multiply-add) operations.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 48 bytes (6 double precision FP elements). The binary loop is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	9
nb uops	8
loop length	48
used x86 registers	4
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.00 cycles
front end	1.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	1.50	1.50	1.50	1.50	1.00	1.00	0.00	0.00	1.00	1.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	1.50	1.50	1.50	1.50	1.00	1.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.00
Dispatch	1.50
Data deps.	1.00
Overall L1	1.50

Vectorization ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	18%
load	18%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.50 cycles. At this rate:

12% of peak load performance is reached (32.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (16.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40f290

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSD (%R10,%R11,1),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%R9,%R11,1),%XMM0,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM9,(%R9,%R11,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD 0x8(%R10,%R11,1),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD213PD 0x8(%R9,%R11,1),%XMM1,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM9,0x8(%R9,%R11,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
ADD $0x18,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 40f290 <advanceVelocity.extracted+0x480>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A

▶Scalability Runs Description

Run 8x1	Number processes: 8Number nodes: NANumber processes per node: 8Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=24 --rank-by fill --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/run/oneview_runs/multicore/icx_1/oneview_run_1773746383OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threadsOMP_NUM_THREADS: 1
Run 8x8	Number processes: 8Number processes per node: 8Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=24 --rank-by fill --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/run/oneview_runs/multicore/icx_1/oneview_run_1773746383OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 8x12	Number processes: 8Number processes per node: 8Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=24 --rank-by fill --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/run/oneview_runs/multicore/icx_1/oneview_run_1773746383OMP_NUM_THREADS: 12OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 8x16	Number processes: 8Number processes per node: 8Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=24 --rank-by fill --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/run/oneview_runs/multicore/icx_1/oneview_run_1773746383OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 8x20	Number processes: 8Number processes per node: 8Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=24 --rank-by fill --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/run/oneview_runs/multicore/icx_1/oneview_run_1773746383OMP_NUM_THREADS: 20OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 8x24	Number processes: 8Number processes per node: 8Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=24 --rank-by fill --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/run/oneview_runs/multicore/icx_1/oneview_run_1773746383OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(8x1) Efficiency	(8x1) Potential Speed-Up (%)	(8x8) Efficiency	(8x8) Potential Speed-Up (%)	(8x12) Efficiency	(8x12) Potential Speed-Up (%)	(8x16) Efficiency	(8x16) Potential Speed-Up (%)	(8x20) Efficiency	(8x20) Potential Speed-Up (%)	(8x24) Efficiency	(8x24) Potential Speed-Up (%)
1	0	1.37	0	0.91	0.03	0.72	0.1	0.59	0.15	0.54	0.16

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
8x1	8	1	1	1	1.2749999761581	0.30204930901527
8x8	40	1.37	6.83	5	0.25499999523163	0.31167319417
8x12	72	0.91	8.18	9	0.21499998867512	0.34472680091858
8x16	104	0.72	9.32	13	0.20000001788139	0.3636269569397
8x20	136	0.59	10.09	17	0.1799999922514	0.36078980565071
8x24	168	0.54	11.43	21	0.16999998688698	0.34766408801079

Report Configuration

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency