OV - exec - Loop 99

	Loop Id: 99	Module: exec	Source: timestep.c:74-78	Coverage: 0.69%

0x40eaa0 MOVSXD	(%R10,%R12,4),%RDI

0x40eaa4 TEST	%EDI,%EDI

0x40eaa6 JLE	40ee88

0x40eaac MOV	0x20(%R11),%R9

0x40eab0 LEA	(%RDI,%RDI,2),%RBX

0x40eab4 LEA	-0x18(,%RBX,8),%RDI

0x40eabc SHR	$0x3,%RDI

0x40eac0 MOV	0x20(%R9),%RSI

0x40eac4 MOV	0x28(%R9),%RCX

0x40eac8 MOV	$0xaaaaaaaaaaaaaab,%R9

0x40ead2 IMUL	%R9,%RDI

0x40ead6 INC	%RDI

0x40ead9 ADD	%R8,%RSI

0x40eadc ADD	%R8,%RCX

0x40eadf AND	$0x7,%EDI

0x40eae2 LEA	(%RSI,%RBX,8),%RDX

0x40eae6 JE	40ecaa

0x40eaec CMP	$0x1,%RDI

0x40eaf0 JE	40ec6a

0x40eaf6 CMP	$0x2,%RDI

0x40eafa JE	40ec33

0x40eb00 CMP	$0x3,%RDI

0x40eb04 JE	40ebfc

0x40eb0a CMP	$0x4,%RDI

0x40eb0e JE	40ebc5

0x40eb14 CMP	$0x5,%RDI

0x40eb18 JE	40eb8e

0x40eb1a CMP	$0x6,%RDI

0x40eb1e JE	40eb57

0x40eb20 VMOVSD	(%RCX),%XMM1

0x40eb24 ADD	$0x18,%RSI

0x40eb28 VFMADD213SD	-0x18(%RSI),%XMM0,%XMM1

0x40eb2e ADD	$0x18,%RCX

0x40eb32 VMOVSD	%XMM1,-0x18(%RSI)

0x40eb37 VMOVSD	-0x10(%RCX),%XMM2

0x40eb3c VFMADD213SD	-0x10(%RSI),%XMM0,%XMM2

0x40eb42 VMOVSD	%XMM2,-0x10(%RSI)

0x40eb47 VMOVSD	-0x8(%RCX),%XMM3

0x40eb4c VFMADD213SD	-0x8(%RSI),%XMM0,%XMM3

0x40eb52 VMOVSD	%XMM3,-0x8(%RSI)

0x40eb57 VMOVSD	(%RCX),%XMM4

0x40eb5b ADD	$0x18,%RSI

0x40eb5f VFMADD213SD	-0x18(%RSI),%XMM0,%XMM4

0x40eb65 ADD	$0x18,%RCX

0x40eb69 VMOVSD	%XMM4,-0x18(%RSI)

0x40eb6e VMOVSD	-0x10(%RCX),%XMM5

0x40eb73 VFMADD213SD	-0x10(%RSI),%XMM0,%XMM5

0x40eb79 VMOVSD	%XMM5,-0x10(%RSI)

0x40eb7e VMOVSD	-0x8(%RCX),%XMM6

0x40eb83 VFMADD213SD	-0x8(%RSI),%XMM0,%XMM6

0x40eb89 VMOVSD	%XMM6,-0x8(%RSI)

0x40eb8e VMOVSD	(%RCX),%XMM7

0x40eb92 ADD	$0x18,%RSI

0x40eb96 VFMADD213SD	-0x18(%RSI),%XMM0,%XMM7

0x40eb9c ADD	$0x18,%RCX

0x40eba0 VMOVSD	%XMM7,-0x18(%RSI)

0x40eba5 VMOVSD	-0x10(%RCX),%XMM8

0x40ebaa VFMADD213SD	-0x10(%RSI),%XMM0,%XMM8

0x40ebb0 VMOVSD	%XMM8,-0x10(%RSI)

0x40ebb5 VMOVSD	-0x8(%RCX),%XMM9

0x40ebba VFMADD213SD	-0x8(%RSI),%XMM0,%XMM9

0x40ebc0 VMOVSD	%XMM9,-0x8(%RSI)

0x40ebc5 VMOVSD	(%RCX),%XMM10

0x40ebc9 ADD	$0x18,%RSI

0x40ebcd VFMADD213SD	-0x18(%RSI),%XMM0,%XMM10

0x40ebd3 ADD	$0x18,%RCX

0x40ebd7 VMOVSD	%XMM10,-0x18(%RSI)

0x40ebdc VMOVSD	-0x10(%RCX),%XMM11

0x40ebe1 VFMADD213SD	-0x10(%RSI),%XMM0,%XMM11

0x40ebe7 VMOVSD	%XMM11,-0x10(%RSI)

0x40ebec VMOVSD	-0x8(%RCX),%XMM12

0x40ebf1 VFMADD213SD	-0x8(%RSI),%XMM0,%XMM12

0x40ebf7 VMOVSD	%XMM12,-0x8(%RSI)

0x40ebfc VMOVSD	(%RCX),%XMM13

0x40ec00 ADD	$0x18,%RSI

0x40ec04 VFMADD213SD	-0x18(%RSI),%XMM0,%XMM13

0x40ec0a ADD	$0x18,%RCX

0x40ec0e VMOVSD	%XMM13,-0x18(%RSI)

0x40ec13 VMOVSD	-0x10(%RCX),%XMM14

0x40ec18 VFMADD213SD	-0x10(%RSI),%XMM0,%XMM14

0x40ec1e VMOVSD	%XMM14,-0x10(%RSI)

0x40ec23 VMOVSD	-0x8(%RCX),%XMM15

0x40ec28 VFMADD213SD	-0x8(%RSI),%XMM0,%XMM15

0x40ec2e VMOVSD	%XMM15,-0x8(%RSI)

0x40ec33 VMOVSD	(%RCX),%XMM1

0x40ec37 ADD	$0x18,%RSI

0x40ec3b VFMADD213SD	-0x18(%RSI),%XMM0,%XMM1

0x40ec41 ADD	$0x18,%RCX

0x40ec45 VMOVSD	%XMM1,-0x18(%RSI)

0x40ec4a VMOVSD	-0x10(%RCX),%XMM2

0x40ec4f VFMADD213SD	-0x10(%RSI),%XMM0,%XMM2

0x40ec55 VMOVSD	%XMM2,-0x10(%RSI)

0x40ec5a VMOVSD	-0x8(%RCX),%XMM3

0x40ec5f VFMADD213SD	-0x8(%RSI),%XMM0,%XMM3

0x40ec65 VMOVSD	%XMM3,-0x8(%RSI)

0x40ec6a VMOVSD	(%RCX),%XMM4

0x40ec6e ADD	$0x18,%RSI

0x40ec72 VFMADD213SD	-0x18(%RSI),%XMM0,%XMM4

0x40ec78 VMOVSD	%XMM4,-0x18(%RSI)

0x40ec7d VMOVSD	0x8(%RCX),%XMM5

0x40ec82 VFMADD213SD	-0x10(%RSI),%XMM0,%XMM5

0x40ec88 VMOVSD	%XMM5,-0x10(%RSI)

0x40ec8d VMOVSD	0x10(%RCX),%XMM6

0x40ec92 ADD	$0x18,%RCX

0x40ec96 VFMADD213SD	-0x8(%RSI),%XMM0,%XMM6

0x40ec9c VMOVSD	%XMM6,-0x8(%RSI)

0x40eca1 CMP	%RDX,%RSI

0x40eca4 JE	40ee88

  (100) 0x40ecaa VMOVSD	(%RCX),%XMM7

  (100) 0x40ecae ADD	$0xc0,%RSI

  (100) 0x40ecb5 VFMADD213SD	-0xc0(%RSI),%XMM0,%XMM7

  (100) 0x40ecbe VMOVSD	%XMM7,-0xc0(%RSI)

  (100) 0x40ecc6 VMOVSD	0x8(%RCX),%XMM8

  (100) 0x40eccb VFMADD213SD	-0xb8(%RSI),%XMM0,%XMM8

  (100) 0x40ecd4 VMOVSD	%XMM8,-0xb8(%RSI)

  (100) 0x40ecdc VMOVSD	0x10(%RCX),%XMM9

  (100) 0x40ece1 VFMADD213SD	-0xb0(%RSI),%XMM0,%XMM9

  (100) 0x40ecea VMOVSD	%XMM9,-0xb0(%RSI)

  (100) 0x40ecf2 VMOVSD	0x18(%RCX),%XMM10

  (100) 0x40ecf7 VFMADD213SD	-0xa8(%RSI),%XMM0,%XMM10

  (100) 0x40ed00 VMOVSD	%XMM10,-0xa8(%RSI)

  (100) 0x40ed08 VMOVSD	0x20(%RCX),%XMM11

  (100) 0x40ed0d VFMADD213SD	-0xa0(%RSI),%XMM0,%XMM11

  (100) 0x40ed16 VMOVSD	%XMM11,-0xa0(%RSI)

  (100) 0x40ed1e VMOVSD	0x28(%RCX),%XMM12

  (100) 0x40ed23 VFMADD213SD	-0x98(%RSI),%XMM0,%XMM12

  (100) 0x40ed2c VMOVSD	%XMM12,-0x98(%RSI)

  (100) 0x40ed34 VMOVSD	0x30(%RCX),%XMM13

  (100) 0x40ed39 VFMADD213SD	-0x90(%RSI),%XMM0,%XMM13

  (100) 0x40ed42 VMOVSD	%XMM13,-0x90(%RSI)

  (100) 0x40ed4a VMOVSD	0x38(%RCX),%XMM14

  (100) 0x40ed4f VFMADD213SD	-0x88(%RSI),%XMM0,%XMM14

  (100) 0x40ed58 VMOVSD	%XMM14,-0x88(%RSI)

  (100) 0x40ed60 VMOVSD	0x40(%RCX),%XMM15

  (100) 0x40ed65 VFMADD213SD	-0x80(%RSI),%XMM0,%XMM15

  (100) 0x40ed6b VMOVSD	%XMM15,-0x80(%RSI)

  (100) 0x40ed70 VMOVSD	0x48(%RCX),%XMM1

  (100) 0x40ed75 VFMADD213SD	-0x78(%RSI),%XMM0,%XMM1

  (100) 0x40ed7b VMOVSD	%XMM1,-0x78(%RSI)

  (100) 0x40ed80 VMOVSD	0x50(%RCX),%XMM2

  (100) 0x40ed85 VFMADD213SD	-0x70(%RSI),%XMM0,%XMM2

  (100) 0x40ed8b VMOVSD	%XMM2,-0x70(%RSI)

  (100) 0x40ed90 VMOVSD	0x58(%RCX),%XMM3

  (100) 0x40ed95 VFMADD213SD	-0x68(%RSI),%XMM0,%XMM3

  (100) 0x40ed9b VMOVSD	%XMM3,-0x68(%RSI)

  (100) 0x40eda0 VMOVSD	0x60(%RCX),%XMM4

  (100) 0x40eda5 VFMADD213SD	-0x60(%RSI),%XMM0,%XMM4

  (100) 0x40edab VMOVSD	%XMM4,-0x60(%RSI)

  (100) 0x40edb0 VMOVSD	0x68(%RCX),%XMM5

  (100) 0x40edb5 VFMADD213SD	-0x58(%RSI),%XMM0,%XMM5

  (100) 0x40edbb VMOVSD	%XMM5,-0x58(%RSI)

  (100) 0x40edc0 VMOVSD	0x70(%RCX),%XMM6

  (100) 0x40edc5 VFMADD213SD	-0x50(%RSI),%XMM0,%XMM6

  (100) 0x40edcb VMOVSD	%XMM6,-0x50(%RSI)

  (100) 0x40edd0 VMOVSD	0x78(%RCX),%XMM7

  (100) 0x40edd5 VFMADD213SD	-0x48(%RSI),%XMM0,%XMM7

  (100) 0x40eddb VMOVSD	%XMM7,-0x48(%RSI)

  (100) 0x40ede0 VMOVSD	0x80(%RCX),%XMM8

  (100) 0x40ede8 VFMADD213SD	-0x40(%RSI),%XMM0,%XMM8

  (100) 0x40edee VMOVSD	%XMM8,-0x40(%RSI)

  (100) 0x40edf3 VMOVSD	0x88(%RCX),%XMM9

  (100) 0x40edfb VFMADD213SD	-0x38(%RSI),%XMM0,%XMM9

  (100) 0x40ee01 VMOVSD	%XMM9,-0x38(%RSI)

  (100) 0x40ee06 VMOVSD	0x90(%RCX),%XMM10

  (100) 0x40ee0e VFMADD213SD	-0x30(%RSI),%XMM0,%XMM10

  (100) 0x40ee14 VMOVSD	%XMM10,-0x30(%RSI)

  (100) 0x40ee19 VMOVSD	0x98(%RCX),%XMM11

  (100) 0x40ee21 VFMADD213SD	-0x28(%RSI),%XMM0,%XMM11

  (100) 0x40ee27 VMOVSD	%XMM11,-0x28(%RSI)

  (100) 0x40ee2c VMOVSD	0xa0(%RCX),%XMM12

  (100) 0x40ee34 VFMADD213SD	-0x20(%RSI),%XMM0,%XMM12

  (100) 0x40ee3a VMOVSD	%XMM12,-0x20(%RSI)

  (100) 0x40ee3f VMOVSD	0xa8(%RCX),%XMM13

  (100) 0x40ee47 VFMADD213SD	-0x18(%RSI),%XMM0,%XMM13

  (100) 0x40ee4d VMOVSD	%XMM13,-0x18(%RSI)

  (100) 0x40ee52 VMOVSD	0xb0(%RCX),%XMM14

  (100) 0x40ee5a VFMADD213SD	-0x10(%RSI),%XMM0,%XMM14

  (100) 0x40ee60 VMOVSD	%XMM14,-0x10(%RSI)

  (100) 0x40ee65 VMOVSD	0xb8(%RCX),%XMM15

  (100) 0x40ee6d ADD	$0xc0,%RCX

  (100) 0x40ee74 VFMADD213SD	-0x8(%RSI),%XMM0,%XMM15

  (100) 0x40ee7a VMOVSD	%XMM15,-0x8(%RSI)

  (100) 0x40ee7f CMP	%RDX,%RSI

  (100) 0x40ee82 JNE	40ecaa

0x40ee88 INC	%R12

0x40ee8b ADD	$0x600,%R8

0x40ee92 CMP	%R12D,%EAX

0x40ee95 JG	40eaa0

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 74 - 78

--------------------------------------------------------------------------------

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

Coverage (%)	Name	Source Location	Module
○98.19	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.81	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.06
CQA speedup if fully vectorized	8.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	P6, P7, P8, P9,
Function	advanceVelocity._omp_fn.0
Source	timestep.c:74-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.75
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	15.88
CQA cycles if fully vectorized	2.03
Front-end cycles	13.88
P0 cycles	7.50
P1 cycles	7.50
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	7.50
P5 cycles	7.50
P6 cycles	16.75
P7 cycles	16.75
P8 cycles	16.75
P9 cycles	16.75
P10 cycles	10.50
P11 cycles	10.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	10.50
P15 cycles	10.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	112.00
Nb uops	111.00
Nb loads	46.00
Nb stores	21.00
Nb stack references	0.00
FLOP/cycle	2.51
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	21.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	31.76
Bytes prefetched	0.00
Bytes loaded	364.00
Bytes stored	168.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.41
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.72

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.06
CQA speedup if fully vectorized	8.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	P6, P7, P8, P9,
Function	advanceVelocity._omp_fn.0
Source	timestep.c:74-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.75
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	15.88
CQA cycles if fully vectorized	2.03
Front-end cycles	13.88
P0 cycles	7.50
P1 cycles	7.50
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	7.50
P5 cycles	7.50
P6 cycles	16.75
P7 cycles	16.75
P8 cycles	16.75
P9 cycles	16.75
P10 cycles	10.50
P11 cycles	10.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	10.50
P15 cycles	10.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	112.00
Nb uops	111.00
Nb loads	46.00
Nb stores	21.00
Nb stack references	0.00
FLOP/cycle	2.51
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	21.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	31.76
Bytes prefetched	0.00
Bytes loaded	364.00
Bytes stored	168.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.41
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.72

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advanceVelocity._omp_fn.0
Source file and lines	timestep.c:74-78
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74-78.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 16.75 to 2.03 cycles (8.25x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 16.75 to 13.88 cycles (1.21x speedup).

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

FMA

Detected 21 FMA (fused multiply-add) operations.

Type of elements and instruction set

21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 42 FP arithmetical operations:

21: addition or subtraction (all inside FMA instructions)
21: multiply (all inside FMA instructions)

The binary loop is loading 364 bytes (45 double precision FP elements). The binary loop is storing 168 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	112
nb uops	111
loop length	541
used x86 registers	11
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.88 cycles
front end	13.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.50	7.50	7.50	7.50	7.50	7.50	16.75	16.75	16.75	16.75	10.50	10.50	0.00	0.00	10.50	10.50
cycles	7.50	7.50	7.50	7.50	7.50	7.50	16.75	16.75	16.75	16.75	10.50	10.50	0.00	0.00	10.50	10.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.88
Dispatch	16.75
Overall L1	16.75

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.75 cycles. At this rate:

8% of peak load performance is reached (21.73 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (10.03 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40eaa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
MOVSXD (%R10,%R12,4),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
TEST %EDI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40ee88 <advanceVelocity._omp_fn.0+0x448>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x20(%R11),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA (%RDI,%RDI,2),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x18(,%RBX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV 0x20(%R9),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%R9),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV $0xaaaaaaaaaaaaaab,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R9,%RDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
INC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RBX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 40ecaa <advanceVelocity._omp_fn.0+0x26a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40ec6a <advanceVelocity._omp_fn.0+0x22a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x2,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40ec33 <advanceVelocity._omp_fn.0+0x1f3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x3,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40ebfc <advanceVelocity._omp_fn.0+0x1bc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x4,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40ebc5 <advanceVelocity._omp_fn.0+0x185>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x5,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40eb8e <advanceVelocity._omp_fn.0+0x14e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x6,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40eb57 <advanceVelocity._omp_fn.0+0x117>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VMOVSD (%RCX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RSI),%XMM0,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM1,-0x18(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RCX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%RSI),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x10(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RCX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%RSI),%XMM0,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,-0x8(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RSI),%XMM0,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM4,-0x18(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RCX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%RSI),%XMM0,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,-0x10(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RCX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%RSI),%XMM0,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM6,-0x8(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RSI),%XMM0,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM7,-0x18(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RCX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%RSI),%XMM0,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM8,-0x10(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RCX),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%RSI),%XMM0,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM9,-0x8(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RSI),%XMM0,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM10,-0x18(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RCX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%RSI),%XMM0,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM11,-0x10(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RCX),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%RSI),%XMM0,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM12,-0x8(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RSI),%XMM0,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM13,-0x18(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RCX),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%RSI),%XMM0,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM14,-0x10(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RCX),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%RSI),%XMM0,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM15,-0x8(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RSI),%XMM0,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM1,-0x18(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RCX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%RSI),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x10(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RCX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%RSI),%XMM0,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,-0x8(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RSI),%XMM0,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,-0x18(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x8(%RCX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%RSI),%XMM0,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,-0x10(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x10(%RCX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x8(%RSI),%XMM0,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM6,-0x8(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40ee88 <advanceVelocity._omp_fn.0+0x448>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x600,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JG 40eaa0 <advanceVelocity._omp_fn.0+0x60>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A

Function	advanceVelocity._omp_fn.0
Source file and lines	timestep.c:74-78
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74-78.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 16.75 to 13.88 cycles (1.21x speedup).

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

FMA

Detected 21 FMA (fused multiply-add) operations.

Type of elements and instruction set

21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 42 FP arithmetical operations:

21: addition or subtraction (all inside FMA instructions)
21: multiply (all inside FMA instructions)

The binary loop is loading 364 bytes (45 double precision FP elements). The binary loop is storing 168 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	112
nb uops	111
loop length	541
used x86 registers	11
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.88 cycles
front end	13.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.50	7.50	7.50	7.50	7.50	7.50	16.75	16.75	16.75	16.75	10.50	10.50	0.00	0.00	10.50	10.50
cycles	7.50	7.50	7.50	7.50	7.50	7.50	16.75	16.75	16.75	16.75	10.50	10.50	0.00	0.00	10.50	10.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.88
Dispatch	16.75
Overall L1	16.75

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.75 cycles. At this rate:

8% of peak load performance is reached (21.73 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (10.03 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40eaa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
MOVSXD (%R10,%R12,4),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
TEST %EDI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40ee88 <advanceVelocity._omp_fn.0+0x448>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x20(%R11),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA (%RDI,%RDI,2),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x18(,%RBX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV 0x20(%R9),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%R9),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV $0xaaaaaaaaaaaaaab,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R9,%RDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
INC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RBX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 40ecaa <advanceVelocity._omp_fn.0+0x26a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40ec6a <advanceVelocity._omp_fn.0+0x22a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x2,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40ec33 <advanceVelocity._omp_fn.0+0x1f3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x3,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40ebfc <advanceVelocity._omp_fn.0+0x1bc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x4,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40ebc5 <advanceVelocity._omp_fn.0+0x185>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x5,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40eb8e <advanceVelocity._omp_fn.0+0x14e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x6,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40eb57 <advanceVelocity._omp_fn.0+0x117>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VMOVSD (%RCX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RSI),%XMM0,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM1,-0x18(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RCX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%RSI),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x10(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RCX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%RSI),%XMM0,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,-0x8(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RSI),%XMM0,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM4,-0x18(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RCX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%RSI),%XMM0,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,-0x10(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RCX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%RSI),%XMM0,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM6,-0x8(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RSI),%XMM0,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM7,-0x18(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RCX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%RSI),%XMM0,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM8,-0x10(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RCX),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%RSI),%XMM0,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM9,-0x8(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RSI),%XMM0,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM10,-0x18(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RCX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%RSI),%XMM0,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM11,-0x10(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RCX),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%RSI),%XMM0,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM12,-0x8(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RSI),%XMM0,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM13,-0x18(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RCX),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%RSI),%XMM0,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM14,-0x10(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RCX),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%RSI),%XMM0,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM15,-0x8(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RSI),%XMM0,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM1,-0x18(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RCX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%RSI),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x10(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RCX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%RSI),%XMM0,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,-0x8(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RSI),%XMM0,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,-0x18(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x8(%RCX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%RSI),%XMM0,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,-0x10(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x10(%RCX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x8(%RSI),%XMM0,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM6,-0x8(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40ee88 <advanceVelocity._omp_fn.0+0x448>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x600,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JG 40eaa0 <advanceVelocity._omp_fn.0+0x60>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code