OV - exec - Loop 97

	Loop Id: 97	Module: exec	Source: timestep.c:88-94	Coverage: 0.20%

0x40e7c0 MOVSXD	(%R10),%RSI

0x40e7c3 TEST	%ESI,%ESI

0x40e7c5 JLE	40ea10

0x40e7cb MOV	0x20(%R13),%R12

0x40e7cf ADD	%R9,%RSI

0x40e7d2 MOVSXD	%R9D,%RCX

0x40e7d5 MOV	0x28(%R13),%RBX

0x40e7d9 MOV	0x10(%R12),%R8

0x40e7de MOV	0x18(%R12),%RAX

0x40e7e3 MOV	0x20(%R12),%RDX

0x40e7e8 LEA	(%R8,%RCX,4),%RCX

0x40e7ec LEA	(%R8,%RSI,4),%R8

0x40e7f0 ADD	%RDI,%RAX

0x40e7f3 ADD	%RDI,%RDX

0x40e7f6 MOV	%R8,%RSI

0x40e7f9 SUB	%RCX,%RSI

0x40e7fc SUB	$0x4,%RSI

0x40e800 SHR	$0x2,%RSI

0x40e804 INC	%RSI

0x40e807 AND	$0x3,%ESI

0x40e80a JE	40e903

0x40e810 CMP	$0x1,%RSI

0x40e814 JE	40e8b1

0x40e81a CMP	$0x2,%RSI

0x40e81e JE	40e869

0x40e820 MOVSXD	(%RCX),%R12

0x40e823 VMULSD	(%RDX),%XMM0,%XMM3

0x40e827 ADD	$0x4,%RCX

0x40e82b ADD	$0x18,%RAX

0x40e82f ADD	$0x18,%RDX

0x40e833 SAL	$0x4,%R12

0x40e837 VDIVSD	0x8(%RBX,%R12,1),%XMM2,%XMM1

0x40e83e VFMADD213SD	-0x18(%RAX),%XMM1,%XMM3

0x40e844 VMOVSD	%XMM3,-0x18(%RAX)

0x40e849 VMULSD	-0x10(%RDX),%XMM0,%XMM4

0x40e84e VFMADD213SD	-0x10(%RAX),%XMM1,%XMM4

0x40e854 VMOVSD	%XMM4,-0x10(%RAX)

0x40e859 VMULSD	-0x8(%RDX),%XMM0,%XMM5

0x40e85e VFMADD213SD	-0x8(%RAX),%XMM5,%XMM1

0x40e864 VMOVSD	%XMM1,-0x8(%RAX)

0x40e869 MOVSXD	(%RCX),%RSI

0x40e86c VMULSD	(%RDX),%XMM0,%XMM7

0x40e870 ADD	$0x4,%RCX

0x40e874 ADD	$0x18,%RAX

0x40e878 ADD	$0x18,%RDX

0x40e87c SAL	$0x4,%RSI

0x40e880 VDIVSD	0x8(%RBX,%RSI,1),%XMM2,%XMM6

0x40e886 VFMADD213SD	-0x18(%RAX),%XMM6,%XMM7

0x40e88c VMOVSD	%XMM7,-0x18(%RAX)

0x40e891 VMULSD	-0x10(%RDX),%XMM0,%XMM8

0x40e896 VFMADD213SD	-0x10(%RAX),%XMM6,%XMM8

0x40e89c VMOVSD	%XMM8,-0x10(%RAX)

0x40e8a1 VMULSD	-0x8(%RDX),%XMM0,%XMM9

0x40e8a6 VFMADD213SD	-0x8(%RAX),%XMM9,%XMM6

0x40e8ac VMOVSD	%XMM6,-0x8(%RAX)

0x40e8b1 MOVSXD	(%RCX),%R12

0x40e8b4 ADD	$0x4,%RCX

0x40e8b8 VMULSD	(%RDX),%XMM0,%XMM11

0x40e8bc ADD	$0x18,%RAX

0x40e8c0 ADD	$0x18,%RDX

0x40e8c4 SAL	$0x4,%R12

0x40e8c8 VDIVSD	0x8(%RBX,%R12,1),%XMM2,%XMM10

0x40e8cf VFMADD213SD	-0x18(%RAX),%XMM10,%XMM11

0x40e8d5 VMOVSD	%XMM11,-0x18(%RAX)

0x40e8da VMULSD	-0x10(%RDX),%XMM0,%XMM12

0x40e8df VFMADD213SD	-0x10(%RAX),%XMM10,%XMM12

0x40e8e5 VMOVSD	%XMM12,-0x10(%RAX)

0x40e8ea VMULSD	-0x8(%RDX),%XMM0,%XMM13

0x40e8ef VFMADD213SD	-0x8(%RAX),%XMM13,%XMM10

0x40e8f5 VMOVSD	%XMM10,-0x8(%RAX)

0x40e8fa CMP	%RCX,%R8

0x40e8fd JE	40ea10

  (98) 0x40e903 MOVSXD	(%RCX),%RSI

  (98) 0x40e906 MOVSXD	0x4(%RCX),%R12

  (98) 0x40e90a VMULSD	(%RDX),%XMM0,%XMM15

  (98) 0x40e90e ADD	$0x10,%RCX

  (98) 0x40e912 ADD	$0x60,%RAX

  (98) 0x40e916 ADD	$0x60,%RDX

  (98) 0x40e91a SAL	$0x4,%RSI

  (98) 0x40e91e VDIVSD	0x8(%RBX,%RSI,1),%XMM2,%XMM14

  (98) 0x40e924 MOVSXD	-0x8(%RCX),%RSI

  (98) 0x40e928 VFMADD213SD	-0x60(%RAX),%XMM14,%XMM15

  (98) 0x40e92e VMOVSD	%XMM15,-0x60(%RAX)

  (98) 0x40e933 VMULSD	-0x58(%RDX),%XMM0,%XMM1

  (98) 0x40e938 VFMADD213SD	-0x58(%RAX),%XMM14,%XMM1

  (98) 0x40e93e VMOVSD	%XMM1,-0x58(%RAX)

  (98) 0x40e943 VMULSD	-0x50(%RDX),%XMM0,%XMM3

  (98) 0x40e948 SAL	$0x4,%R12

  (98) 0x40e94c VFMADD213SD	-0x50(%RAX),%XMM3,%XMM14

  (98) 0x40e952 VMOVSD	%XMM14,-0x50(%RAX)

  (98) 0x40e957 VMULSD	-0x48(%RDX),%XMM0,%XMM5

  (98) 0x40e95c VDIVSD	0x8(%RBX,%R12,1),%XMM2,%XMM4

  (98) 0x40e963 VFMADD213SD	-0x48(%RAX),%XMM4,%XMM5

  (98) 0x40e969 VMOVSD	%XMM5,-0x48(%RAX)

  (98) 0x40e96e VMULSD	-0x40(%RDX),%XMM0,%XMM6

  (98) 0x40e973 SAL	$0x4,%RSI

  (98) 0x40e977 VFMADD213SD	-0x40(%RAX),%XMM4,%XMM6

  (98) 0x40e97d VMOVSD	%XMM6,-0x40(%RAX)

  (98) 0x40e982 VMULSD	-0x38(%RDX),%XMM0,%XMM7

  (98) 0x40e987 VFMADD213SD	-0x38(%RAX),%XMM7,%XMM4

  (98) 0x40e98d VMOVSD	%XMM4,-0x38(%RAX)

  (98) 0x40e992 VMULSD	-0x30(%RDX),%XMM0,%XMM9

  (98) 0x40e997 VDIVSD	0x8(%RBX,%RSI,1),%XMM2,%XMM8

  (98) 0x40e99d VFMADD213SD	-0x30(%RAX),%XMM8,%XMM9

  (98) 0x40e9a3 VMOVSD	%XMM9,-0x30(%RAX)

  (98) 0x40e9a8 VMULSD	-0x28(%RDX),%XMM0,%XMM10

  (98) 0x40e9ad VFMADD213SD	-0x28(%RAX),%XMM8,%XMM10

  (98) 0x40e9b3 VMOVSD	%XMM10,-0x28(%RAX)

  (98) 0x40e9b8 VMULSD	-0x20(%RDX),%XMM0,%XMM11

  (98) 0x40e9bd VFMADD213SD	-0x20(%RAX),%XMM11,%XMM8

  (98) 0x40e9c3 VMOVSD	%XMM8,-0x20(%RAX)

  (98) 0x40e9c8 MOVSXD	-0x4(%RCX),%R12

  (98) 0x40e9cc VMULSD	-0x18(%RDX),%XMM0,%XMM13

  (98) 0x40e9d1 SAL	$0x4,%R12

  (98) 0x40e9d5 VDIVSD	0x8(%RBX,%R12,1),%XMM2,%XMM12

  (98) 0x40e9dc VFMADD213SD	-0x18(%RAX),%XMM12,%XMM13

  (98) 0x40e9e2 VMOVSD	%XMM13,-0x18(%RAX)

  (98) 0x40e9e7 VMULSD	-0x10(%RDX),%XMM0,%XMM14

  (98) 0x40e9ec VFMADD213SD	-0x10(%RAX),%XMM12,%XMM14

  (98) 0x40e9f2 VMOVSD	%XMM14,-0x10(%RAX)

  (98) 0x40e9f7 VMULSD	-0x8(%RDX),%XMM0,%XMM15

  (98) 0x40e9fc VFMADD213SD	-0x8(%RAX),%XMM15,%XMM12

  (98) 0x40ea02 VMOVSD	%XMM12,-0x8(%RAX)

  (98) 0x40ea07 CMP	%RCX,%R8

  (98) 0x40ea0a JNE	40e903

0x40ea10 ADD	$0x600,%RDI

0x40ea17 ADD	$0x4,%R10

0x40ea1b ADD	$0x40,%R9

0x40ea1f CMP	%R11,%RDI

0x40ea22 JNE	40e7c0

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 88 - 94

--------------------------------------------------------------------------------

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

94:          s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass;

Coverage (%)	Name	Source Location	Module
○100.00	gomp_thread_start	team.c:130	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.54
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P10, P11,
Function	advancePosition._omp_fn.0
Source	timestep.c:88-94
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	7.78
CQA cycles if fully vectorized	1.50
Front-end cycles	9.50
P0 cycles	6.67
P1 cycles	6.67
P2 cycles	6.67
P3 cycles	6.67
P4 cycles	6.67
P5 cycles	6.67
P6 cycles	9.75
P7 cycles	9.75
P8 cycles	9.75
P9 cycles	9.75
P10 cycles	10.50
P11 cycles	10.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.50
P15 cycles	4.50
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	77.00
Nb uops	76.00
Nb loads	30.00
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	2.50
Nb FLOP add-sub	0.00
Nb FLOP mul	9.00
Nb FLOP fma	9.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.67
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	72.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.32
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	10.94

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.54
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P10, P11,
Function	advancePosition._omp_fn.0
Source	timestep.c:88-94
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	7.78
CQA cycles if fully vectorized	1.50
Front-end cycles	9.50
P0 cycles	6.67
P1 cycles	6.67
P2 cycles	6.67
P3 cycles	6.67
P4 cycles	6.67
P5 cycles	6.67
P6 cycles	9.75
P7 cycles	9.75
P8 cycles	9.75
P9 cycles	9.75
P10 cycles	10.50
P11 cycles	10.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.50
P15 cycles	4.50
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	77.00
Nb uops	76.00
Nb loads	30.00
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	2.50
Nb FLOP add-sub	0.00
Nb FLOP mul	9.00
Nb FLOP fma	9.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.67
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	72.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.32
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	10.94

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advancePosition._omp_fn.0
Source file and lines	timestep.c:88-94
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88-94.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.50 cycles (1.14x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

FMA

Detected 9 FMA (fused multiply-add) operations.

Type of elements and instruction set

21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 30 FP arithmetical operations:

9: addition or subtraction (all inside FMA instructions)
18: multiply (9 inside FMA instructions)
3: divide

The binary loop is loading 224 bytes (28 double precision FP elements). The binary loop is storing 72 bytes (9 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	77
nb uops	76
loop length	347
used x86 registers	12
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.67	6.67	6.67	6.67	6.67	6.67	9.75	9.75	9.75	9.75	10.50	10.50	0.00	0.00	4.50	4.50
cycles	6.67	6.67	6.67	6.67	6.67	6.67	9.75	9.75	9.75	9.75	10.50	10.50	0.00	0.00	4.50	4.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.50
Dispatch	10.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

7% of peak load performance is reached (18.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40e7c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
MOVSXD (%R10),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
TEST %ESI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40ea10 <advancePosition._omp_fn.0+0x2d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x20(%R13),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD %R9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %R9D,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%R13),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%R12),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%R12),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%R12),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA (%R8,%RCX,4),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R8,%RSI,4),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 40e903 <advancePosition._omp_fn.0+0x1c3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40e8b1 <advancePosition._omp_fn.0+0x171>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x2,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40e869 <advancePosition._omp_fn.0+0x129>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOVSXD (%RCX),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
VMULSD (%RDX),%XMM0,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADD $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%R12	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RBX,%R12,1),%XMM2,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	13	4	scal (12.5%)
VFMADD213SD -0x18(%RAX),%XMM1,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,-0x18(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD -0x10(%RDX),%XMM0,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
VFMADD213SD -0x10(%RAX),%XMM1,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,-0x10(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD -0x8(%RDX),%XMM0,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
VFMADD213SD -0x8(%RAX),%XMM5,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,-0x8(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSXD (%RCX),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
VMULSD (%RDX),%XMM0,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADD $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RBX,%RSI,1),%XMM2,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	13	4	scal (12.5%)
VFMADD213SD -0x18(%RAX),%XMM6,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM7,-0x18(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD -0x10(%RDX),%XMM0,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
VFMADD213SD -0x10(%RAX),%XMM6,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM8,-0x10(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD -0x8(%RDX),%XMM0,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
VFMADD213SD -0x8(%RAX),%XMM9,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM6,-0x8(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSXD (%RCX),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%RDX),%XMM0,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%R12	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RBX,%R12,1),%XMM2,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	13	4	scal (12.5%)
VFMADD213SD -0x18(%RAX),%XMM10,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM11,-0x18(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD -0x10(%RDX),%XMM0,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
VFMADD213SD -0x10(%RAX),%XMM10,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM12,-0x10(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD -0x8(%RDX),%XMM0,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
VFMADD213SD -0x8(%RAX),%XMM13,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM10,-0x8(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RCX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40ea10 <advancePosition._omp_fn.0+0x2d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
ADD $0x600,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x4,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R11,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 40e7c0 <advancePosition._omp_fn.0+0x80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A

Function	advancePosition._omp_fn.0
Source file and lines	timestep.c:88-94
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88-94.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

FMA

Detected 9 FMA (fused multiply-add) operations.

Type of elements and instruction set

21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 30 FP arithmetical operations:

9: addition or subtraction (all inside FMA instructions)
18: multiply (9 inside FMA instructions)
3: divide

The binary loop is loading 224 bytes (28 double precision FP elements). The binary loop is storing 72 bytes (9 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	77
nb uops	76
loop length	347
used x86 registers	12
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.67	6.67	6.67	6.67	6.67	6.67	9.75	9.75	9.75	9.75	10.50	10.50	0.00	0.00	4.50	4.50
cycles	6.67	6.67	6.67	6.67	6.67	6.67	9.75	9.75	9.75	9.75	10.50	10.50	0.00	0.00	4.50	4.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.50
Dispatch	10.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

7% of peak load performance is reached (18.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40e7c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
MOVSXD (%R10),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
TEST %ESI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40ea10 <advancePosition._omp_fn.0+0x2d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x20(%R13),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD %R9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %R9D,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%R13),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%R12),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%R12),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%R12),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA (%R8,%RCX,4),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R8,%RSI,4),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 40e903 <advancePosition._omp_fn.0+0x1c3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40e8b1 <advancePosition._omp_fn.0+0x171>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x2,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40e869 <advancePosition._omp_fn.0+0x129>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOVSXD (%RCX),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
VMULSD (%RDX),%XMM0,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADD $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%R12	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RBX,%R12,1),%XMM2,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	13	4	scal (12.5%)
VFMADD213SD -0x18(%RAX),%XMM1,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,-0x18(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD -0x10(%RDX),%XMM0,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
VFMADD213SD -0x10(%RAX),%XMM1,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,-0x10(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD -0x8(%RDX),%XMM0,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
VFMADD213SD -0x8(%RAX),%XMM5,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,-0x8(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSXD (%RCX),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
VMULSD (%RDX),%XMM0,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADD $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RBX,%RSI,1),%XMM2,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	13	4	scal (12.5%)
VFMADD213SD -0x18(%RAX),%XMM6,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM7,-0x18(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD -0x10(%RDX),%XMM0,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
VFMADD213SD -0x10(%RAX),%XMM6,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM8,-0x10(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD -0x8(%RDX),%XMM0,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
VFMADD213SD -0x8(%RAX),%XMM9,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM6,-0x8(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSXD (%RCX),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%RDX),%XMM0,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%R12	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RBX,%R12,1),%XMM2,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	13	4	scal (12.5%)
VFMADD213SD -0x18(%RAX),%XMM10,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM11,-0x18(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD -0x10(%RDX),%XMM0,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
VFMADD213SD -0x10(%RAX),%XMM10,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM12,-0x10(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD -0x8(%RDX),%XMM0,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
VFMADD213SD -0x8(%RAX),%XMM13,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM10,-0x8(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RCX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40ea10 <advancePosition._omp_fn.0+0x2d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
ADD $0x600,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x4,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R11,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 40e7c0 <advancePosition._omp_fn.0+0x80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code