OV - exec - Function advancePosition._omp

	Function: advancePosition._omp_fn.0	Module: exec	Source: timestep.c:85-94	Coverage (incl. loops): 1.40% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 85 - 94

--------------------------------------------------------------------------------

85:    #pragma omp parallel for

86:    for (int iBox=0; iBox<nBoxes; iBox++)

87:    {

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

94:          s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass;

0x40e740 PUSH	%RBP

0x40e741 MOV	%RSP,%RBP

0x40e744 PUSH	%R13

0x40e746 PUSH	%R12

0x40e748 PUSH	%RBX

0x40e749 SUB	$0x8,%RSP

0x40e74d MOV	%RDI,%RBX

0x40e750 CALL	4032d0 <omp_get_num_threads@plt>

0x40e755 MOV	%EAX,%R12D

0x40e758 CALL	403280 <omp_get_thread_num@plt>

0x40e75d MOV	%EAX,%ECX

0x40e75f MOV	0x10(%RBX),%EAX

0x40e762 CLTD

0x40e763 IDIV	%R12D

0x40e766 CMP	%EDX,%ECX

0x40e768 JL	40ea33

0x40e76e IMUL	%EAX,%ECX

0x40e771 ADD	%ECX,%EDX

0x40e773 LEA	(%RAX,%RDX,1),%ESI

0x40e776 CMP	%ESI,%EDX

0x40e778 JGE	40ea28

0x40e77e MOV	(%RBX),%R13

0x40e781 MOVSXD	%EDX,%R8

0x40e784 MOV	%EAX,%R11D

0x40e787 VMOVSD	0x8(%RBX),%XMM0

0x40e78c ADD	%R8,%R11

0x40e78f VMOVSD	0x33b9(%RIP),%XMM2

0x40e797 LEA	(%R11,%R11,2),%R11

0x40e79b SAL	$0x9,%R11

0x40e79f MOV	0x18(%R13),%RDI

0x40e7a3 MOV	0x78(%RDI),%R9

0x40e7a7 LEA	(%R8,%R8,2),%RDI

0x40e7ab SAL	$0x9,%RDI

0x40e7af LEA	(%R9,%R8,4),%R10

0x40e7b3 MOV	%R8,%R9

0x40e7b6 SAL	$0x6,%R9

0x40e7ba NOPW	(%RAX,%RAX,1)

(97) 0x40e7c0 MOVSXD	(%R10),%RSI

(97) 0x40e7c3 TEST	%ESI,%ESI

(97) 0x40e7c5 JLE	40ea10

(97) 0x40e7cb MOV	0x20(%R13),%R12

(97) 0x40e7cf ADD	%R9,%RSI

(97) 0x40e7d2 MOVSXD	%R9D,%RCX

(97) 0x40e7d5 MOV	0x28(%R13),%RBX

(97) 0x40e7d9 MOV	0x10(%R12),%R8

(97) 0x40e7de MOV	0x18(%R12),%RAX

(97) 0x40e7e3 MOV	0x20(%R12),%RDX

(97) 0x40e7e8 LEA	(%R8,%RCX,4),%RCX

(97) 0x40e7ec LEA	(%R8,%RSI,4),%R8

(97) 0x40e7f0 ADD	%RDI,%RAX

(97) 0x40e7f3 ADD	%RDI,%RDX

(97) 0x40e7f6 MOV	%R8,%RSI

(97) 0x40e7f9 SUB	%RCX,%RSI

(97) 0x40e7fc SUB	$0x4,%RSI

(97) 0x40e800 SHR	$0x2,%RSI

(97) 0x40e804 INC	%RSI

(97) 0x40e807 AND	$0x3,%ESI

(97) 0x40e80a JE	40e903

(97) 0x40e810 CMP	$0x1,%RSI

(97) 0x40e814 JE	40e8b1

(97) 0x40e81a CMP	$0x2,%RSI

(97) 0x40e81e JE	40e869

(97) 0x40e820 MOVSXD	(%RCX),%R12

(97) 0x40e823 VMULSD	(%RDX),%XMM0,%XMM3

(97) 0x40e827 ADD	$0x4,%RCX

(97) 0x40e82b ADD	$0x18,%RAX

(97) 0x40e82f ADD	$0x18,%RDX

(97) 0x40e833 SAL	$0x4,%R12

(97) 0x40e837 VDIVSD	0x8(%RBX,%R12,1),%XMM2,%XMM1

(97) 0x40e83e VFMADD213SD	-0x18(%RAX),%XMM1,%XMM3

(97) 0x40e844 VMOVSD	%XMM3,-0x18(%RAX)

(97) 0x40e849 VMULSD	-0x10(%RDX),%XMM0,%XMM4

(97) 0x40e84e VFMADD213SD	-0x10(%RAX),%XMM1,%XMM4

(97) 0x40e854 VMOVSD	%XMM4,-0x10(%RAX)

(97) 0x40e859 VMULSD	-0x8(%RDX),%XMM0,%XMM5

(97) 0x40e85e VFMADD213SD	-0x8(%RAX),%XMM5,%XMM1

(97) 0x40e864 VMOVSD	%XMM1,-0x8(%RAX)

(97) 0x40e869 MOVSXD	(%RCX),%RSI

(97) 0x40e86c VMULSD	(%RDX),%XMM0,%XMM7

(97) 0x40e870 ADD	$0x4,%RCX

(97) 0x40e874 ADD	$0x18,%RAX

(97) 0x40e878 ADD	$0x18,%RDX

(97) 0x40e87c SAL	$0x4,%RSI

(97) 0x40e880 VDIVSD	0x8(%RBX,%RSI,1),%XMM2,%XMM6

(97) 0x40e886 VFMADD213SD	-0x18(%RAX),%XMM6,%XMM7

(97) 0x40e88c VMOVSD	%XMM7,-0x18(%RAX)

(97) 0x40e891 VMULSD	-0x10(%RDX),%XMM0,%XMM8

(97) 0x40e896 VFMADD213SD	-0x10(%RAX),%XMM6,%XMM8

(97) 0x40e89c VMOVSD	%XMM8,-0x10(%RAX)

(97) 0x40e8a1 VMULSD	-0x8(%RDX),%XMM0,%XMM9

(97) 0x40e8a6 VFMADD213SD	-0x8(%RAX),%XMM9,%XMM6

(97) 0x40e8ac VMOVSD	%XMM6,-0x8(%RAX)

(97) 0x40e8b1 MOVSXD	(%RCX),%R12

(97) 0x40e8b4 ADD	$0x4,%RCX

(97) 0x40e8b8 VMULSD	(%RDX),%XMM0,%XMM11

(97) 0x40e8bc ADD	$0x18,%RAX

(97) 0x40e8c0 ADD	$0x18,%RDX

(97) 0x40e8c4 SAL	$0x4,%R12

(97) 0x40e8c8 VDIVSD	0x8(%RBX,%R12,1),%XMM2,%XMM10

(97) 0x40e8cf VFMADD213SD	-0x18(%RAX),%XMM10,%XMM11

(97) 0x40e8d5 VMOVSD	%XMM11,-0x18(%RAX)

(97) 0x40e8da VMULSD	-0x10(%RDX),%XMM0,%XMM12

(97) 0x40e8df VFMADD213SD	-0x10(%RAX),%XMM10,%XMM12

(97) 0x40e8e5 VMOVSD	%XMM12,-0x10(%RAX)

(97) 0x40e8ea VMULSD	-0x8(%RDX),%XMM0,%XMM13

(97) 0x40e8ef VFMADD213SD	-0x8(%RAX),%XMM13,%XMM10

(97) 0x40e8f5 VMOVSD	%XMM10,-0x8(%RAX)

(97) 0x40e8fa CMP	%RCX,%R8

(97) 0x40e8fd JE	40ea10

  (98) 0x40e903 MOVSXD	(%RCX),%RSI

  (98) 0x40e906 MOVSXD	0x4(%RCX),%R12

  (98) 0x40e90a VMULSD	(%RDX),%XMM0,%XMM15

  (98) 0x40e90e ADD	$0x10,%RCX

  (98) 0x40e912 ADD	$0x60,%RAX

  (98) 0x40e916 ADD	$0x60,%RDX

  (98) 0x40e91a SAL	$0x4,%RSI

  (98) 0x40e91e VDIVSD	0x8(%RBX,%RSI,1),%XMM2,%XMM14

  (98) 0x40e924 MOVSXD	-0x8(%RCX),%RSI

  (98) 0x40e928 VFMADD213SD	-0x60(%RAX),%XMM14,%XMM15

  (98) 0x40e92e VMOVSD	%XMM15,-0x60(%RAX)

  (98) 0x40e933 VMULSD	-0x58(%RDX),%XMM0,%XMM1

  (98) 0x40e938 VFMADD213SD	-0x58(%RAX),%XMM14,%XMM1

  (98) 0x40e93e VMOVSD	%XMM1,-0x58(%RAX)

  (98) 0x40e943 VMULSD	-0x50(%RDX),%XMM0,%XMM3

  (98) 0x40e948 SAL	$0x4,%R12

  (98) 0x40e94c VFMADD213SD	-0x50(%RAX),%XMM3,%XMM14

  (98) 0x40e952 VMOVSD	%XMM14,-0x50(%RAX)

  (98) 0x40e957 VMULSD	-0x48(%RDX),%XMM0,%XMM5

  (98) 0x40e95c VDIVSD	0x8(%RBX,%R12,1),%XMM2,%XMM4

  (98) 0x40e963 VFMADD213SD	-0x48(%RAX),%XMM4,%XMM5

  (98) 0x40e969 VMOVSD	%XMM5,-0x48(%RAX)

  (98) 0x40e96e VMULSD	-0x40(%RDX),%XMM0,%XMM6

  (98) 0x40e973 SAL	$0x4,%RSI

  (98) 0x40e977 VFMADD213SD	-0x40(%RAX),%XMM4,%XMM6

  (98) 0x40e97d VMOVSD	%XMM6,-0x40(%RAX)

  (98) 0x40e982 VMULSD	-0x38(%RDX),%XMM0,%XMM7

  (98) 0x40e987 VFMADD213SD	-0x38(%RAX),%XMM7,%XMM4

  (98) 0x40e98d VMOVSD	%XMM4,-0x38(%RAX)

  (98) 0x40e992 VMULSD	-0x30(%RDX),%XMM0,%XMM9

  (98) 0x40e997 VDIVSD	0x8(%RBX,%RSI,1),%XMM2,%XMM8

  (98) 0x40e99d VFMADD213SD	-0x30(%RAX),%XMM8,%XMM9

  (98) 0x40e9a3 VMOVSD	%XMM9,-0x30(%RAX)

  (98) 0x40e9a8 VMULSD	-0x28(%RDX),%XMM0,%XMM10

  (98) 0x40e9ad VFMADD213SD	-0x28(%RAX),%XMM8,%XMM10

  (98) 0x40e9b3 VMOVSD	%XMM10,-0x28(%RAX)

  (98) 0x40e9b8 VMULSD	-0x20(%RDX),%XMM0,%XMM11

  (98) 0x40e9bd VFMADD213SD	-0x20(%RAX),%XMM11,%XMM8

  (98) 0x40e9c3 VMOVSD	%XMM8,-0x20(%RAX)

  (98) 0x40e9c8 MOVSXD	-0x4(%RCX),%R12

  (98) 0x40e9cc VMULSD	-0x18(%RDX),%XMM0,%XMM13

  (98) 0x40e9d1 SAL	$0x4,%R12

  (98) 0x40e9d5 VDIVSD	0x8(%RBX,%R12,1),%XMM2,%XMM12

  (98) 0x40e9dc VFMADD213SD	-0x18(%RAX),%XMM12,%XMM13

  (98) 0x40e9e2 VMOVSD	%XMM13,-0x18(%RAX)

  (98) 0x40e9e7 VMULSD	-0x10(%RDX),%XMM0,%XMM14

  (98) 0x40e9ec VFMADD213SD	-0x10(%RAX),%XMM12,%XMM14

  (98) 0x40e9f2 VMOVSD	%XMM14,-0x10(%RAX)

  (98) 0x40e9f7 VMULSD	-0x8(%RDX),%XMM0,%XMM15

  (98) 0x40e9fc VFMADD213SD	-0x8(%RAX),%XMM15,%XMM12

  (98) 0x40ea02 VMOVSD	%XMM12,-0x8(%RAX)

  (98) 0x40ea07 CMP	%RCX,%R8

  (98) 0x40ea0a JNE	40e903

(97) 0x40ea10 ADD	$0x600,%RDI

(97) 0x40ea17 ADD	$0x4,%R10

(97) 0x40ea1b ADD	$0x40,%R9

(97) 0x40ea1f CMP	%R11,%RDI

(97) 0x40ea22 JNE	40e7c0

0x40ea28 ADD	$0x8,%RSP

0x40ea2c POP	%RBX

0x40ea2d POP	%R12

0x40ea2f POP	%R13

0x40ea31 POP	%RBP

0x40ea32 RET

0x40ea33 INC	%EAX

0x40ea35 XOR	%EDX,%EDX

0x40ea37 JMP	40e76e

0x40ea3c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○99.62	gomp_thread_start	team.c:130	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_10

Source file and lines	timestep.c:85-94
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 0.88 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.00 to 0.40 cycles (15.06x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86
omp_get_thread_num@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes.

General properties

nb instructions	47
nb uops	47
loop length	152
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.88 cycles
front end	5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.00	4.00	4.00	4.00	4.00	4.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.00	4.00	4.00	4.00	4.00	4.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	5.88
Dispatch	4.00
DIV/SQRT	6.00
Overall L1	6.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

2% of peak load performance is reached (7.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40e740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 4032d0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403280 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x10(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40ea33 <advancePosition._omp_fn.0+0x2f3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40ea28 <advancePosition._omp_fn.0+0x2e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV (%RBX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %EDX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x8(%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x33b9(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%R11,%R11,2),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x9,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV 0x18(%R13),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x78(%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R8,%R8,2),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x9,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R9,%R8,4),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x6,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
ADD $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 40e76e <advancePosition._omp_fn.0+0x2e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_10

Source file and lines	timestep.c:85-94
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 0.88 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86
omp_get_thread_num@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes.

General properties

nb instructions	47
nb uops	47
loop length	152
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.88 cycles
front end	5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.00	4.00	4.00	4.00	4.00	4.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.00	4.00	4.00	4.00	4.00	4.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	5.88
Dispatch	4.00
DIV/SQRT	6.00
Overall L1	6.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

2% of peak load performance is reached (7.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40e740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 4032d0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403280 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x10(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40ea33 <advancePosition._omp_fn.0+0x2f3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40ea28 <advancePosition._omp_fn.0+0x2e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV (%RBX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %EDX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x8(%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x33b9(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%R11,%R11,2),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x9,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV 0x18(%R13),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x78(%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R8,%R8,2),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x9,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R9,%R8,4),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x6,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
ADD $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 40e76e <advancePosition._omp_fn.0+0x2e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

Name	Coverage (%)	Time (s)
▼advancePosition._omp_fn.0–	1.40	0.10
▼Loop 97 - timestep.c:88-94 - exec–	0.20	0.01
○Loop 98 - timestep.c:88-94 - exec	1.20	0.05

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code