OV - exec - Function ljForce._omp

	Function: ljForce._omp_fn.1	Module: exec	Source: ljForce.c:172-216 [...]	Coverage (incl. loops): 64.19% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 172 - 216

--------------------------------------------------------------------------------

172:    #pragma omp parallel for reduction(+:ePot)

173:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

174:    {

175:       int nIBox = s->boxes->nAtoms[iBox];

176:

177:       // loop over neighbors of iBox

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

0x40b7e0 PUSH	%RBP

0x40b7e1 MOV	%RSP,%RBP

0x40b7e4 PUSH	%R15

0x40b7e6 PUSH	%R14

0x40b7e8 PUSH	%R13

0x40b7ea PUSH	%R12

0x40b7ec PUSH	%RBX

0x40b7ed MOV	%RDI,%RBX

0x40b7f0 SUB	$0x48,%RSP

0x40b7f4 MOV	(%RDI),%RAX

0x40b7f7 MOV	0x18(%RAX),%R12

0x40b7fb MOV	%RAX,-0x50(%RBP)

0x40b7ff CALL	4032d0 <omp_get_num_threads@plt>

0x40b804 MOV	%EAX,%R13D

0x40b807 CALL	403280 <omp_get_thread_num@plt>

0x40b80c MOV	%EAX,%ECX

0x40b80e MOV	0xc(%R12),%EAX

0x40b813 CLTD

0x40b814 IDIV	%R13D

0x40b817 CMP	%EDX,%ECX

0x40b819 JL	40be35

0x40b81f IMUL	%EAX,%ECX

0x40b822 ADD	%EDX,%ECX

0x40b824 LEA	(%RAX,%RCX,1),%R11D

0x40b828 CMP	%R11D,%ECX

0x40b82b JGE	40be4b

0x40b831 MOV	0x30(%RBX),%R9D

0x40b835 MOVSXD	%ECX,%RSI

0x40b838 MOV	%ECX,%R10D

0x40b83b VMOVSD	0x6375(%RIP),%XMM10

0x40b843 MOV	%RSI,%R8

0x40b846 MOV	0x78(%R12),%RDI

0x40b84b VMOVSD	0x20(%RBX),%XMM11

0x40b850 VMOVSD	0x18(%RBX),%XMM12

0x40b855 NOT	%R8

0x40b858 VMOVSD	0x10(%RBX),%XMM3

0x40b85d VMULSD	0x8(%RBX),%XMM10,%XMM10

0x40b862 ADD	%R11D,%R8D

0x40b865 SAL	$0x6,%R10D

0x40b869 MOVSXD	%R9D,%R14

0x40b86c AND	$0x7,%R8D

0x40b870 SAL	$0x2,%R14

0x40b874 TEST	%R9D,%R9D

0x40b877 JLE	40be51

0x40b87d MOV	(%RDI,%RSI,4),%R15D

0x40b881 MOV	0x80(%R12),%R8

0x40b889 MOV	%RBX,-0x60(%RBP)

0x40b88d VMOVQ	%RDI,%XMM22

0x40b893 MOV	%R10D,%ECX

0x40b896 MOV	%R11D,%EBX

0x40b899 MOV	%R14,%R12

0x40b89c VXORPD	%XMM7,%XMM7,%XMM7

0x40b8a0 VMOVSD	0x62a8(%RIP),%XMM9

0x40b8a8 VMOVSD	0x62c8(%RIP),%XMM8

0x40b8b0 VMOVSD	0x6308(%RIP),%XMM14

0x40b8b8 VMOVSD	0x6308(%RIP),%XMM13

(86) 0x40b8c0 MOV	(%R8,%RSI,8),%R9

(86) 0x40b8c4 MOV	%ESI,%R13D

(86) 0x40b8c7 LEA	(%R15,%RCX,1),%EDX

(86) 0x40b8cb MOV	%ECX,%EAX

(86) 0x40b8cd VMOVD	%R15D,%XMM5

(86) 0x40b8d2 VMOVDQA64	%XMM22,%XMM4

(86) 0x40b8d8 MOV	%EDX,%ECX

(86) 0x40b8da MOV	%RSI,-0x68(%RBP)

(86) 0x40b8de SAL	$0x6,%R13D

(86) 0x40b8e2 MOV	%R12,-0x70(%RBP)

(86) 0x40b8e6 VMOVQ	%R8,%XMM21

(86) 0x40b8ec MOVSXD	%R13D,%R10

(86) 0x40b8ef MOV	%EBX,%R13D

(86) 0x40b8f2 LEA	(%R12,%R9,1),%R14

(86) 0x40b8f6 LEA	(,%R10,8),%R11

(86) 0x40b8fe MOV	%R11,-0x48(%RBP)

(86) 0x40b902 MOV	%R14,-0x58(%RBP)

  (85) 0x40b906 MOV	(%R9),%R15D

  (85) 0x40b909 TEST	%R15D,%R15D

  (85) 0x40b90c JS	40bf30

  (85) 0x40b912 MOVSXD	%R15D,%RBX

  (85) 0x40b915 VMOVQ	%XMM4,%RSI

  (85) 0x40b91a VMOVD	%XMM5,%EDI

  (85) 0x40b91e MOV	(%RSI,%RBX,4),%R8D

  (85) 0x40b922 TEST	%EDI,%EDI

  (85) 0x40b924 JLE	40ba14

  (85) 0x40b92a MOV	%EAX,%R10D

  (85) 0x40b92d LEA	(%RBX,%RBX,2),%RDX

  (85) 0x40b931 MOV	%EAX,%R14D

  (85) 0x40b934 MOV	-0x48(%RBP),%RBX

  (85) 0x40b938 NOT	%R10D

  (85) 0x40b93b SAL	$0x6,%R15D

  (85) 0x40b93f ADD	%ECX,%R10D

  (85) 0x40b942 LEA	(%R8,%R15,1),%R12D

  (85) 0x40b946 SAL	$0x9,%RDX

  (85) 0x40b94a AND	$0x7,%R10D

  (85) 0x40b94e TEST	%R8D,%R8D

  (85) 0x40b951 JG	40ba54

  (85) 0x40b957 MOV	-0x48(%RBP),%R11

  (85) 0x40b95b LEA	0x1(%RAX),%R14D

  (85) 0x40b95f LEA	0x8(%R11),%RBX

  (85) 0x40b963 CMP	%ECX,%R14D

  (85) 0x40b966 JGE	40ba14

  (85) 0x40b96c TEST	%R10D,%R10D

  (85) 0x40b96f JE	40ba02

  (85) 0x40b975 CMP	$0x1,%R10D

  (85) 0x40b979 JE	40b9f1

  (85) 0x40b97b CMP	$0x2,%R10D

  (85) 0x40b97f JE	40b9e5

  (85) 0x40b981 CMP	$0x3,%R10D

  (85) 0x40b985 JE	40b9d9

  (85) 0x40b987 CMP	$0x4,%R10D

  (85) 0x40b98b JE	40b9c9

  (85) 0x40b98d CMP	$0x5,%R10D

  (85) 0x40b991 JE	40b9b9

  (85) 0x40b993 CMP	$0x6,%R10D

  (85) 0x40b997 JE	40b9a9

  (85) 0x40b999 TEST	%R8D,%R8D

  (85) 0x40b99c JG	40ba54

  (85) 0x40b9a2 INC	%R14D

  (85) 0x40b9a5 ADD	$0x8,%RBX

  (85) 0x40b9a9 TEST	%R8D,%R8D

  (85) 0x40b9ac JG	40ba54

  (85) 0x40b9b2 INC	%R14D

  (85) 0x40b9b5 ADD	$0x8,%RBX

  (85) 0x40b9b9 TEST	%R8D,%R8D

  (85) 0x40b9bc JG	40ba54

  (85) 0x40b9c2 INC	%R14D

  (85) 0x40b9c5 ADD	$0x8,%RBX

  (85) 0x40b9c9 TEST	%R8D,%R8D

  (85) 0x40b9cc JG	40ba54

  (85) 0x40b9d2 INC	%R14D

  (85) 0x40b9d5 ADD	$0x8,%RBX

  (85) 0x40b9d9 TEST	%R8D,%R8D

  (85) 0x40b9dc JG	40ba54

  (85) 0x40b9de INC	%R14D

  (85) 0x40b9e1 ADD	$0x8,%RBX

  (85) 0x40b9e5 TEST	%R8D,%R8D

  (85) 0x40b9e8 JG	40ba54

  (85) 0x40b9ea INC	%R14D

  (85) 0x40b9ed ADD	$0x8,%RBX

  (85) 0x40b9f1 TEST	%R8D,%R8D

  (85) 0x40b9f4 JG	40ba54

  (85) 0x40b9f6 INC	%R14D

  (85) 0x40b9f9 ADD	$0x8,%RBX

  (85) 0x40b9fd CMP	%ECX,%R14D

  (85) 0x40ba00 JGE	40ba14

    (89) 0x40ba02 TEST	%R8D,%R8D

    (89) 0x40ba05 JG	40ba54

    (89) 0x40ba07 ADD	$0x8,%R14D

    (89) 0x40ba0b ADD	$0x40,%RBX

    (89) 0x40ba0f CMP	%ECX,%R14D

    (89) 0x40ba12 JL	40ba02

  (85) 0x40ba14 ADD	$0x4,%R9

  (85) 0x40ba18 CMP	%R9,-0x58(%RBP)

  (85) 0x40ba1c JNE	40b906

(86) 0x40ba22 MOV	-0x68(%RBP),%RSI

(86) 0x40ba26 MOV	%EAX,%ECX

(86) 0x40ba28 MOV	-0x70(%RBP),%R12

(86) 0x40ba2c MOV	%R13D,%EBX

(86) 0x40ba2f VMOVQ	%XMM21,%R8

(86) 0x40ba35 ADD	$0x40,%ECX

(86) 0x40ba38 INC	%RSI

(86) 0x40ba3b CMP	%ESI,%R13D

(86) 0x40ba3e JLE	40bdf9

(86) 0x40ba44 VMOVQ	%XMM22,%R13

(86) 0x40ba4a MOV	(%R13,%RSI,4),%R15D

(86) 0x40ba4f JMP	40b8c0

  (85) 0x40ba54 MOV	-0x50(%RBP),%RSI

  (85) 0x40ba58 MOV	%EAX,-0x34(%RBP)

  (85) 0x40ba5b MOV	%RDX,%RDI

  (85) 0x40ba5e MOV	%R15D,%EAX

  (85) 0x40ba61 MOV	%R14D,%R15D

  (85) 0x40ba64 MOV	%RBX,%R14

  (85) 0x40ba67 VXORPD	%XMM6,%XMM6,%XMM6

  (85) 0x40ba6b MOV	%R9,-0x40(%RBP)

  (85) 0x40ba6f MOV	0x20(%RSI),%R8

  (85) 0x40ba73 NOPW	%CS:(%RAX,%RAX,1)

  (85) 0x40ba7e XCHG	%AX,%AX

    (87) 0x40ba80 MOV	0x18(%R8),%RBX

    (87) 0x40ba84 LEA	(%R14,%R14,2),%R9

    (87) 0x40ba88 MOV	%EAX,%R10D

    (87) 0x40ba8b NOT	%R10D

    (87) 0x40ba8e ADD	%R12D,%R10D

    (87) 0x40ba91 AND	$0x1,%R10D

    (87) 0x40ba95 LEA	(%RBX,%R9,1),%R11

    (87) 0x40ba99 ADD	%RDI,%RBX

    (87) 0x40ba9c VMOVSD	(%R11),%XMM15

    (87) 0x40baa1 VMOVSD	0x8(%R11),%XMM1

    (87) 0x40baa7 VSUBSD	(%RBX),%XMM15,%XMM16

    (87) 0x40baad VSUBSD	0x8(%RBX),%XMM1,%XMM1

    (87) 0x40bab2 VMULSD	%XMM1,%XMM1,%XMM0

    (87) 0x40bab6 VFMADD231SD	%XMM16,%XMM16,%XMM0

    (87) 0x40babc VMOVSD	0x10(%R11),%XMM2

    (87) 0x40bac2 VSUBSD	0x10(%RBX),%XMM2,%XMM2

    (87) 0x40bac7 VFMADD231SD	%XMM2,%XMM2,%XMM0

    (87) 0x40bacc VCOMISD	%XMM0,%XMM3

    (87) 0x40bad0 JB	40bb57

    (87) 0x40bad6 VCOMISD	%XMM6,%XMM0

    (87) 0x40bada JBE	40bb57

    (87) 0x40badc VDIVSD	%XMM0,%XMM9,%XMM0

    (87) 0x40bae0 VMULSD	%XMM0,%XMM0,%XMM15

    (87) 0x40bae4 VMULSD	%XMM10,%XMM0,%XMM17

    (87) 0x40baea VMULSD	%XMM0,%XMM12,%XMM0

    (87) 0x40baee VMULSD	%XMM0,%XMM15,%XMM0

    (87) 0x40baf2 VSUBSD	%XMM9,%XMM0,%XMM15

    (87) 0x40baf7 VFMSUB132SD	%XMM0,%XMM11,%XMM15

    (87) 0x40bafc MOV	0x30(%R8),%RDX

    (87) 0x40bb00 MOV	0x28(%R8),%RSI

    (87) 0x40bb04 VMOVAPD	%XMM15,%XMM20

    (87) 0x40bb0a VFMADD231SD	%XMM8,%XMM15,%XMM7

    (87) 0x40bb0f VMOVAPD	%XMM0,%XMM15

    (87) 0x40bb13 VFMADD132SD	%XMM14,%XMM13,%XMM15

    (87) 0x40bb18 ADD	%R14,%RDX

    (87) 0x40bb1b ADD	%R9,%RSI

    (87) 0x40bb1e VFMADD213SD	(%RDX),%XMM8,%XMM20

    (87) 0x40bb24 VMOVSD	%XMM20,(%RDX)

    (87) 0x40bb2a VMULSD	%XMM15,%XMM0,%XMM0

    (87) 0x40bb2f VMULSD	%XMM17,%XMM0,%XMM15

    (87) 0x40bb35 VFNMADD213SD	(%RSI),%XMM15,%XMM16

    (87) 0x40bb3b VFNMADD213SD	0x8(%RSI),%XMM15,%XMM1

    (87) 0x40bb41 VMOVSD	%XMM16,(%RSI)

    (87) 0x40bb47 VFNMADD213SD	0x10(%RSI),%XMM2,%XMM15

    (87) 0x40bb4d VMOVSD	%XMM1,0x8(%RSI)

    (87) 0x40bb52 VMOVSD	%XMM15,0x10(%RSI)

    (87) 0x40bb57 LEA	0x1(%RAX),%EDX

    (87) 0x40bb5a LEA	0x18(%RBX),%RSI

    (87) 0x40bb5e CMP	%R12D,%EDX

    (87) 0x40bb61 JGE	40bdcf

    (87) 0x40bb67 TEST	%R10D,%R10D

    (87) 0x40bb6a JE	40bc40

    (87) 0x40bb70 VMOVSD	(%R11),%XMM1

    (87) 0x40bb75 VMOVSD	0x8(%R11),%XMM2

    (87) 0x40bb7b VSUBSD	0x18(%RBX),%XMM1,%XMM18

    (87) 0x40bb82 VSUBSD	0x8(%RSI),%XMM2,%XMM1

    (87) 0x40bb87 VMULSD	%XMM1,%XMM1,%XMM0

    (87) 0x40bb8b VFMADD231SD	%XMM18,%XMM18,%XMM0

    (87) 0x40bb91 VMOVSD	0x10(%R11),%XMM15

    (87) 0x40bb97 VSUBSD	0x10(%RSI),%XMM15,%XMM2

    (87) 0x40bb9c VFMADD231SD	%XMM2,%XMM2,%XMM0

    (87) 0x40bba1 VCOMISD	%XMM0,%XMM3

    (87) 0x40bba5 JB	40bc2e

    (87) 0x40bbab VCOMISD	%XMM6,%XMM0

    (87) 0x40bbaf JBE	40bc2e

    (87) 0x40bbb1 VDIVSD	%XMM0,%XMM9,%XMM0

    (87) 0x40bbb5 VMULSD	%XMM0,%XMM0,%XMM15

    (87) 0x40bbb9 VMULSD	%XMM10,%XMM0,%XMM19

    (87) 0x40bbbf VMULSD	%XMM0,%XMM12,%XMM0

    (87) 0x40bbc3 VMULSD	%XMM0,%XMM15,%XMM0

    (87) 0x40bbc7 VSUBSD	%XMM9,%XMM0,%XMM15

    (87) 0x40bbcc VFMSUB132SD	%XMM0,%XMM11,%XMM15

    (87) 0x40bbd1 MOV	0x30(%R8),%RBX

    (87) 0x40bbd5 MOV	0x28(%R8),%R10

    (87) 0x40bbd9 VMOVAPD	%XMM15,%XMM23

    (87) 0x40bbdf VFMADD231SD	%XMM8,%XMM15,%XMM7

    (87) 0x40bbe4 VMOVAPD	%XMM0,%XMM15

    (87) 0x40bbe8 VFMADD132SD	%XMM14,%XMM13,%XMM15

    (87) 0x40bbed ADD	%R14,%RBX

    (87) 0x40bbf0 ADD	%R9,%R10

    (87) 0x40bbf3 VFMADD213SD	(%RBX),%XMM8,%XMM23

    (87) 0x40bbf9 VMOVSD	%XMM23,(%RBX)

    (87) 0x40bbff VMULSD	%XMM15,%XMM0,%XMM0

    (87) 0x40bc04 VMULSD	%XMM19,%XMM0,%XMM15

    (87) 0x40bc0a VFNMADD213SD	(%R10),%XMM15,%XMM18

    (87) 0x40bc10 VFNMADD213SD	0x8(%R10),%XMM15,%XMM1

    (87) 0x40bc16 VMOVSD	%XMM18,(%R10)

    (87) 0x40bc1c VFNMADD213SD	0x10(%R10),%XMM2,%XMM15

    (87) 0x40bc22 VMOVSD	%XMM1,0x8(%R10)

    (87) 0x40bc28 VMOVSD	%XMM15,0x10(%R10)

    (87) 0x40bc2e INC	%EDX

    (87) 0x40bc30 ADD	$0x18,%RSI

    (87) 0x40bc34 CMP	%R12D,%EDX

    (87) 0x40bc37 JGE	40bdcf

    (87) 0x40bc3d NOPL	(%RAX)

      (88) 0x40bc40 VMOVSD	(%R11),%XMM1

      (88) 0x40bc45 VMOVSD	0x8(%R11),%XMM2

      (88) 0x40bc4b VSUBSD	(%RSI),%XMM1,%XMM24

      (88) 0x40bc51 VSUBSD	0x8(%RSI),%XMM2,%XMM1

      (88) 0x40bc56 VMULSD	%XMM1,%XMM1,%XMM0

      (88) 0x40bc5a VFMADD231SD	%XMM24,%XMM24,%XMM0

      (88) 0x40bc60 VMOVSD	0x10(%R11),%XMM15

      (88) 0x40bc66 VSUBSD	0x10(%RSI),%XMM15,%XMM2

      (88) 0x40bc6b VFMADD231SD	%XMM2,%XMM2,%XMM0

      (88) 0x40bc70 VCOMISD	%XMM0,%XMM3

      (88) 0x40bc74 JB	40bcfd

      (88) 0x40bc7a VCOMISD	%XMM6,%XMM0

      (88) 0x40bc7e JBE	40bcfd

      (88) 0x40bc80 VDIVSD	%XMM0,%XMM9,%XMM0

      (88) 0x40bc84 VMULSD	%XMM0,%XMM0,%XMM15

      (88) 0x40bc88 VMULSD	%XMM10,%XMM0,%XMM25

      (88) 0x40bc8e VMULSD	%XMM0,%XMM12,%XMM0

      (88) 0x40bc92 VMULSD	%XMM0,%XMM15,%XMM0

      (88) 0x40bc96 VSUBSD	%XMM9,%XMM0,%XMM15

      (88) 0x40bc9b VFMSUB132SD	%XMM0,%XMM11,%XMM15

      (88) 0x40bca0 MOV	0x30(%R8),%RBX

      (88) 0x40bca4 MOV	0x28(%R8),%R10

      (88) 0x40bca8 VMOVAPD	%XMM15,%XMM26

      (88) 0x40bcae VFMADD231SD	%XMM8,%XMM15,%XMM7

      (88) 0x40bcb3 VMOVAPD	%XMM0,%XMM15

      (88) 0x40bcb7 VFMADD132SD	%XMM14,%XMM13,%XMM15

      (88) 0x40bcbc ADD	%R14,%RBX

      (88) 0x40bcbf ADD	%R9,%R10

      (88) 0x40bcc2 VFMADD213SD	(%RBX),%XMM8,%XMM26

      (88) 0x40bcc8 VMOVSD	%XMM26,(%RBX)

      (88) 0x40bcce VMULSD	%XMM15,%XMM0,%XMM0

      (88) 0x40bcd3 VMULSD	%XMM25,%XMM0,%XMM15

      (88) 0x40bcd9 VFNMADD213SD	(%R10),%XMM15,%XMM24

      (88) 0x40bcdf VFNMADD213SD	0x8(%R10),%XMM15,%XMM1

      (88) 0x40bce5 VMOVSD	%XMM24,(%R10)

      (88) 0x40bceb VFNMADD213SD	0x10(%R10),%XMM2,%XMM15

      (88) 0x40bcf1 VMOVSD	%XMM1,0x8(%R10)

      (88) 0x40bcf7 VMOVSD	%XMM15,0x10(%R10)

      (88) 0x40bcfd VMOVSD	(%R11),%XMM1

      (88) 0x40bd02 VMOVSD	0x8(%R11),%XMM2

      (88) 0x40bd08 VSUBSD	0x18(%RSI),%XMM1,%XMM27

      (88) 0x40bd0f VSUBSD	0x20(%RSI),%XMM2,%XMM1

      (88) 0x40bd14 VMULSD	%XMM1,%XMM1,%XMM0

      (88) 0x40bd18 VFMADD231SD	%XMM27,%XMM27,%XMM0

      (88) 0x40bd1e VMOVSD	0x10(%R11),%XMM15

      (88) 0x40bd24 VSUBSD	0x28(%RSI),%XMM15,%XMM15

      (88) 0x40bd29 INC	%EDX

      (88) 0x40bd2b LEA	0x18(%RSI),%RBX

      (88) 0x40bd2f VFMADD231SD	%XMM15,%XMM15,%XMM0

      (88) 0x40bd34 VCOMISD	%XMM0,%XMM3

      (88) 0x40bd38 JB	40bdc0

      (88) 0x40bd3e VCOMISD	%XMM6,%XMM0

      (88) 0x40bd42 JBE	40bdc0

      (88) 0x40bd44 VDIVSD	%XMM0,%XMM9,%XMM0

      (88) 0x40bd48 VMULSD	%XMM0,%XMM0,%XMM2

      (88) 0x40bd4c VMULSD	%XMM10,%XMM0,%XMM28

      (88) 0x40bd52 VMULSD	%XMM0,%XMM12,%XMM0

      (88) 0x40bd56 VMULSD	%XMM0,%XMM2,%XMM0

      (88) 0x40bd5a VSUBSD	%XMM9,%XMM0,%XMM2

      (88) 0x40bd5f VFMSUB132SD	%XMM0,%XMM11,%XMM2

      (88) 0x40bd64 MOV	0x30(%R8),%RSI

      (88) 0x40bd68 MOV	0x28(%R8),%R10

      (88) 0x40bd6c VMOVAPD	%XMM2,%XMM29

      (88) 0x40bd72 VFMADD231SD	%XMM8,%XMM2,%XMM7

      (88) 0x40bd77 VMOVAPD	%XMM0,%XMM2

      (88) 0x40bd7b VFMADD132SD	%XMM14,%XMM13,%XMM2

      (88) 0x40bd80 ADD	%R14,%RSI

      (88) 0x40bd83 ADD	%R9,%R10

      (88) 0x40bd86 VFMADD213SD	(%RSI),%XMM8,%XMM29

      (88) 0x40bd8c VMOVSD	%XMM29,(%RSI)

      (88) 0x40bd92 VMULSD	%XMM2,%XMM0,%XMM0

      (88) 0x40bd96 VMULSD	%XMM28,%XMM0,%XMM2

      (88) 0x40bd9c VFNMADD213SD	(%R10),%XMM2,%XMM27

      (88) 0x40bda2 VFNMADD213SD	0x8(%R10),%XMM2,%XMM1

      (88) 0x40bda8 VMOVSD	%XMM27,(%R10)

      (88) 0x40bdae VFNMADD213SD	0x10(%R10),%XMM15,%XMM2

      (88) 0x40bdb4 VMOVSD	%XMM1,0x8(%R10)

      (88) 0x40bdba VMOVSD	%XMM2,0x10(%R10)

      (88) 0x40bdc0 INC	%EDX

      (88) 0x40bdc2 LEA	0x18(%RBX),%RSI

      (88) 0x40bdc6 CMP	%R12D,%EDX

      (88) 0x40bdc9 JL	40bc40

    (87) 0x40bdcf INC	%R15D

    (87) 0x40bdd2 ADD	$0x8,%R14

    (87) 0x40bdd6 CMP	%R15D,%ECX

    (87) 0x40bdd9 JG	40ba80

  (85) 0x40bddf MOV	-0x40(%RBP),%R9

  (85) 0x40bde3 MOV	-0x34(%RBP),%EAX

  (85) 0x40bde6 ADD	$0x4,%R9

  (85) 0x40bdea CMP	%R9,-0x58(%RBP)

  (85) 0x40bdee JNE	40b906

(86) 0x40bdf4 JMP	40ba22

0x40bdf9 MOV	-0x60(%RBP),%RBX

0x40bdfd MOV	0x28(%RBX),%RDX

0x40be01 LEA	0x28(%RBX),%R11

(84) 0x40be05 VMOVQ	%RDX,%XMM1

(84) 0x40be0a MOV	%RDX,%RAX

(84) 0x40be0d VADDSD	%XMM1,%XMM7,%XMM15

(84) 0x40be11 VMOVQ	%XMM15,%R10

(84) 0x40be16 LOCK CMPXCHG	%R10,(%R11)

(84) 0x40be1b MOV	%RDX,%RDI

(84) 0x40be1e MOV	%RAX,%RDX

(84) 0x40be21 CMP	%RAX,%RDI

(84) 0x40be24 JNE	40be05

0x40be26 ADD	$0x48,%RSP

0x40be2a POP	%RBX

0x40be2b POP	%R12

0x40be2d POP	%R13

0x40be2f POP	%R14

0x40be31 POP	%R15

0x40be33 POP	%RBP

0x40be34 RET

0x40be35 INC	%EAX

0x40be37 XOR	%EDX,%EDX

0x40be39 IMUL	%EAX,%ECX

0x40be3c ADD	%EDX,%ECX

0x40be3e LEA	(%RAX,%RCX,1),%R11D

0x40be42 CMP	%R11D,%ECX

0x40be45 JL	40b831

0x40be4b VXORPD	%XMM7,%XMM7,%XMM7

0x40be4f JMP	40bdfd

0x40be51 INC	%RSI

0x40be54 ADD	$0x40,%R10D

0x40be58 CMP	%ESI,%R11D

0x40be5b JLE	40be4b

0x40be5d TEST	%R8D,%R8D

0x40be60 JE	40bf03

0x40be66 CMP	$0x1,%R8D

0x40be6a JE	40beea

0x40be6c CMP	$0x2,%R8D

0x40be70 JE	40beda

0x40be72 CMP	$0x3,%R8D

0x40be76 JE	40beca

0x40be78 CMP	$0x4,%R8D

0x40be7c JE	40beba

0x40be7e CMP	$0x5,%R8D

0x40be82 JE	40beaa

0x40be84 CMP	$0x6,%R8D

0x40be88 JE	40be9a

0x40be8a TEST	%R9D,%R9D

0x40be8d JG	40b87d

0x40be93 INC	%RSI

0x40be96 ADD	$0x40,%R10D

0x40be9a TEST	%R9D,%R9D

0x40be9d JG	40b87d

0x40bea3 INC	%RSI

0x40bea6 ADD	$0x40,%R10D

0x40beaa TEST	%R9D,%R9D

0x40bead JG	40b87d

0x40beb3 INC	%RSI

0x40beb6 ADD	$0x40,%R10D

0x40beba TEST	%R9D,%R9D

0x40bebd JG	40b87d

0x40bec3 INC	%RSI

0x40bec6 ADD	$0x40,%R10D

0x40beca TEST	%R9D,%R9D

0x40becd JG	40b87d

0x40bed3 INC	%RSI

0x40bed6 ADD	$0x40,%R10D

0x40beda TEST	%R9D,%R9D

0x40bedd JG	40b87d

0x40bee3 INC	%RSI

0x40bee6 ADD	$0x40,%R10D

0x40beea TEST	%R9D,%R9D

0x40beed JG	40b87d

0x40bef3 INC	%RSI

0x40bef6 ADD	$0x40,%R10D

0x40befa CMP	%ESI,%R11D

0x40befd JLE	40be4b

(90) 0x40bf03 TEST	%R9D,%R9D

(90) 0x40bf06 JG	40b87d

(90) 0x40bf0c ADD	$0x8,%RSI

(90) 0x40bf10 ADD	$0x200,%R10D

(90) 0x40bf17 CMP	%ESI,%R11D

(90) 0x40bf1a JG	40bf03

0x40bf1c JMP	40be4b

0x40bf21 NOPW	%CS:(%RAX,%RAX,1)

0x40bf2c NOPL	(%RAX)

0x40bf30 MOV	$0x411e00,%ECX

0x40bf35 MOV	$0xb6,%EDX

0x40bf3a MOV	$0x411380,%ESI

0x40bf3f MOV	$0x41037f,%EDI

0x40bf44 CALL	4030a0 <__assert_fail@plt>

0x40bf49 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○99.07	gomp_thread_start	team.c:130	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_10

Source file and lines	ljForce.c:172-216
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172-191,197-216.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.63 to 6.67 cycles (2.49x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 16.63 to 1.17 cycles (14.19x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:182
omp_get_num_threads@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173
omp_get_thread_num@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 132 bytes (16 double precision FP elements). The binary function is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	133
nb uops	133
loop length	509
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.63 cycles
front end	16.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	14.33	14.33	14.33	14.33	14.33	14.33	5.75	5.75	5.75	5.75	0.50	0.50	0.00	0.00	0.00	0.00
cycles	14.33	14.33	14.33	14.33	14.33	14.33	5.75	5.75	5.75	5.75	0.50	0.50	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	16.63
Dispatch	14.33
DIV/SQRT	6.00
Overall L1	16.63

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	18%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	7%
load	9%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	14%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	8%
load	11%
store	12%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.63 cycles. At this rate:

3% of peak load performance is reached (7.94 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.96 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.63 to 14.33 cycles (1.16x speedup).

ASM code

In the binary file, the address of the function is: 40b7e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 4032d0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403280 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xc(%R12),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40be35 <ljForce._omp_fn.1+0x655>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RCX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40be4b <ljForce._omp_fn.1+0x66b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x30(%RBX),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVSXD %ECX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVSD 0x6375(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV 0x78(%R12),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x20(%RBX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x18(%RBX),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOT %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSD 0x10(%RBX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD 0x8(%RBX),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADD %R11D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x6,%R10D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
MOVSXD %R9D,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x2,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40be51 <ljForce._omp_fn.1+0x671>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV (%RDI,%RSI,4),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x80(%R12),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RBX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %RDI,%XMM22	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R10D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSD 0x62a8(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x62c8(%RIP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x6308(%RIP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x6308(%RIP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x60(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
LEA 0x28(%RBX),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RCX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40b831 <ljForce._omp_fn.1+0x51>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 40bdfd <ljForce._omp_fn.1+0x61d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %ESI,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40be4b <ljForce._omp_fn.1+0x66b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40bf03 <ljForce._omp_fn.1+0x723>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40beea <ljForce._omp_fn.1+0x70a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x2,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40beda <ljForce._omp_fn.1+0x6fa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x3,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40beca <ljForce._omp_fn.1+0x6ea>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x4,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40beba <ljForce._omp_fn.1+0x6da>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x5,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40beaa <ljForce._omp_fn.1+0x6ca>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x6,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40be9a <ljForce._omp_fn.1+0x6ba>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b87d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b87d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b87d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b87d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b87d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b87d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b87d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %ESI,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 40be4b <ljForce._omp_fn.1+0x66b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
JMP 40be4b <ljForce._omp_fn.1+0x66b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV $0x411e00,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0xb6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x411380,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x41037f,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4030a0 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_10

Source file and lines	ljForce.c:172-216
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.63 to 6.67 cycles (2.49x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:182
omp_get_num_threads@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173
omp_get_thread_num@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 132 bytes (16 double precision FP elements). The binary function is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	133
nb uops	133
loop length	509
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.63 cycles
front end	16.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	14.33	14.33	14.33	14.33	14.33	14.33	5.75	5.75	5.75	5.75	0.50	0.50	0.00	0.00	0.00	0.00
cycles	14.33	14.33	14.33	14.33	14.33	14.33	5.75	5.75	5.75	5.75	0.50	0.50	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	16.63
Dispatch	14.33
DIV/SQRT	6.00
Overall L1	16.63

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	18%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	7%
load	9%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	14%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	8%
load	11%
store	12%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.63 cycles. At this rate:

3% of peak load performance is reached (7.94 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.96 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40b7e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 4032d0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403280 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xc(%R12),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40be35 <ljForce._omp_fn.1+0x655>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RCX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40be4b <ljForce._omp_fn.1+0x66b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x30(%RBX),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVSXD %ECX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVSD 0x6375(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV 0x78(%R12),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x20(%RBX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x18(%RBX),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOT %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSD 0x10(%RBX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD 0x8(%RBX),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADD %R11D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x6,%R10D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
MOVSXD %R9D,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x2,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40be51 <ljForce._omp_fn.1+0x671>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV (%RDI,%RSI,4),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x80(%R12),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RBX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %RDI,%XMM22	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R10D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSD 0x62a8(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x62c8(%RIP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x6308(%RIP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x6308(%RIP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x60(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
LEA 0x28(%RBX),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RCX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40b831 <ljForce._omp_fn.1+0x51>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 40bdfd <ljForce._omp_fn.1+0x61d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %ESI,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40be4b <ljForce._omp_fn.1+0x66b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40bf03 <ljForce._omp_fn.1+0x723>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40beea <ljForce._omp_fn.1+0x70a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x2,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40beda <ljForce._omp_fn.1+0x6fa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x3,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40beca <ljForce._omp_fn.1+0x6ea>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x4,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40beba <ljForce._omp_fn.1+0x6da>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x5,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40beaa <ljForce._omp_fn.1+0x6ca>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x6,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40be9a <ljForce._omp_fn.1+0x6ba>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b87d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b87d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b87d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b87d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b87d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b87d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b87d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %ESI,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 40be4b <ljForce._omp_fn.1+0x66b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
JMP 40be4b <ljForce._omp_fn.1+0x66b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV $0x411e00,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0xb6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x411380,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x41037f,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4030a0 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

Name	Coverage (%)	Time (s)
▼ljForce._omp_fn.1–	64.19	4.56
▼Loop 86 - ljForce.c:175-216 - exec–	0.03	0.01
▼Loop 85 - ljForce.c:178-216 - exec–	0.26	0.01
▼Loop 87 - ljForce.c:187-216 - exec–	9.84	0.43
○Loop 88 - ljForce.c:191-216 - exec	54.06	2.36
○Loop 89 - ljForce.c:187-191 - exec	0.00	0.00
○Loop 90 - ljForce.c:178-178 - exec	0.00	0.00
○Loop 84 - ljForce.c:172-172 - exec	0.00	0.00

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