OV - exec - Function kineticEnergy._omp

	Function: kineticEnergy._omp_fn.0	Module: exec	Source: timestep.c:107-116	Coverage (incl. loops): 0.11% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 107 - 116

--------------------------------------------------------------------------------

107:    #pragma omp parallel for reduction(+:kenergy)

108:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

109:    {

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

0x40eeb0 PUSH	%RBP

0x40eeb1 MOV	%RSP,%RBP

0x40eeb4 PUSH	%R14

0x40eeb6 PUSH	%R13

0x40eeb8 PUSH	%R12

0x40eeba PUSH	%RBX

0x40eebb MOV	(%RDI),%RBX

0x40eebe MOV	%RDI,%R12

0x40eec1 CALL	4032d0 <omp_get_num_threads@plt>

0x40eec6 MOV	%EAX,%R13D

0x40eec9 CALL	403280 <omp_get_thread_num@plt>

0x40eece MOV	%EAX,%ECX

0x40eed0 MOV	0x18(%RBX),%R14

0x40eed4 MOV	0xc(%R14),%EAX

0x40eed8 CLTD

0x40eed9 IDIV	%R13D

0x40eedc CMP	%EDX,%ECX

0x40eede JL	40f143

0x40eee4 IMUL	%EAX,%ECX

0x40eee7 VXORPD	%XMM0,%XMM0,%XMM0

0x40eeeb ADD	%ECX,%EDX

0x40eeed LEA	(%RAX,%RDX,1),%ESI

0x40eef0 CMP	%ESI,%EDX

0x40eef2 JGE	40f11b

0x40eef8 MOV	0x78(%R14),%RDI

0x40eefc MOVSXD	%EDX,%R10

0x40eeff MOV	%EAX,%R11D

0x40ef02 VMOVSD	0x2c6e(%RIP),%XMM3

0x40ef0a ADD	%R10,%R11

0x40ef0d LEA	(%R10,%R10,2),%R13

0x40ef11 MOV	%R10,%R8

0x40ef14 SAL	$0x9,%R13

0x40ef18 SAL	$0x6,%R8

0x40ef1c LEA	(%RDI,%R10,4),%R9

0x40ef20 LEA	(%R11,%R11,2),%R10

0x40ef24 SAL	$0x9,%R10

0x40ef28 NOPL	(%RAX,%RAX,1)

(102) 0x40ef30 MOVSXD	(%R9),%RCX

(102) 0x40ef33 TEST	%ECX,%ECX

(102) 0x40ef35 JLE	40f103

(102) 0x40ef3b MOV	0x20(%RBX),%R14

(102) 0x40ef3f ADD	%R8,%RCX

(102) 0x40ef42 MOVSXD	%R8D,%RAX

(102) 0x40ef45 MOV	0x28(%RBX),%RDI

(102) 0x40ef49 MOV	0x10(%R14),%RSI

(102) 0x40ef4d LEA	(%RSI,%RCX,4),%R11

(102) 0x40ef51 LEA	(%RSI,%RAX,4),%RDX

(102) 0x40ef55 MOV	0x20(%R14),%RAX

(102) 0x40ef59 MOV	%R11,%RCX

(102) 0x40ef5c SUB	%RDX,%RCX

(102) 0x40ef5f SUB	$0x4,%RCX

(102) 0x40ef63 SHR	$0x2,%RCX

(102) 0x40ef67 INC	%RCX

(102) 0x40ef6a ADD	%R13,%RAX

(102) 0x40ef6d AND	$0x3,%ECX

(102) 0x40ef70 JE	40f030

(102) 0x40ef76 CMP	$0x1,%RCX

(102) 0x40ef7a JE	40eff0

(102) 0x40ef7c CMP	$0x2,%RCX

(102) 0x40ef80 JE	40efb9

(102) 0x40ef82 VMOVSD	(%RAX),%XMM1

(102) 0x40ef86 VMOVSD	0x8(%RAX),%XMM2

(102) 0x40ef8b VMULSD	%XMM2,%XMM2,%XMM4

(102) 0x40ef8f VFMADD231SD	%XMM1,%XMM1,%XMM4

(102) 0x40ef94 MOVSXD	(%RDX),%R14

(102) 0x40ef97 VMOVSD	0x10(%RAX),%XMM5

(102) 0x40ef9c ADD	$0x4,%RDX

(102) 0x40efa0 ADD	$0x18,%RAX

(102) 0x40efa4 VFMADD132SD	%XMM5,%XMM4,%XMM5

(102) 0x40efa9 SAL	$0x4,%R14

(102) 0x40efad VDIVSD	0x8(%RDI,%R14,1),%XMM3,%XMM6

(102) 0x40efb4 VFMADD231SD	%XMM5,%XMM6,%XMM0

(102) 0x40efb9 VMOVSD	(%RAX),%XMM7

(102) 0x40efbd VMOVSD	0x8(%RAX),%XMM8

(102) 0x40efc2 VMULSD	%XMM8,%XMM8,%XMM9

(102) 0x40efc7 VFMADD231SD	%XMM7,%XMM7,%XMM9

(102) 0x40efcc MOVSXD	(%RDX),%RSI

(102) 0x40efcf VMOVSD	0x10(%RAX),%XMM10

(102) 0x40efd4 ADD	$0x4,%RDX

(102) 0x40efd8 ADD	$0x18,%RAX

(102) 0x40efdc VFMADD132SD	%XMM10,%XMM9,%XMM10

(102) 0x40efe1 SAL	$0x4,%RSI

(102) 0x40efe5 VDIVSD	0x8(%RDI,%RSI,1),%XMM3,%XMM11

(102) 0x40efeb VFMADD231SD	%XMM10,%XMM11,%XMM0

(102) 0x40eff0 VMOVSD	(%RAX),%XMM12

(102) 0x40eff4 VMOVSD	0x8(%RAX),%XMM13

(102) 0x40eff9 VMULSD	%XMM13,%XMM13,%XMM14

(102) 0x40effe VFMADD231SD	%XMM12,%XMM12,%XMM14

(102) 0x40f003 MOVSXD	(%RDX),%RCX

(102) 0x40f006 VMOVSD	0x10(%RAX),%XMM15

(102) 0x40f00b ADD	$0x4,%RDX

(102) 0x40f00f ADD	$0x18,%RAX

(102) 0x40f013 VFMADD132SD	%XMM15,%XMM14,%XMM15

(102) 0x40f018 SAL	$0x4,%RCX

(102) 0x40f01c VDIVSD	0x8(%RDI,%RCX,1),%XMM3,%XMM1

(102) 0x40f022 VFMADD231SD	%XMM15,%XMM1,%XMM0

(102) 0x40f027 CMP	%RDX,%R11

(102) 0x40f02a JE	40f103

  (103) 0x40f030 VMOVSD	(%RAX),%XMM4

  (103) 0x40f034 VMOVSD	0x8(%RAX),%XMM2

  (103) 0x40f039 VMULSD	%XMM2,%XMM2,%XMM5

  (103) 0x40f03d VFMADD231SD	%XMM4,%XMM4,%XMM5

  (103) 0x40f042 MOVSXD	(%RDX),%R14

  (103) 0x40f045 VMOVSD	0x10(%RAX),%XMM6

  (103) 0x40f04a VMOVSD	0x20(%RAX),%XMM8

  (103) 0x40f04f VMULSD	%XMM8,%XMM8,%XMM9

  (103) 0x40f054 MOVSXD	0x4(%RDX),%RSI

  (103) 0x40f058 VMOVSD	0x28(%RAX),%XMM10

  (103) 0x40f05d VMOVSD	0x30(%RAX),%XMM12

  (103) 0x40f062 VMOVSD	0x38(%RAX),%XMM13

  (103) 0x40f067 VMULSD	%XMM13,%XMM13,%XMM14

  (103) 0x40f06c VFMADD231SD	%XMM12,%XMM12,%XMM14

  (103) 0x40f071 MOVSXD	0x8(%RDX),%RCX

  (103) 0x40f075 VMOVSD	0x40(%RAX),%XMM15

  (103) 0x40f07a VFMADD132SD	%XMM6,%XMM5,%XMM6

  (103) 0x40f07f VMOVSD	0x48(%RAX),%XMM2

  (103) 0x40f084 VMOVSD	0x50(%RAX),%XMM1

  (103) 0x40f089 VMULSD	%XMM1,%XMM1,%XMM5

  (103) 0x40f08d VFMADD231SD	%XMM2,%XMM2,%XMM5

  (103) 0x40f092 ADD	$0x10,%RDX

  (103) 0x40f096 ADD	$0x60,%RAX

  (103) 0x40f09a SAL	$0x4,%R14

  (103) 0x40f09e VFMADD132SD	%XMM15,%XMM14,%XMM15

  (103) 0x40f0a3 VDIVSD	0x8(%RDI,%R14,1),%XMM3,%XMM7

  (103) 0x40f0aa VFMADD132SD	%XMM6,%XMM0,%XMM7

  (103) 0x40f0af VMOVSD	-0x48(%RAX),%XMM0

  (103) 0x40f0b4 VFMADD231SD	%XMM0,%XMM0,%XMM9

  (103) 0x40f0b9 SAL	$0x4,%RSI

  (103) 0x40f0bd VMOVSD	-0x8(%RAX),%XMM0

  (103) 0x40f0c2 VFMADD132SD	%XMM0,%XMM5,%XMM0

  (103) 0x40f0c7 VDIVSD	0x8(%RDI,%RSI,1),%XMM3,%XMM11

  (103) 0x40f0cd MOVSXD	-0x4(%RDX),%R14

  (103) 0x40f0d1 VFMADD132SD	%XMM10,%XMM9,%XMM10

  (103) 0x40f0d6 SAL	$0x4,%RCX

  (103) 0x40f0da VDIVSD	0x8(%RDI,%RCX,1),%XMM3,%XMM4

  (103) 0x40f0e0 VFMADD132SD	%XMM10,%XMM7,%XMM11

  (103) 0x40f0e5 SAL	$0x4,%R14

  (103) 0x40f0e9 VDIVSD	0x8(%RDI,%R14,1),%XMM3,%XMM6

  (103) 0x40f0f0 VFMADD132SD	%XMM15,%XMM11,%XMM4

  (103) 0x40f0f5 VFMADD132SD	%XMM6,%XMM4,%XMM0

  (103) 0x40f0fa CMP	%RDX,%R11

  (103) 0x40f0fd JNE	40f030

(102) 0x40f103 ADD	$0x600,%R13

(102) 0x40f10a ADD	$0x4,%R9

(102) 0x40f10e ADD	$0x40,%R8

(102) 0x40f112 CMP	%R13,%R10

(102) 0x40f115 JNE	40ef30

0x40f11b MOV	0x8(%R12),%RAX

0x40f120 LEA	0x8(%R12),%RBX

(101) 0x40f125 VMOVQ	%RAX,%XMM3

(101) 0x40f12a VADDSD	%XMM3,%XMM0,%XMM7

(101) 0x40f12e VMOVQ	%XMM7,%R12

(101) 0x40f133 LOCK CMPXCHG	%R12,(%RBX)

(101) 0x40f138 JNE	40f125

0x40f13a POP	%RBX

0x40f13b POP	%R12

0x40f13d POP	%R13

0x40f13f POP	%R14

0x40f141 POP	%RBP

0x40f142 RET

0x40f143 INC	%EAX

0x40f145 XOR	%EDX,%EDX

0x40f147 JMP	40eee4

0x40f14c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○98.86	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.14	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_10

Source file and lines	timestep.c:107-116
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107-116.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.13 to 0.88 cycles (7.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.13 to 0.41 cycles (15.08x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107
omp_get_thread_num@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:108

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:108

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes.

General properties

nb instructions	49
nb uops	49
loop length	160
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.13 cycles
front end	6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.83	3.83	3.83	3.83	3.83	3.83	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.83	3.83	3.83	3.83	3.83	3.83	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	6.13
Dispatch	3.83
DIV/SQRT	6.00
Overall L1	6.13

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	7%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.13 cycles. At this rate:

2% of peak load performance is reached (7.18 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 40eeb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV (%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 4032d0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403280 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x18(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc(%R14),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40f143 <kineticEnergy._omp_fn.0+0x293>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40f11b <kineticEnergy._omp_fn.0+0x26b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %EDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x2c6e(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R10,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R10,%R10,2),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x9,%R13	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SAL $0x6,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA (%RDI,%R10,4),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R11,%R11,2),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x9,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x8(%R12),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x8(%R12),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 40eee4 <kineticEnergy._omp_fn.0+0x34>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_10

Source file and lines	timestep.c:107-116
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.13 to 0.88 cycles (7.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107
omp_get_thread_num@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:108

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:108

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes.

General properties

nb instructions	49
nb uops	49
loop length	160
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.13 cycles
front end	6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.83	3.83	3.83	3.83	3.83	3.83	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.83	3.83	3.83	3.83	3.83	3.83	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	6.13
Dispatch	3.83
DIV/SQRT	6.00
Overall L1	6.13

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	7%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.13 cycles. At this rate:

2% of peak load performance is reached (7.18 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 40eeb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV (%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 4032d0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403280 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x18(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc(%R14),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40f143 <kineticEnergy._omp_fn.0+0x293>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40f11b <kineticEnergy._omp_fn.0+0x26b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %EDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x2c6e(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R10,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R10,%R10,2),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x9,%R13	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SAL $0x6,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA (%RDI,%R10,4),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R11,%R11,2),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x9,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x8(%R12),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x8(%R12),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 40eee4 <kineticEnergy._omp_fn.0+0x34>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

Name	Coverage (%)	Time (s)
▼kineticEnergy._omp_fn.0–	0.11	0.01
▼Loop 102 - timestep.c:110-116 - exec–	0.02	0.01
○Loop 103 - timestep.c:110-116 - exec	0.09	0.01
○Loop 101 - timestep.c:107-107 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code