OV - exec - Loop 108

0x40fa90 MOVSXD	(%R15,%RAX,4),%RDX    [4]

0x40fa94 VMOVSD	(%R9,%RCX,1),%XMM19    [2]

0x40fa9b INC	%RAX

0x40fa9e SAL	$0x4,%RDX

0x40faa2 VDIVSD	0x8(%R11,%RDX,1),%XMM0,%XMM18    [3]

0x40faaa VFMADD213SD	(%R8,%RCX,1),%XMM18,%XMM19    [1]

0x40fab1 VMOVDDUP	%XMM18,%XMM18

0x40fab7 VMOVSD	%XMM19,(%R8,%RCX,1)    [1]

0x40fabe VMOVUPD	0x8(%R9,%RCX,1),%XMM19    [2]

0x40fac9 VFMADD213PD	0x8(%R8,%RCX,1),%XMM19,%XMM18    [1]

0x40fad4 VMOVUPD	%XMM18,0x8(%R8,%RCX,1)    [1]

0x40fadf ADD	$0x18,%RCX

0x40fae3 CMP	%EAX,%R12D

0x40fae6 JNE	40fa90

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 88 - 93

--------------------------------------------------------------------------------

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.25
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P10, P11,
Function	advancePosition.extracted
Source	timestep.c:88-93
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	1.78
CQA cycles if fully vectorized	0.50
Front-end cycles	1.63
P0 cycles	0.83
P1 cycles	0.83
P2 cycles	0.83
P3 cycles	0.83
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	14.00
Nb uops	13.00
Nb loads	6.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.75
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.00
Bytes prefetched	0.00
Bytes loaded	60.00
Bytes stored	24.00
Stride 0	1.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	37.50
Vectorization ratio load	40.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	17.19
Vector-efficiency ratio load	17.50
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	18.75
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.25
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P10, P11,
Function	advancePosition.extracted
Source	timestep.c:88-93
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	1.78
CQA cycles if fully vectorized	0.50
Front-end cycles	1.63
P0 cycles	0.83
P1 cycles	0.83
P2 cycles	0.83
P3 cycles	0.83
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	14.00
Nb uops	13.00
Nb loads	6.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.75
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.00
Bytes prefetched	0.00
Bytes loaded	60.00
Bytes stored	24.00
Stride 0	1.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	37.50
Vectorization ratio load	40.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	17.19
Vector-efficiency ratio load	17.50
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	18.75
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advancePosition.extracted
Source file and lines	timestep.c:88-93
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88-93.

It is peel/tail loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is poorly vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions).

Details

37% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.00 to 2.00 cycles (2.00x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.75 cycles (2.29x speedup).

FMA

Detected 3 FMA (fused multiply-add) operations.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 7 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
3: multiply (all inside FMA instructions)
1: divide

The binary loop is loading 60 bytes (7 double precision FP elements). The binary loop is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	14
nb uops	13
loop length	88
used x86 registers	8
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.63 cycles
front end	1.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.83	0.83	0.83	0.83	0.83	0.83	2.00	2.00	2.00	2.00	1.50	1.50	0.50	0.50	1.00	1.00
cycles	0.83	0.83	0.83	0.83	0.83	0.83	2.00	2.00	2.00	2.00	1.50	1.50	0.50	0.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	4.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.63
Dispatch	2.00
DIV/SQRT	4.00
Data deps.	1.00
Overall L1	4.00

Vectorization ratios

all	37%
load	40%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	17%
load	17%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	18%
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

5% of peak load performance is reached (15.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40fa90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOVSXD (%R15,%RAX,4),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R9,%RCX,1),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%R11,%RDX,1),%XMM0,%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VFMADD213SD (%R8,%RCX,1),%XMM18,%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVSD %XMM19,(%R8,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD 0x8(%R9,%RCX,1),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VFMADD213PD 0x8(%R8,%RCX,1),%XMM19,%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM18,0x8(%R8,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 40fa90 <advancePosition.extracted+0x7c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A

Function	advancePosition.extracted
Source file and lines	timestep.c:88-93
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88-93.

It is peel/tail loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is poorly vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions).

Details

37% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.00 to 2.00 cycles (2.00x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.75 cycles (2.29x speedup).

FMA

Detected 3 FMA (fused multiply-add) operations.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 7 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
3: multiply (all inside FMA instructions)
1: divide

The binary loop is loading 60 bytes (7 double precision FP elements). The binary loop is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	14
nb uops	13
loop length	88
used x86 registers	8
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.63 cycles
front end	1.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.83	0.83	0.83	0.83	0.83	0.83	2.00	2.00	2.00	2.00	1.50	1.50	0.50	0.50	1.00	1.00
cycles	0.83	0.83	0.83	0.83	0.83	0.83	2.00	2.00	2.00	2.00	1.50	1.50	0.50	0.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	4.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.63
Dispatch	2.00
DIV/SQRT	4.00
Data deps.	1.00
Overall L1	4.00

Vectorization ratios

all	37%
load	40%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	17%
load	17%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	18%
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

5% of peak load performance is reached (15.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40fa90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOVSXD (%R15,%RAX,4),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R9,%RCX,1),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%R11,%RDX,1),%XMM0,%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VFMADD213SD (%R8,%RCX,1),%XMM18,%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP %XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVSD %XMM19,(%R8,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD 0x8(%R9,%RCX,1),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VFMADD213PD 0x8(%R8,%RCX,1),%XMM19,%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM18,0x8(%R8,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 40fa90 <advancePosition.extracted+0x7c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A

Report Configuration

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code