OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:211-385 [...]	Coverage (incl. loops): 0.28% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 211 - 385

--------------------------------------------------------------------------------

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

[...]

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

[...]

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

372:    {

373:       if (iz == gridSize[2]) iz = gridSize[2] - 1;

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x40aac0 PUSH	%RBP

0x40aac1 MOV	%RSP,%RBP

0x40aac4 PUSH	%R15

0x40aac6 PUSH	%R14

0x40aac8 PUSH	%R13

0x40aaca PUSH	%R12

0x40aacc PUSH	%RBX

0x40aacd SUB	$0x28,%RSP

0x40aad1 MOV	0xc(%RDI),%EAX

0x40aad4 CMP	0x14(%RDI),%EAX

0x40aad7 JGE	40aaf6

0x40aad9 MOV	0x78(%RDI),%RCX

0x40aadd CLTQ

0x40aadf NOP

(91) 0x40aae0 MOVL	$0,(%RCX,%RAX,4)

(91) 0x40aae7 INC	%RAX

(91) 0x40aaea MOVSXD	0x14(%RDI),%RDX

(91) 0x40aaee CMP	%RDX,%RAX

(91) 0x40aaf1 JL	40aae0

0x40aaf3 MOV	0xc(%RDI),%EAX

0x40aaf6 MOV	%RAX,-0x30(%RBP)

0x40aafa TEST	%EAX,%EAX

0x40aafc JLE	40aed8

0x40ab02 MOV	0x78(%RDI),%R10

0x40ab06 XOR	%EAX,%EAX

0x40ab08 JMP	40ab20

0x40ab0a NOPW	(%RAX,%RAX,1)

(89) 0x40ab10 MOVSXD	-0x30(%RBP),%RCX

(89) 0x40ab14 INC	%RAX

(89) 0x40ab17 CMP	%RCX,%RAX

(89) 0x40ab1a JGE	40aed8

(89) 0x40ab20 CMPL	$0,(%R10,%RAX,4)

(89) 0x40ab25 JLE	40ab10

(89) 0x40ab27 MOV	%RAX,%RCX

(89) 0x40ab2a SAL	$0x6,%RCX

(89) 0x40ab2e XOR	%EDX,%EDX

(89) 0x40ab30 MOV	%RAX,-0x48(%RBP)

(89) 0x40ab34 MOV	%RCX,-0x40(%RBP)

(89) 0x40ab38 MOV	-0x30(%RBP),%RCX

(89) 0x40ab3c MOV	%ECX,%R14D

(89) 0x40ab3f JMP	40ab60

0x40ab41 NOPW	%CS:(%RAX,%RAX,1)

  (90) 0x40ab50 MOV	-0x38(%RBP),%RDX

  (90) 0x40ab54 INC	%EDX

  (90) 0x40ab56 MOV	0x78(%RDI),%R10

  (90) 0x40ab5a CMP	(%R10,%RAX,4),%EDX

  (90) 0x40ab5e JGE	40ab10

  (90) 0x40ab60 MOV	-0x40(%RBP),%RCX

  (90) 0x40ab64 MOV	0x18(%RSI),%R11

  (90) 0x40ab68 VMOVSD	0x30(%RDI),%XMM1

  (90) 0x40ab6d MOV	(%RDI),%R13D

  (90) 0x40ab70 ADD	%EDX,%ECX

  (90) 0x40ab72 MOV	%R13D,%R12D

  (90) 0x40ab75 MOVSXD	%ECX,%R9

  (90) 0x40ab78 LEA	(%R9,%R9,2),%RBX

  (90) 0x40ab7c VMOVSD	(%R11,%RBX,8),%XMM0

  (90) 0x40ab82 VUCOMISD	%XMM0,%XMM1

  (90) 0x40ab86 JBE	40aba5

  (90) 0x40ab88 VSUBSD	0x18(%RDI),%XMM0,%XMM0

  (90) 0x40ab8d VMULSD	0x60(%RDI),%XMM0,%XMM0

  (90) 0x40ab92 VROUNDSD	$0x9,%XMM0,%XMM0,%XMM0

  (90) 0x40ab98 VCVTTSD2SI	%XMM0,%R12D

  (90) 0x40ab9c CMP	%R12D,%R13D

  (90) 0x40ab9f JNE	40aba5

  (90) 0x40aba1 LEA	-0x1(%R13),%R12D

  (90) 0x40aba5 VMOVSD	0x8(%R11,%RBX,8),%XMM0

  (90) 0x40abac MOV	0x4(%RDI),%ECX

  (90) 0x40abaf MOV	%R14D,%EAX

  (90) 0x40abb2 VSUBSD	0x20(%RDI),%XMM0,%XMM1

  (90) 0x40abb7 VMULSD	0x68(%RDI),%XMM1,%XMM1

  (90) 0x40abbc VROUNDSD	$0x9,%XMM1,%XMM1,%XMM1

  (90) 0x40abc2 VCVTTSD2SI	%XMM1,%R15D

  (90) 0x40abc6 CMP	%R15D,%ECX

  (90) 0x40abc9 JNE	40abcf

  (90) 0x40abcb LEA	-0x1(%RCX),%R15D

  (90) 0x40abcf VMOVSD	0x38(%RDI),%XMM1

  (90) 0x40abd4 VMOVSD	0x10(%R11,%RBX,8),%XMM2

  (90) 0x40abdb VMOVSD	0x40(%RDI),%XMM3

  (90) 0x40abe0 MOV	0x8(%RDI),%R14D

  (90) 0x40abe4 MOV	%RDX,-0x38(%RBP)

  (90) 0x40abe8 MOV	%R15D,%EDX

  (90) 0x40abeb VUCOMISD	%XMM0,%XMM1

  (90) 0x40abef CMOVBE	%ECX,%EDX

  (90) 0x40abf2 VUCOMISD	%XMM2,%XMM3

  (90) 0x40abf6 JBE	40ac40

  (90) 0x40abf8 VSUBSD	0x28(%RDI),%XMM2,%XMM2

  (90) 0x40abfd VMULSD	0x70(%RDI),%XMM2,%XMM2

  (90) 0x40ac02 VROUNDSD	$0x9,%XMM2,%XMM2,%XMM2

  (90) 0x40ac08 VCVTTSD2SI	%XMM2,%R8D

  (90) 0x40ac0c CMP	%R8D,%R14D

  (90) 0x40ac0f JNE	40ac15

  (90) 0x40ac11 LEA	-0x1(%R14),%R8D

  (90) 0x40ac15 CMP	$-0x1,%R8D

  (90) 0x40ac19 JE	40ac78

  (90) 0x40ac1b VUCOMISD	%XMM0,%XMM1

  (90) 0x40ac1f JA	40acad

  (90) 0x40ac25 IMUL	%R14D,%ECX

  (90) 0x40ac29 ADD	$0x2,%R13D

  (90) 0x40ac2d ADD	%R14D,%R8D

  (90) 0x40ac30 IMUL	%R13D,%R8D

  (90) 0x40ac34 LEA	(%R12,%RCX,2),%ECX

  (90) 0x40ac38 ADD	%R8D,%ECX

  (90) 0x40ac3b JMP	40acf1

  (90) 0x40ac40 LEA	(%RDX,%R14,2),%EDX

  (90) 0x40ac44 LEA	(%R14,%R14,1),%R8D

  (90) 0x40ac48 ADD	$0x2,%R13D

  (90) 0x40ac4c ADD	%EAX,%R12D

  (90) 0x40ac4f MOV	%EAX,%R14D

  (90) 0x40ac52 IMUL	%ECX,%R8D

  (90) 0x40ac56 LEA	0x3(%RCX,%RDX,1),%ECX

  (90) 0x40ac5a IMUL	%R13D,%ECX

  (90) 0x40ac5e ADD	%R8D,%R12D

  (90) 0x40ac61 LEA	0x1(%RCX,%R12,1),%R15D

  (90) 0x40ac66 MOV	-0x48(%RBP),%RAX

  (90) 0x40ac6a TEST	%R15D,%R15D

  (90) 0x40ac6d JNS	40ad0a

0x40ac73 JMP	40aebf

  (90) 0x40ac78 LEA	(%R14,%R14,1),%R8D

  (90) 0x40ac7c LEA	0x1(%RDX,%R14,2),%EDX

  (90) 0x40ac81 ADD	$0x2,%R13D

  (90) 0x40ac85 IMUL	%R8D,%ECX

  (90) 0x40ac89 IMUL	%R13D,%EDX

  (90) 0x40ac8d ADD	%ECX,%R12D

  (90) 0x40ac90 MOV	-0x30(%RBP),%RCX

  (90) 0x40ac94 ADD	%EDX,%R12D

  (90) 0x40ac97 LEA	0x1(%RCX,%R12,1),%R15D

  (90) 0x40ac9c MOV	%ECX,%R14D

  (90) 0x40ac9f MOV	-0x48(%RBP),%RAX

  (90) 0x40aca3 TEST	%R15D,%R15D

  (90) 0x40aca6 JNS	40ad0a

0x40aca8 JMP	40aebf

  (90) 0x40acad CMP	$-0x1,%R15D

  (90) 0x40acb1 JE	40acde

  (90) 0x40acb3 CMP	%R13D,%R12D

  (90) 0x40acb6 JNE	40ae8b

  (90) 0x40acbc MOV	-0x30(%RBP),%RDX

  (90) 0x40acc0 ADD	%R14D,%R8D

  (90) 0x40acc3 IMUL	%R8D,%ECX

  (90) 0x40acc7 ADD	%EDX,%R15D

  (90) 0x40acca MOV	%EDX,%R14D

  (90) 0x40accd ADD	%ECX,%R15D

  (90) 0x40acd0 MOV	-0x48(%RBP),%RAX

  (90) 0x40acd4 TEST	%R15D,%R15D

  (90) 0x40acd7 JNS	40ad0a

0x40acd9 JMP	40aebf

  (90) 0x40acde IMUL	%ECX,%R14D

  (90) 0x40ace2 ADD	$0x2,%R13D

  (90) 0x40ace6 IMUL	%R8D,%R13D

  (90) 0x40acea LEA	(%R12,%R14,2),%ECX

  (90) 0x40acee ADD	%R13D,%ECX

  (90) 0x40acf1 MOV	-0x30(%RBP),%RDX

  (90) 0x40acf5 LEA	0x1(%RDX,%RCX,1),%R15D

  (90) 0x40acfa MOV	%EDX,%R14D

  (90) 0x40acfd MOV	-0x48(%RBP),%RAX

  (90) 0x40ad01 TEST	%R15D,%R15D

  (90) 0x40ad04 JS	40aebf

  (90) 0x40ad0a CMP	0x14(%RDI),%R15D

  (90) 0x40ad0e JGE	40aee7

  (90) 0x40ad14 MOV	%R15D,%R8D

  (90) 0x40ad17 CMP	%R8,%RAX

  (90) 0x40ad1a JE	40ab50

  (90) 0x40ad20 MOV	0x8(%RSI),%R14

  (90) 0x40ad24 MOVSXD	(%R10,%R8,4),%R10

  (90) 0x40ad28 LEA	(%R11,%RBX,8),%RCX

  (90) 0x40ad2c MOVSXD	%R15D,%RDX

  (90) 0x40ad2f SAL	$0x6,%RDX

  (90) 0x40ad33 MOV	(%R14,%R9,4),%EBX

  (90) 0x40ad37 ADD	%R10,%RDX

  (90) 0x40ad3a MOV	%EBX,(%R14,%RDX,4)

  (90) 0x40ad3e MOV	0x10(%RSI),%R10

  (90) 0x40ad42 MOV	(%R10,%R9,4),%EBX

  (90) 0x40ad46 MOV	%EBX,(%R10,%RDX,4)

  (90) 0x40ad4a LEA	(,%RDX,8),%R10

  (90) 0x40ad52 MOV	0x10(%RCX),%RBX

  (90) 0x40ad56 LEA	(%R10,%R10,2),%R10

  (90) 0x40ad5a MOV	%RBX,0x10(%R11,%R10,1)

  (90) 0x40ad5f VMOVUPS	(%RCX),%XMM0

  (90) 0x40ad63 LEA	(,%R9,8),%RCX

  (90) 0x40ad6b LEA	(%RCX,%RCX,2),%RCX

  (90) 0x40ad6f VMOVUPS	%XMM0,(%R11,%R10,1)

  (90) 0x40ad75 MOV	0x20(%RSI),%R11

  (90) 0x40ad79 MOV	0x10(%R11,%RCX,1),%RBX

  (90) 0x40ad7e MOV	%RBX,0x10(%R11,%R10,1)

  (90) 0x40ad83 VMOVUPS	(%R11,%RCX,1),%XMM0

  (90) 0x40ad89 VMOVUPS	%XMM0,(%R11,%R10,1)

  (90) 0x40ad8f MOV	0x28(%RSI),%R11

  (90) 0x40ad93 MOV	0x10(%R11,%RCX,1),%RBX

  (90) 0x40ad98 MOV	%RBX,0x10(%R11,%R10,1)

  (90) 0x40ad9d VMOVUPD	(%R11,%RCX,1),%XMM0

  (90) 0x40ada3 VMOVUPD	%XMM0,(%R11,%R10,1)

  (90) 0x40ada9 MOV	0x30(%RSI),%R10

  (90) 0x40adad MOV	(%R10,%R9,8),%R11

  (90) 0x40adb1 MOV	%R11,(%R10,%RDX,8)

  (90) 0x40adb5 MOV	0x78(%RDI),%R10

  (90) 0x40adb9 MOV	(%R10,%R8,4),%EDX

  (90) 0x40adbd LEA	0x1(%RDX),%R11D

  (90) 0x40adc1 MOV	%R11D,(%R10,%R8,4)

  (90) 0x40adc5 CMP	$0x3f,%EDX

  (90) 0x40adc8 JGE	40af00

  (90) 0x40adce MOVSXD	(%R10,%RAX,4),%RDX

  (90) 0x40add2 DEC	%RDX

  (90) 0x40add5 MOV	%EDX,(%R10,%RAX,4)

  (90) 0x40add9 TEST	%EDX,%EDX

  (90) 0x40addb JE	40ae63

  (90) 0x40ade1 ADD	-0x40(%RBP),%RDX

  (90) 0x40ade5 MOV	0x8(%RSI),%R8

  (90) 0x40ade9 MOV	(%R8,%RDX,4),%R10D

  (90) 0x40aded MOV	%R10D,(%R8,%R9,4)

  (90) 0x40adf1 MOV	0x10(%RSI),%R8

  (90) 0x40adf5 MOV	(%R8,%RDX,4),%R10D

  (90) 0x40adf9 MOV	%R10D,(%R8,%R9,4)

  (90) 0x40adfd LEA	(,%RDX,8),%R8

  (90) 0x40ae05 MOV	0x18(%RSI),%R10

  (90) 0x40ae09 LEA	(%R8,%R8,2),%R8

  (90) 0x40ae0d MOV	0x10(%R10,%R8,1),%R11

  (90) 0x40ae12 MOV	%R11,0x10(%R10,%RCX,1)

  (90) 0x40ae17 VMOVUPS	(%R10,%R8,1),%XMM0

  (90) 0x40ae1d VMOVUPS	%XMM0,(%R10,%RCX,1)

  (90) 0x40ae23 MOV	0x20(%RSI),%R10

  (90) 0x40ae27 MOV	0x10(%R10,%R8,1),%R11

  (90) 0x40ae2c MOV	%R11,0x10(%R10,%RCX,1)

  (90) 0x40ae31 VMOVUPS	(%R10,%R8,1),%XMM0

  (90) 0x40ae37 VMOVUPS	%XMM0,(%R10,%RCX,1)

  (90) 0x40ae3d MOV	0x28(%RSI),%R10

  (90) 0x40ae41 MOV	0x10(%R10,%R8,1),%R11

  (90) 0x40ae46 MOV	%R11,0x10(%R10,%RCX,1)

  (90) 0x40ae4b VMOVUPD	(%R10,%R8,1),%XMM0

  (90) 0x40ae51 VMOVUPD	%XMM0,(%R10,%RCX,1)

  (90) 0x40ae57 MOV	0x30(%RSI),%RCX

  (90) 0x40ae5b MOV	(%RCX,%RDX,8),%RDX

  (90) 0x40ae5f MOV	%RDX,(%RCX,%R9,8)

  (90) 0x40ae63 MOV	0xc(%RDI),%ECX

  (90) 0x40ae66 MOV	%RCX,-0x30(%RBP)

  (90) 0x40ae6a CMP	%ECX,%R15D

  (90) 0x40ae6d JLE	40ae71

  (90) 0x40ae6f DECL	(%RSI)

  (90) 0x40ae71 MOV	-0x38(%RBP),%RDX

  (90) 0x40ae75 MOV	%ECX,%R14D

  (90) 0x40ae78 MOV	0x78(%RDI),%R10

  (90) 0x40ae7c CMP	(%R10,%RAX,4),%EDX

  (90) 0x40ae80 JL	40ab60

(89) 0x40ae86 JMP	40ab10

  (90) 0x40ae8b IMUL	%R8D,%ECX

  (90) 0x40ae8f MOV	-0x30(%RBP),%R8

  (90) 0x40ae93 MOV	%EAX,%R14D

  (90) 0x40ae96 ADD	%R15D,%ECX

  (90) 0x40ae99 LEA	(%RCX,%R8,1),%EDX

  (90) 0x40ae9d IMUL	%R13D,%ECX

  (90) 0x40aea1 ADD	%R12D,%ECX

  (90) 0x40aea4 CMP	$-0x1,%R12D

  (90) 0x40aea8 CMOVE	%EDX,%ECX

  (90) 0x40aeab CMOVE	%R8D,%R14D

  (90) 0x40aeaf MOV	%ECX,%R15D

  (90) 0x40aeb2 MOV	-0x48(%RBP),%RAX

  (90) 0x40aeb6 TEST	%R15D,%R15D

  (90) 0x40aeb9 JNS	40ad0a

0x40aebf MOV	$0x41478c,%EDI

0x40aec4 MOV	$0x414687,%ESI

0x40aec9 MOV	$0x414796,%ECX

0x40aece MOV	$0xf6,%EDX

0x40aed3 CALL	403080 <__assert_fail@plt>

0x40aed8 ADD	$0x28,%RSP

0x40aedc POP	%RBX

0x40aedd POP	%R12

0x40aedf POP	%R13

0x40aee1 POP	%R14

0x40aee3 POP	%R15

0x40aee5 POP	%RBP

0x40aee6 RET

0x40aee7 MOV	$0x4147c5,%EDI

0x40aeec MOV	$0x414687,%ESI

0x40aef1 MOV	$0x414796,%ECX

0x40aef6 MOV	$0xf7,%EDX

0x40aefb CALL	403080 <__assert_fail@plt>

0x40af00 MOV	$0x4147df,%EDI

0x40af05 MOV	$0x414687,%ESI

0x40af0a MOV	$0x4147fe,%ECX

0x40af0f MOV	$0x106,%EDX

0x40af14 CALL	403080 <__assert_fail@plt>

0x40af19 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►53.70+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
►45.55+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_1

Source file and lines	linkCells.c:211-385
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-237,246-247,258-269,288-304,327-334,352-365,371-373,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.00 to 0.40 cycles (14.81x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:384

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	50
nb uops	48
loop length	188
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.33	4.33	4.33	4.33	4.33	4.33	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.33	4.33	4.33	4.33	4.33	4.33	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	4.33
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

1% of peak load performance is reached (4.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 4.33 cycles (1.38x speedup).

ASM code

In the binary file, the address of the function is: 40aac0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xc(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP 0x14(%RDI),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JGE 40aaf6 <updateLinkCells+0x36>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CLTQ																				scal (12.5%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xc(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40aed8 <updateLinkCells+0x418>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 40ab20 <updateLinkCells+0x60>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 40aebf <updateLinkCells+0x3ff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
JMP 40aebf <updateLinkCells+0x3ff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
JMP 40aebf <updateLinkCells+0x3ff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV $0x41478c,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x414687,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x414796,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403080 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x4147c5,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x414687,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x414796,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403080 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV $0x4147df,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x414687,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x4147fe,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x106,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403080 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_1

Source file and lines	linkCells.c:211-385
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:384

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	50
nb uops	48
loop length	188
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.33	4.33	4.33	4.33	4.33	4.33	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.33	4.33	4.33	4.33	4.33	4.33	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	4.33
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

1% of peak load performance is reached (4.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40aac0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xc(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP 0x14(%RDI),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JGE 40aaf6 <updateLinkCells+0x36>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CLTQ																				scal (12.5%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xc(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40aed8 <updateLinkCells+0x418>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 40ab20 <updateLinkCells+0x60>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 40aebf <updateLinkCells+0x3ff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
JMP 40aebf <updateLinkCells+0x3ff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
JMP 40aebf <updateLinkCells+0x3ff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV $0x41478c,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x414687,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x414796,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403080 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x4147c5,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x414687,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x414796,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403080 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV $0x4147df,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x414687,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x4147fe,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x106,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403080 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.28	0.02
▼Loop 89 - linkCells.c:211-373 - exec–	0.00	0.01
○Loop 90 - linkCells.c:211-373 - exec	0.28	1.98
○Loop 91 - linkCells.c:384-385 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code