OV - exec - Loop 109

	Loop Id: 109	Module: exec	Source: timestep.c:76-78	Coverage: 0.88%

0x213650 VMOVUPD	(%R15,%RDX,1),%ZMM18    [2]

0x213657 VMOVUPD	0x40(%R15,%RDX,1),%ZMM19    [2]

0x21365f VMOVUPD	0x40(%R8,%RDX,1),%ZMM26    [1]

0x213667 VMOVUPD	0x80(%R15,%RDX,1),%ZMM20    [2]

0x21366f VMOVUPD	0x80(%R8,%RDX,1),%ZMM23    [1]

0x213677 VBROADCASTSD	(%RBX),%ZMM17    [3]

0x21367d VMOVAPD	%ZMM18,%ZMM21

0x213683 VPERMT2PD	%ZMM19,%ZMM5,%ZMM21

0x213689 VMOVAPD	%ZMM18,%ZMM22

0x21368f VPERMT2PD	%ZMM19,%ZMM7,%ZMM22

0x213695 VPERMT2PD	%ZMM18,%ZMM9,%ZMM19

0x21369b VMOVUPD	(%R8,%RDX,1),%ZMM18    [1]

0x2136a2 VPERMT2PD	%ZMM20,%ZMM6,%ZMM21

0x2136a8 VPERMT2PD	%ZMM20,%ZMM8,%ZMM22

0x2136ae VPERMT2PD	%ZMM20,%ZMM10,%ZMM19

0x2136b4 VMOVAPD	%ZMM18,%ZMM24

0x2136ba VPERMT2PD	%ZMM26,%ZMM5,%ZMM24

0x2136c0 VMOVAPD	%ZMM18,%ZMM25

0x2136c6 VPERMT2PD	%ZMM26,%ZMM7,%ZMM25

0x2136cc VPERMT2PD	%ZMM18,%ZMM9,%ZMM26

0x2136d2 VPERMT2PD	%ZMM23,%ZMM6,%ZMM24

0x2136d8 VPERMT2PD	%ZMM23,%ZMM8,%ZMM25

0x2136de VPERMT2PD	%ZMM23,%ZMM10,%ZMM26

0x2136e4 VFMADD231PD	%ZMM21,%ZMM17,%ZMM24

0x2136ea VFMADD231PD	%ZMM22,%ZMM17,%ZMM25

0x2136f0 VFMADD231PD	%ZMM19,%ZMM17,%ZMM26

0x2136f6 VMOVAPD	%ZMM25,%ZMM17

0x2136fc VPERMT2PD	%ZMM24,%ZMM11,%ZMM17

0x213702 VMOVAPD	%ZMM24,%ZMM18

0x213708 VPERMT2PD	%ZMM25,%ZMM13,%ZMM18

0x21370e VPERMT2PD	%ZMM25,%ZMM15,%ZMM24

0x213714 VPERMT2PD	%ZMM26,%ZMM12,%ZMM17

0x21371a VPERMT2PD	%ZMM26,%ZMM14,%ZMM18

0x213720 VPERMT2PD	%ZMM26,%ZMM16,%ZMM24

0x213726 VMOVUPD	%ZMM24,(%R8,%RDX,1)    [1]

0x21372d VMOVUPD	%ZMM18,0x40(%R8,%RDX,1)    [1]

0x213735 VMOVUPD	%ZMM17,0x80(%R8,%RDX,1)    [1]

0x21373d ADD	$0xc0,%RDX

0x213744 CMP	%RDX,%R13

0x213747 JNE	213650

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 76 - 78

--------------------------------------------------------------------------------

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.71
Bottlenecks	P11, P12,
Function	advanceVelocity.omp_outlined
Source	timestep.c:76-78
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	9.00
Front-end cycles	5.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	3.00
P11 cycles	9.00
P12 cycles	9.00
P13 cycles	0.00
P14 cycles	3.00
P15 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	42.00
Nb loads	7.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	5.33
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	24.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.89
Bytes prefetched	0.00
Bytes loaded	392.00
Bytes stored	192.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	97.30
Vectorization ratio load	85.71
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	96.00
Vector-efficiency ratio all	97.64
Vector-efficiency ratio load	87.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	96.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.71
Bottlenecks	P11, P12,
Function	advanceVelocity.omp_outlined
Source	timestep.c:76-78
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	9.00
Front-end cycles	5.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	3.00
P11 cycles	9.00
P12 cycles	9.00
P13 cycles	0.00
P14 cycles	3.00
P15 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	42.00
Nb loads	7.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	5.33
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	24.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.89
Bytes prefetched	0.00
Bytes loaded	392.00
Bytes stored	192.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	97.30
Vectorization ratio load	85.71
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	96.00
Vector-efficiency ratio all	97.64
Vector-efficiency ratio load	87.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	96.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advanceVelocity.omp_outlined
Source file and lines	timestep.c:76-78
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76-78.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all SSE/AVX instructions).

Details

97% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

85% of SSE/AVX loads are used in vector version.
96% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.00 to 5.25 cycles (1.71x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 24 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78

Vector unaligned load/store instructions

Detected 9 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 9 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

3 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 48 FP arithmetical operations:

24: addition or subtraction (all inside FMA instructions)
24: multiply (all inside FMA instructions)

The binary loop is loading 392 bytes (49 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	40
nb uops	42
loop length	253
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	22
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.25 cycles
front end	5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	2.50	2.50	2.50	2.50	3.00	9.00	9.00	0.00	3.00	3.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	2.50	2.50	2.50	2.50	3.00	9.00	9.00	0.00	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Dispatch	9.00
Data deps.	1.00
Overall L1	9.00

Vectorization ratios

all	97%
load	85%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	96%

Vector efficiency ratios

all	97%
load	87%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	96%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

17% of peak load performance is reached (43.56 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (21.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 213650

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R15,%RDX,1),%ZMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R15,%RDX,1),%ZMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R8,%RDX,1),%ZMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%R15,%RDX,1),%ZMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%R8,%RDX,1),%ZMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD (%RBX),%ZMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %ZMM18,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM5,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM18,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM7,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM18,%ZMM9,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVUPD (%R8,%RDX,1),%ZMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM6,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM8,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM10,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM18,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM5,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM18,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM7,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM18,%ZMM9,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM23,%ZMM6,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM23,%ZMM8,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM23,%ZMM10,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM17,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM22,%ZMM17,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM17,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM25,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM24,%ZMM11,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM24,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM25,%ZMM13,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM25,%ZMM15,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM12,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM14,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM16,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVUPD %ZMM24,(%R8,%RDX,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	1	4	1	vect (100.0%)
VMOVUPD %ZMM18,0x40(%R8,%RDX,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	1	4	1	vect (100.0%)
VMOVUPD %ZMM17,0x80(%R8,%RDX,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	1	4	1	vect (100.0%)
ADD $0xc0,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 213650 <advanceVelocity.omp_outlined+0x2e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A

Function	advanceVelocity.omp_outlined
Source file and lines	timestep.c:76-78
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all SSE/AVX instructions).

Details

97% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

85% of SSE/AVX loads are used in vector version.
96% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 24 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78

Vector unaligned load/store instructions

Detected 9 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 9 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

3 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 48 FP arithmetical operations:

24: addition or subtraction (all inside FMA instructions)
24: multiply (all inside FMA instructions)

The binary loop is loading 392 bytes (49 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	40
nb uops	42
loop length	253
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	22
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.25 cycles
front end	5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	2.50	2.50	2.50	2.50	3.00	9.00	9.00	0.00	3.00	3.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	2.50	2.50	2.50	2.50	3.00	9.00	9.00	0.00	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Dispatch	9.00
Data deps.	1.00
Overall L1	9.00

Vectorization ratios

all	97%
load	85%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	96%

Vector efficiency ratios

all	97%
load	87%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	96%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

17% of peak load performance is reached (43.56 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (21.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 213650

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R15,%RDX,1),%ZMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R15,%RDX,1),%ZMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R8,%RDX,1),%ZMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%R15,%RDX,1),%ZMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%R8,%RDX,1),%ZMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD (%RBX),%ZMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %ZMM18,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM5,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM18,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM7,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM18,%ZMM9,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVUPD (%R8,%RDX,1),%ZMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM6,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM8,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM10,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM18,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM5,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM18,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM7,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM18,%ZMM9,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM23,%ZMM6,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM23,%ZMM8,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM23,%ZMM10,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM17,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM22,%ZMM17,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM17,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM25,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM24,%ZMM11,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM24,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM25,%ZMM13,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM25,%ZMM15,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM12,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM14,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM16,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVUPD %ZMM24,(%R8,%RDX,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	1	4	1	vect (100.0%)
VMOVUPD %ZMM18,0x40(%R8,%RDX,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	1	4	1	vect (100.0%)
VMOVUPD %ZMM17,0x80(%R8,%RDX,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	1	4	1	vect (100.0%)
ADD $0xc0,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 213650 <advanceVelocity.omp_outlined+0x2e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code