OV - exec - Function advanceVelocity.omp

	Function: advanceVelocity.omp_outlined	Module: exec	Source: timestep.c:71-78	Coverage (incl. loops): 1.13% \| (excl. loops): 0.04%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

0x213370 PUSH	%RBP

0x213371 MOV	%RSP,%RBP

0x213374 PUSH	%R15

0x213376 PUSH	%R14

0x213378 PUSH	%R13

0x21337a PUSH	%R12

0x21337c PUSH	%RBX

0x21337d SUB	$0x48,%RSP

0x213381 MOV	(%RDX),%R15D

0x213384 TEST	%R15D,%R15D

0x213387 JLE	213421

0x21338d MOV	(%RDI),%ESI

0x21338f LEA	0x3722(%RIP),%R14

0x213396 DEC	%R15D

0x213399 MOV	%R8,%RBX

0x21339c MOV	%RCX,%R12

0x21339f MOVL	$0,-0x34(%RBP)

0x2133a6 MOVL	$0x1,-0x4c(%RBP)

0x2133ad MOVL	$0,-0x48(%RBP)

0x2133b4 MOV	%R15D,-0x30(%RBP)

0x2133b8 SUB	$0x8,%RSP

0x2133bc MOV	$0x1590,%RDI

0x2133c6 LEA	-0x4c(%RBP),%RAX

0x2133ca LEA	-0x48(%RBP),%RCX

0x2133ce LEA	-0x34(%RBP),%R8

0x2133d2 LEA	-0x30(%RBP),%R9

0x2133d6 MOV	%ESI,-0x44(%RBP)

0x2133d9 MOV	$0x22,%EDX

0x2133de ADD	%R14,%RDI

0x2133e1 PUSH	$0x1

0x2133e3 PUSH	$0x1

0x2133e5 PUSH	%RAX

0x2133e6 CALL	214700 <@plt_start@+0x180>

0x2133eb ADD	$0x20,%RSP

0x2133ef MOV	-0x30(%RBP),%EAX

0x2133f2 CMP	%R15D,%EAX

0x2133f5 CMOVL	%EAX,%R15D

0x2133f9 MOVSXD	-0x34(%RBP),%RAX

0x2133fd MOV	%R15D,-0x30(%RBP)

0x213401 CMP	%R15D,%EAX

0x213404 JLE	213430

0x213406 MOV	-0x44(%RBP),%ESI

0x213409 MOV	$0x15a8,%RAX

0x213413 ADD	%RAX,%R14

0x213416 MOV	%R14,%RDI

0x213419 VZEROUPPER

0x21341c CALL	214710 <@plt_start@+0x190>

0x213421 ADD	$0x48,%RSP

0x213425 POP	%RBX

0x213426 POP	%R12

0x213428 POP	%R13

0x21342a POP	%R14

0x21342c POP	%R15

0x21342e POP	%RBP

0x21342f RET

0x213430 MOV	(%R12),%RDI

0x213434 MOV	%EAX,%ESI

0x213436 MOVSXD	%R15D,%R9

0x213439 LEA	0x8(%RBX),%R8

0x21343d SAL	$0x6,%ESI

0x213440 MOV	%R9,-0x68(%RBP)

0x213444 MOV	%R8,-0x60(%RBP)

0x213448 MOV	0x18(%RDI),%RCX

0x21344c MOV	%RDI,-0x58(%RBP)

0x213450 MOV	0x78(%RCX),%RDX

0x213454 MOV	$-0x118d8,%RCX

0x21345e VMOVAPD	(%R14,%RCX,1),%YMM0

0x213464 MOV	$-0x11898,%RCX

0x21346e VMOVAPD	(%R14,%RCX,1),%YMM1

0x213474 MOV	$-0x118f8,%RCX

0x21347e VMOVAPD	(%R14,%RCX,1),%YMM2

0x213484 MOV	$-0x11918,%RCX

0x21348e VMOVAPD	(%R14,%RCX,1),%YMM3

0x213494 MOV	$-0x10eb8,%RCX

0x21349e VMOVAPD	(%R14,%RCX,1),%ZMM4

0x2134a5 MOV	$-0x111b8,%RCX

0x2134af MOV	%RDX,-0x40(%RBP)

0x2134b3 VMOVAPD	(%R14,%RCX,1),%ZMM5

0x2134ba MOV	$-0x11178,%RCX

0x2134c4 VMOVAPD	(%R14,%RCX,1),%ZMM6

0x2134cb MOV	$-0x11138,%RCX

0x2134d5 VMOVAPD	(%R14,%RCX,1),%ZMM7

0x2134dc MOV	$-0x110f8,%RCX

0x2134e6 VMOVAPD	(%R14,%RCX,1),%ZMM8

0x2134ed MOV	$-0x110b8,%RCX

0x2134f7 VMOVAPD	(%R14,%RCX,1),%ZMM9

0x2134fe MOV	$-0x11078,%RCX

0x213508 VMOVAPD	(%R14,%RCX,1),%ZMM10

0x21350f MOV	$-0x11038,%RCX

0x213519 VMOVAPD	(%R14,%RCX,1),%ZMM11

0x213520 MOV	$-0x10ff8,%RCX

0x21352a VMOVAPD	(%R14,%RCX,1),%ZMM12

0x213531 MOV	$-0x10fb8,%RCX

0x21353b VMOVAPD	(%R14,%RCX,1),%ZMM13

0x213542 MOV	$-0x10f78,%RCX

0x21354c VMOVAPD	(%R14,%RCX,1),%ZMM14

0x213553 MOV	$-0x10f38,%RCX

0x21355d VMOVAPD	(%R14,%RCX,1),%ZMM15

0x213564 MOV	$-0x10ef8,%RCX

0x21356e VMOVAPD	(%R14,%RCX,1),%ZMM16

0x213575 JMP	213594

0x213577 NOPW	(%RAX,%RAX,1)

(107) 0x213580 ADD	$0x40,%ESI

(107) 0x213583 LEA	0x1(%RAX),%RCX

(107) 0x213587 CMP	-0x68(%RBP),%RAX

(107) 0x21358b MOV	%RCX,%RAX

(107) 0x21358e JGE	213406

(107) 0x213594 MOV	(%RDX,%RAX,4),%R9D

(107) 0x213598 TEST	%R9D,%R9D

(107) 0x21359b JLE	213580

(107) 0x21359d MOV	0x20(%RDI),%RCX

(107) 0x2135a1 MOVSXD	%ESI,%R12

(107) 0x2135a4 XOR	%R13D,%R13D

(107) 0x2135a7 MOV	0x20(%RCX),%R10

(107) 0x2135ab MOV	0x28(%RCX),%R11

(107) 0x2135af CMP	$0x4,%R9D

(107) 0x2135b3 JB	213850

(107) 0x2135b9 LEA	(,%R12,8),%RCX

(107) 0x2135c1 LEA	(%RCX,%RCX,2),%R15

(107) 0x2135c5 LEA	-0x1(%R9),%ECX

(107) 0x2135c9 ADD	%R12,%RCX

(107) 0x2135cc SAL	$0x3,%RCX

(107) 0x2135d0 LEA	(%R10,%R15,1),%R8

(107) 0x2135d4 ADD	%R11,%R15

(107) 0x2135d7 CMP	-0x60(%RBP),%R8

(107) 0x2135db LEA	(%RCX,%RCX,2),%RCX

(107) 0x2135df LEA	0x18(%R10,%RCX,1),%RDX

(107) 0x2135e4 LEA	0x18(%R11,%RCX,1),%RCX

(107) 0x2135e9 SETBB	-0x29(%RBP)

(107) 0x2135ed CMP	%RBX,%RDX

(107) 0x2135f0 SETA	%DIL

(107) 0x2135f4 CMP	%RCX,%R8

(107) 0x2135f7 SETB	%CL

(107) 0x2135fa CMP	%RDX,%R15

(107) 0x2135fd SETB	%DL

(107) 0x213600 TEST	%DIL,-0x29(%RBP)

(107) 0x213604 JNE	213623

(107) 0x213606 AND	%DL,%CL

(107) 0x213608 MOV	-0x58(%RBP),%RDI

(107) 0x21360c MOV	-0x40(%RBP),%RDX

(107) 0x213610 JNE	213850

(107) 0x213616 CMP	$0x8,%R9D

(107) 0x21361a JAE	213630

(107) 0x21361c XOR	%ECX,%ECX

(107) 0x21361e JMP	21376b

(107) 0x213623 MOV	-0x58(%RBP),%RDI

(107) 0x213627 MOV	-0x40(%RBP),%RDX

(107) 0x21362b JMP	213850

(107) 0x213630 MOV	%R9D,%EDX

(107) 0x213633 SHR	$0x3,%EDX

(107) 0x213636 MOV	%R9D,%ECX

(107) 0x213639 AND	$-0x8,%ECX

(107) 0x21363c SAL	$0x6,%RDX

(107) 0x213640 LEA	(%RDX,%RDX,2),%R13

(107) 0x213644 XOR	%EDX,%EDX

(107) 0x213646 NOPW	%CS:(%RAX,%RAX,1)

  (109) 0x213650 VMOVUPD	(%R15,%RDX,1),%ZMM18

  (109) 0x213657 VMOVUPD	0x40(%R15,%RDX,1),%ZMM19

  (109) 0x21365f VMOVUPD	0x40(%R8,%RDX,1),%ZMM26

  (109) 0x213667 VMOVUPD	0x80(%R15,%RDX,1),%ZMM20

  (109) 0x21366f VMOVUPD	0x80(%R8,%RDX,1),%ZMM23

  (109) 0x213677 VBROADCASTSD	(%RBX),%ZMM17

  (109) 0x21367d VMOVAPD	%ZMM18,%ZMM21

  (109) 0x213683 VPERMT2PD	%ZMM19,%ZMM5,%ZMM21

  (109) 0x213689 VMOVAPD	%ZMM18,%ZMM22

  (109) 0x21368f VPERMT2PD	%ZMM19,%ZMM7,%ZMM22

  (109) 0x213695 VPERMT2PD	%ZMM18,%ZMM9,%ZMM19

  (109) 0x21369b VMOVUPD	(%R8,%RDX,1),%ZMM18

  (109) 0x2136a2 VPERMT2PD	%ZMM20,%ZMM6,%ZMM21

  (109) 0x2136a8 VPERMT2PD	%ZMM20,%ZMM8,%ZMM22

  (109) 0x2136ae VPERMT2PD	%ZMM20,%ZMM10,%ZMM19

  (109) 0x2136b4 VMOVAPD	%ZMM18,%ZMM24

  (109) 0x2136ba VPERMT2PD	%ZMM26,%ZMM5,%ZMM24

  (109) 0x2136c0 VMOVAPD	%ZMM18,%ZMM25

  (109) 0x2136c6 VPERMT2PD	%ZMM26,%ZMM7,%ZMM25

  (109) 0x2136cc VPERMT2PD	%ZMM18,%ZMM9,%ZMM26

  (109) 0x2136d2 VPERMT2PD	%ZMM23,%ZMM6,%ZMM24

  (109) 0x2136d8 VPERMT2PD	%ZMM23,%ZMM8,%ZMM25

  (109) 0x2136de VPERMT2PD	%ZMM23,%ZMM10,%ZMM26

  (109) 0x2136e4 VFMADD231PD	%ZMM21,%ZMM17,%ZMM24

  (109) 0x2136ea VFMADD231PD	%ZMM22,%ZMM17,%ZMM25

  (109) 0x2136f0 VFMADD231PD	%ZMM19,%ZMM17,%ZMM26

  (109) 0x2136f6 VMOVAPD	%ZMM25,%ZMM17

  (109) 0x2136fc VPERMT2PD	%ZMM24,%ZMM11,%ZMM17

  (109) 0x213702 VMOVAPD	%ZMM24,%ZMM18

  (109) 0x213708 VPERMT2PD	%ZMM25,%ZMM13,%ZMM18

  (109) 0x21370e VPERMT2PD	%ZMM25,%ZMM15,%ZMM24

  (109) 0x213714 VPERMT2PD	%ZMM26,%ZMM12,%ZMM17

  (109) 0x21371a VPERMT2PD	%ZMM26,%ZMM14,%ZMM18

  (109) 0x213720 VPERMT2PD	%ZMM26,%ZMM16,%ZMM24

  (109) 0x213726 VMOVUPD	%ZMM24,(%R8,%RDX,1)

  (109) 0x21372d VMOVUPD	%ZMM18,0x40(%R8,%RDX,1)

  (109) 0x213735 VMOVUPD	%ZMM17,0x80(%R8,%RDX,1)

  (109) 0x21373d ADD	$0xc0,%RDX

  (109) 0x213744 CMP	%RDX,%R13

  (109) 0x213747 JNE	213650

(107) 0x21374d MOV	-0x40(%RBP),%RDX

(107) 0x213751 CMP	%R9,%RCX

(107) 0x213754 JE	213580

(107) 0x21375a TEST	$0x4,%R9B

(107) 0x21375e JNE	21376b

(107) 0x213760 ADD	%RCX,%R12

(107) 0x213763 MOV	%ECX,%R13D

(107) 0x213766 JMP	213850

(107) 0x21376b MOV	%R9D,%R13D

(107) 0x21376e AND	$-0x4,%R13D

(107) 0x213772 MOV	%RCX,%RDX

(107) 0x213775 LEA	(%R13,%R12,1),%R8

(107) 0x21377a ADD	%RCX,%R12

(107) 0x21377d SUB	%R13,%RDX

(107) 0x213780 SAL	$0x3,%R12

(107) 0x213784 LEA	(%R12,%R12,2),%RCX

(107) 0x213788 NOPL	(%RAX,%RAX,1)

  (110) 0x213790 VMOVUPD	(%R11,%RCX,1),%ZMM18

  (110) 0x213797 VMOVUPD	0x40(%R11,%RCX,1),%YMM19

  (110) 0x21379f VMOVUPD	0x40(%R10,%RCX,1),%YMM22

  (110) 0x2137a7 VBROADCASTSD	(%RBX),%YMM17

  (110) 0x2137ad VMOVAPD	%ZMM18,%ZMM20

  (110) 0x2137b3 VMOVAPD	%ZMM18,%ZMM21

  (110) 0x2137b9 VPERMT2PD	%ZMM19,%ZMM0,%ZMM20

  (110) 0x2137bf VPERMT2PD	%ZMM19,%ZMM1,%ZMM21

  (110) 0x2137c5 VPERMT2PD	%ZMM19,%ZMM2,%ZMM18

  (110) 0x2137cb VMOVUPD	(%R10,%RCX,1),%ZMM19

  (110) 0x2137d2 VMOVAPD	%ZMM19,%ZMM23

  (110) 0x2137d8 VPERMT2PD	%ZMM22,%ZMM0,%ZMM23

  (110) 0x2137de VMOVAPD	%ZMM19,%ZMM24

  (110) 0x2137e4 VPERMT2PD	%ZMM22,%ZMM1,%ZMM24

  (110) 0x2137ea VPERMT2PD	%ZMM22,%ZMM2,%ZMM19

  (110) 0x2137f0 VFMADD231PD	%YMM20,%YMM17,%YMM23

  (110) 0x2137f6 VFMADD231PD	%YMM21,%YMM17,%YMM24

  (110) 0x2137fc VFMADD231PD	%YMM18,%YMM17,%YMM19

  (110) 0x213802 VINSERTF64X4	$0x1,%YMM24,%ZMM23,%ZMM17

  (110) 0x213809 VMOVAPD	%ZMM17,%ZMM18

  (110) 0x21380f VPERMT2PD	%ZMM19,%ZMM3,%ZMM18

  (110) 0x213815 VPERMT2PD	%ZMM19,%ZMM4,%ZMM17

  (110) 0x21381b VMOVUPD	%ZMM17,(%R10,%RCX,1)

  (110) 0x213822 VMOVUPD	%YMM18,0x40(%R10,%RCX,1)

  (110) 0x21382a ADD	$0x60,%RCX

  (110) 0x21382e ADD	$0x4,%RDX

  (110) 0x213832 JNE	213790

(107) 0x213838 MOV	-0x40(%RBP),%RDX

(107) 0x21383c MOV	%R8,%R12

(107) 0x21383f CMP	%R9,%R13

(107) 0x213842 JE	213580

(107) 0x213848 NOPL	(%RAX,%RAX,1)

(107) 0x213850 LEA	(%R12,%R12,2),%RCX

(107) 0x213854 SUB	%R13D,%R9D

(107) 0x213857 LEA	0x10(,%RCX,8),%RCX

(107) 0x21385f NOP

  (108) 0x213860 VMOVSD	(%RBX),%XMM17

  (108) 0x213866 VMOVSD	-0x10(%R11,%RCX,1),%XMM18

  (108) 0x21386e VFMADD213SD	-0x10(%R10,%RCX,1),%XMM17,%XMM18

  (108) 0x213876 VMOVSD	%XMM18,-0x10(%R10,%RCX,1)

  (108) 0x21387e VMOVSD	(%RBX),%XMM17

  (108) 0x213884 VMOVSD	-0x8(%R11,%RCX,1),%XMM18

  (108) 0x21388c VFMADD213SD	-0x8(%R10,%RCX,1),%XMM17,%XMM18

  (108) 0x213894 VMOVSD	%XMM18,-0x8(%R10,%RCX,1)

  (108) 0x21389c VMOVSD	(%RBX),%XMM17

  (108) 0x2138a2 VMOVSD	(%R11,%RCX,1),%XMM18

  (108) 0x2138a9 VFMADD213SD	(%R10,%RCX,1),%XMM17,%XMM18

  (108) 0x2138b0 VMOVSD	%XMM18,(%R10,%RCX,1)

  (108) 0x2138b7 ADD	$0x18,%RCX

  (108) 0x2138bb DEC	%R9D

  (108) 0x2138be JNE	213860

(107) 0x2138c0 JMP	213580

0x2138c5 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.04% of application time for run aocc_2

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.00 to 4.50 cycles (2.89x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 43% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 13.00 to 10.55 cycles (1.23x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1004 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	103
nb uops	104
loop length	539
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	4
used zmm registers	13
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.00 cycles
front end	13.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.83	7.83	7.83	7.83	7.83	7.83	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	7.83	7.83	7.83	7.83	7.83	7.83	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.00
Dispatch	9.25
Overall L1	13.00

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	46%
load	85%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	8%
load	6%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	88%
load	88%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	43%
load	75%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.00 cycles. At this rate:

30% of peak load performance is reached (77.23 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.31 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.00 to 9.25 cycles (1.41x speedup).

ASM code

In the binary file, the address of the function is: 213370

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R15D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 213421 <advanceVelocity.omp_outlined+0xb1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
LEA 0x3722(%RIP),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
DEC %R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0x1,-0x4c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R15D,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x1590,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x4c(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x48(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x34(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %R14,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 214700 <@plt_start@+0x180>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVL %EAX,%R15D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOVSXD -0x34(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %R15D,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 213430 <advanceVelocity.omp_outlined+0xc0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV $0x15a8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 214710 <@plt_start@+0x190>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV (%R12),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOVSXD %R15D,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x8(%RBX),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOV %R9,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R8,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x18(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x78(%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV $-0x118d8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
MOV $-0x11898,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
MOV $-0x118f8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
MOV $-0x11918,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
MOV $-0x10eb8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x111b8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
VMOVAPD (%R14,%RCX,1),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x11178,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x11138,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x110f8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x110b8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x11078,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x11038,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x10ff8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x10fb8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x10f78,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x10f38,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x10ef8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
JMP 213594 <advanceVelocity.omp_outlined+0x224>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.04% of application time for run aocc_2

Source file and lines	timestep.c:71-78
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.00 to 4.50 cycles (2.89x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1004 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	103
nb uops	104
loop length	539
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	4
used zmm registers	13
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.00 cycles
front end	13.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.83	7.83	7.83	7.83	7.83	7.83	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	7.83	7.83	7.83	7.83	7.83	7.83	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.00
Dispatch	9.25
Overall L1	13.00

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	46%
load	85%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	8%
load	6%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	88%
load	88%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	43%
load	75%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.00 cycles. At this rate:

30% of peak load performance is reached (77.23 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.31 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 213370

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R15D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 213421 <advanceVelocity.omp_outlined+0xb1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
LEA 0x3722(%RIP),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
DEC %R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0x1,-0x4c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R15D,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x1590,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x4c(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x48(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x34(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %R14,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 214700 <@plt_start@+0x180>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVL %EAX,%R15D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOVSXD -0x34(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %R15D,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 213430 <advanceVelocity.omp_outlined+0xc0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV $0x15a8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 214710 <@plt_start@+0x190>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV (%R12),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOVSXD %R15D,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x8(%RBX),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOV %R9,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R8,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x18(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x78(%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV $-0x118d8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
MOV $-0x11898,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
MOV $-0x118f8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
MOV $-0x11918,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
MOV $-0x10eb8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x111b8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
VMOVAPD (%R14,%RCX,1),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x11178,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x11138,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x110f8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x110b8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x11078,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x11038,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x10ff8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x10fb8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x10f78,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x10f38,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV $-0x10ef8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VMOVAPD (%R14,%RCX,1),%ZMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
JMP 213594 <advanceVelocity.omp_outlined+0x224>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

Name	Coverage (%)	Time (s)
▼advanceVelocity.omp_outlined–	1.13	0.09
▼Loop 107 - timestep.c:72-78 - exec–	0.00	0.01
○Loop 109 - timestep.c:76-78 - exec	0.88	0.07
○Loop 108 - timestep.c:74-78 - exec	0.15	0.02
○Loop 110 - timestep.c:76-78 - exec	0.06	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code