OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:211-385 [...]	Coverage (incl. loops): 0.25% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 211 - 385

--------------------------------------------------------------------------------

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

[...]

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

[...]

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

372:    {

373:       if (iz == gridSize[2]) iz = gridSize[2] - 1;

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x20f910 PUSH	%RBP

0x20f911 MOV	%RSP,%RBP

0x20f914 PUSH	%R15

0x20f916 PUSH	%R14

0x20f918 PUSH	%R13

0x20f91a PUSH	%R12

0x20f91c PUSH	%RBX

0x20f91d SUB	$0x18,%RSP

0x20f921 MOV	0xc(%RDI),%R9D

0x20f925 CMP	%R9D,0x14(%RDI)

0x20f929 JLE	20f957

0x20f92b MOV	0x78(%RDI),%RCX

0x20f92f MOVSXD	%R9D,%RAX

0x20f932 NOPW	%CS:(%RAX,%RAX,1)

(92) 0x20f940 MOVL	$0,(%RCX,%RAX,4)

(92) 0x20f947 INC	%RAX

(92) 0x20f94a MOVSXD	0x14(%RDI),%RDX

(92) 0x20f94e CMP	%RDX,%RAX

(92) 0x20f951 JL	20f940

0x20f953 MOV	0xc(%RDI),%R9D

0x20f957 TEST	%R9D,%R9D

0x20f95a JLE	20fcfc

0x20f960 MOV	0x78(%RDI),%R11

0x20f964 XOR	%ECX,%ECX

0x20f966 JMP	20f97f

0x20f968 NOPL	(%RAX,%RAX,1)

(90) 0x20f970 INC	%RCX

(90) 0x20f973 MOVSXD	%R9D,%RAX

(90) 0x20f976 CMP	%RAX,%RCX

(90) 0x20f979 JGE	20fcfc

(90) 0x20f97f CMPL	$0,(%R11,%RCX,4)

(90) 0x20f984 JLE	20f970

(90) 0x20f986 MOVSXD	%ECX,%RAX

(90) 0x20f989 XOR	%EDX,%EDX

(90) 0x20f98b SAL	$0x6,%RAX

(90) 0x20f98f MOV	%RAX,-0x38(%RBP)

(90) 0x20f993 JMP	20f9b0

0x20f995 NOPW	%CS:(%RAX,%RAX,1)

  (91) 0x20f9a0 MOV	-0x30(%RBP),%RDX

  (91) 0x20f9a4 INC	%EDX

  (91) 0x20f9a6 MOV	0x78(%RDI),%R11

  (91) 0x20f9aa CMP	%EDX,(%R11,%RCX,4)

  (91) 0x20f9ae JLE	20f970

  (91) 0x20f9b0 MOV	-0x38(%RBP),%RAX

  (91) 0x20f9b4 MOV	0x18(%RSI),%RBX

  (91) 0x20f9b8 VMOVSD	0x30(%RDI),%XMM1

  (91) 0x20f9bd ADD	%EDX,%EAX

  (91) 0x20f9bf MOVSXD	%EAX,%R10

  (91) 0x20f9c2 LEA	(%R10,%R10,2),%R14

  (91) 0x20f9c6 VMOVSD	(%RBX,%R14,8),%XMM0

  (91) 0x20f9cc VUCOMISD	%XMM0,%XMM1

  (91) 0x20f9d0 JBE	20fa00

  (91) 0x20f9d2 VSUBSD	0x18(%RDI),%XMM0,%XMM0

  (91) 0x20f9d7 MOV	(%RDI),%R13D

  (91) 0x20f9da VMULSD	0x60(%RDI),%XMM0,%XMM0

  (91) 0x20f9df VROUNDSD	$0x9,%XMM0,%XMM0,%XMM0

  (91) 0x20f9e5 VCVTTSD2SI	%XMM0,%R12D

  (91) 0x20f9e9 CMP	%R12D,%R13D

  (91) 0x20f9ec JNE	20fa06

  (91) 0x20f9ee LEA	-0x1(%R13),%R12D

  (91) 0x20f9f2 JMP	20fa06

0x20f9f4 NOPW	%CS:(%RAX,%RAX,1)

  (91) 0x20fa00 MOV	(%RDI),%R13D

  (91) 0x20fa03 MOV	%R13D,%R12D

  (91) 0x20fa06 VMOVSD	0x8(%RBX,%R14,8),%XMM0

  (91) 0x20fa0d MOV	0x4(%RDI),%EAX

  (91) 0x20fa10 MOV	%RDX,-0x30(%RBP)

  (91) 0x20fa14 VSUBSD	0x20(%RDI),%XMM0,%XMM1

  (91) 0x20fa19 VMULSD	0x68(%RDI),%XMM1,%XMM1

  (91) 0x20fa1e VROUNDSD	$0x9,%XMM1,%XMM1,%XMM1

  (91) 0x20fa24 VCVTTSD2SI	%XMM1,%R15D

  (91) 0x20fa28 CMP	%R15D,%EAX

  (91) 0x20fa2b JNE	20fa31

  (91) 0x20fa2d LEA	-0x1(%RAX),%R15D

  (91) 0x20fa31 VMOVSD	0x38(%RDI),%XMM1

  (91) 0x20fa36 VMOVSD	0x10(%RBX,%R14,8),%XMM2

  (91) 0x20fa3d VMOVSD	0x40(%RDI),%XMM3

  (91) 0x20fa42 MOV	0x8(%RDI),%EDX

  (91) 0x20fa45 VUCOMISD	%XMM0,%XMM1

  (91) 0x20fa49 CMOVBE	%EAX,%R15D

  (91) 0x20fa4d VUCOMISD	%XMM2,%XMM3

  (91) 0x20fa51 JBE	20fab0

  (91) 0x20fa53 VSUBSD	0x28(%RDI),%XMM2,%XMM2

  (91) 0x20fa58 VMULSD	0x70(%RDI),%XMM2,%XMM2

  (91) 0x20fa5d VROUNDSD	$0x9,%XMM2,%XMM2,%XMM2

  (91) 0x20fa63 VCVTTSD2SI	%XMM2,%R8D

  (91) 0x20fa67 CMP	%R8D,%EDX

  (91) 0x20fa6a JNE	20fa70

  (91) 0x20fa6c LEA	-0x1(%RDX),%R8D

  (91) 0x20fa70 CMP	$-0x1,%R8D

  (91) 0x20fa74 JE	20fae1

  (91) 0x20fa76 VUCOMISD	%XMM0,%XMM1

  (91) 0x20fa7a JA	20fb0b

  (91) 0x20fa80 IMUL	%EDX,%EAX

  (91) 0x20fa83 ADD	$0x2,%R13D

  (91) 0x20fa87 ADD	%EDX,%R8D

  (91) 0x20fa8a IMUL	%R13D,%R8D

  (91) 0x20fa8e LEA	(%R12,%RAX,2),%EAX

  (91) 0x20fa92 ADD	%R9D,%EAX

  (91) 0x20fa95 LEA	0x1(%R8,%RAX,1),%R15D

  (91) 0x20fa9a TEST	%R15D,%R15D

  (91) 0x20fa9d JNS	20fb80

0x20faa3 JMP	20fd0b

0x20faa8 NOPL	(%RAX,%RAX,1)

  (91) 0x20fab0 LEA	(%RDX,%RDX,1),%R8D

  (91) 0x20fab4 LEA	(%R15,%RDX,2),%EDX

  (91) 0x20fab8 ADD	$0x2,%R13D

  (91) 0x20fabc ADD	%R9D,%R12D

  (91) 0x20fabf IMUL	%EAX,%R8D

  (91) 0x20fac3 LEA	0x3(%RAX,%RDX,1),%EAX

  (91) 0x20fac7 IMUL	%R13D,%EAX

  (91) 0x20facb ADD	%R8D,%R12D

  (91) 0x20face LEA	0x1(%RAX,%R12,1),%R15D

  (91) 0x20fad3 TEST	%R15D,%R15D

  (91) 0x20fad6 JNS	20fb80

0x20fadc JMP	20fd0b

  (91) 0x20fae1 LEA	(%RDX,%RDX,1),%R8D

  (91) 0x20fae5 LEA	0x1(%R15,%RDX,2),%EDX

  (91) 0x20faea ADD	$0x2,%R13D

  (91) 0x20faee ADD	%R9D,%R12D

  (91) 0x20faf1 IMUL	%R8D,%EAX

  (91) 0x20faf5 IMUL	%R13D,%EDX

  (91) 0x20faf9 ADD	%EAX,%R12D

  (91) 0x20fafc LEA	0x1(%RDX,%R12,1),%R15D

  (91) 0x20fb01 TEST	%R15D,%R15D

  (91) 0x20fb04 JNS	20fb80

0x20fb06 JMP	20fd0b

  (91) 0x20fb0b CMP	$-0x1,%R15D

  (91) 0x20fb0f JE	20fb2c

  (91) 0x20fb11 CMP	%R12D,%R13D

  (91) 0x20fb14 JNE	20fb4d

  (91) 0x20fb16 ADD	%R8D,%EDX

  (91) 0x20fb19 ADD	%R9D,%R15D

  (91) 0x20fb1c IMUL	%EDX,%EAX

  (91) 0x20fb1f ADD	%EAX,%R15D

  (91) 0x20fb22 TEST	%R15D,%R15D

  (91) 0x20fb25 JNS	20fb80

0x20fb27 JMP	20fd0b

  (91) 0x20fb2c IMUL	%EAX,%EDX

  (91) 0x20fb2f ADD	$0x2,%R13D

  (91) 0x20fb33 IMUL	%R8D,%R13D

  (91) 0x20fb37 LEA	(%R12,%RDX,2),%EAX

  (91) 0x20fb3b ADD	%R9D,%EAX

  (91) 0x20fb3e LEA	0x1(%R13,%RAX,1),%R15D

  (91) 0x20fb43 TEST	%R15D,%R15D

  (91) 0x20fb46 JNS	20fb80

0x20fb48 JMP	20fd0b

  (91) 0x20fb4d IMUL	%R8D,%EAX

  (91) 0x20fb51 ADD	%R15D,%EAX

  (91) 0x20fb54 CMP	$-0x1,%R12D

  (91) 0x20fb58 JE	20fb6e

  (91) 0x20fb5a IMUL	%EAX,%R13D

  (91) 0x20fb5e ADD	%R12D,%R13D

  (91) 0x20fb61 MOV	%R13D,%R15D

  (91) 0x20fb64 TEST	%R15D,%R15D

  (91) 0x20fb67 JNS	20fb80

0x20fb69 JMP	20fd0b

  (91) 0x20fb6e ADD	%R9D,%EAX

  (91) 0x20fb71 MOV	%EAX,%R15D

  (91) 0x20fb74 TEST	%R15D,%R15D

  (91) 0x20fb77 JS	20fd0b

  (91) 0x20fb7d NOPL	(%RAX)

  (91) 0x20fb80 CMP	%R15D,0x14(%RDI)

  (91) 0x20fb84 JLE	20fd43

  (91) 0x20fb8a MOV	%R15D,%EDX

  (91) 0x20fb8d CMP	%RDX,%RCX

  (91) 0x20fb90 JE	20f9a0

  (91) 0x20fb96 LEA	(%RBX,%R14,8),%RAX

  (91) 0x20fb9a MOV	0x8(%RSI),%R14

  (91) 0x20fb9e MOVSXD	(%R11,%RDX,4),%R9

  (91) 0x20fba2 MOVSXD	%R15D,%R8

  (91) 0x20fba5 SAL	$0x6,%R8

  (91) 0x20fba9 MOV	(%R14,%R10,4),%R11D

  (91) 0x20fbad ADD	%R9,%R8

  (91) 0x20fbb0 MOV	%R11D,(%R14,%R8,4)

  (91) 0x20fbb4 MOV	0x10(%RSI),%R9

  (91) 0x20fbb8 MOV	(%R9,%R10,4),%R11D

  (91) 0x20fbbc MOV	%R11D,(%R9,%R8,4)

  (91) 0x20fbc0 LEA	(,%R8,8),%R9

  (91) 0x20fbc8 MOV	0x10(%RAX),%R11

  (91) 0x20fbcc LEA	(%R9,%R9,2),%R9

  (91) 0x20fbd0 MOV	%R11,0x10(%RBX,%R9,1)

  (91) 0x20fbd5 VMOVUPS	(%RAX),%XMM0

  (91) 0x20fbd9 LEA	(,%R10,8),%RAX

  (91) 0x20fbe1 LEA	(%RAX,%RAX,2),%RAX

  (91) 0x20fbe5 VMOVUPS	%XMM0,(%RBX,%R9,1)

  (91) 0x20fbeb MOV	0x20(%RSI),%R11

  (91) 0x20fbef MOV	0x10(%R11,%RAX,1),%RBX

  (91) 0x20fbf4 MOV	%RBX,0x10(%R11,%R9,1)

  (91) 0x20fbf9 VMOVUPS	(%R11,%RAX,1),%XMM0

  (91) 0x20fbff VMOVUPS	%XMM0,(%R11,%R9,1)

  (91) 0x20fc05 MOV	0x28(%RSI),%R11

  (91) 0x20fc09 MOV	0x10(%R11,%RAX,1),%RBX

  (91) 0x20fc0e MOV	%RBX,0x10(%R11,%R9,1)

  (91) 0x20fc13 VMOVUPD	(%R11,%RAX,1),%XMM0

  (91) 0x20fc19 VMOVUPD	%XMM0,(%R11,%R9,1)

  (91) 0x20fc1f MOV	0x30(%RSI),%R9

  (91) 0x20fc23 MOV	(%R9,%R10,8),%R11

  (91) 0x20fc27 MOV	%R11,(%R9,%R8,8)

  (91) 0x20fc2b MOV	0x78(%RDI),%R8

  (91) 0x20fc2f MOV	(%R8,%RDX,4),%R9D

  (91) 0x20fc33 LEA	0x1(%R9),%R11D

  (91) 0x20fc37 MOV	%R11D,(%R8,%RDX,4)

  (91) 0x20fc3b CMP	$0x3f,%R9D

  (91) 0x20fc3f JGE	20fd7b

  (91) 0x20fc45 MOVSXD	(%R8,%RCX,4),%RDX

  (91) 0x20fc49 DEC	%RDX

  (91) 0x20fc4c MOV	%EDX,(%R8,%RCX,4)

  (91) 0x20fc50 TEST	%EDX,%EDX

  (91) 0x20fc52 JE	20fcda

  (91) 0x20fc58 ADD	-0x38(%RBP),%RDX

  (91) 0x20fc5c MOV	0x8(%RSI),%R8

  (91) 0x20fc60 MOV	(%R8,%RDX,4),%R9D

  (91) 0x20fc64 MOV	%R9D,(%R8,%R10,4)

  (91) 0x20fc68 MOV	0x10(%RSI),%R8

  (91) 0x20fc6c MOV	(%R8,%RDX,4),%R9D

  (91) 0x20fc70 MOV	%R9D,(%R8,%R10,4)

  (91) 0x20fc74 LEA	(,%RDX,8),%R9

  (91) 0x20fc7c MOV	0x18(%RSI),%R8

  (91) 0x20fc80 LEA	(%R9,%R9,2),%R9

  (91) 0x20fc84 MOV	0x10(%R8,%R9,1),%R11

  (91) 0x20fc89 MOV	%R11,0x10(%R8,%RAX,1)

  (91) 0x20fc8e VMOVUPS	(%R8,%R9,1),%XMM0

  (91) 0x20fc94 VMOVUPS	%XMM0,(%R8,%RAX,1)

  (91) 0x20fc9a MOV	0x20(%RSI),%R8

  (91) 0x20fc9e MOV	0x10(%R8,%R9,1),%R11

  (91) 0x20fca3 MOV	%R11,0x10(%R8,%RAX,1)

  (91) 0x20fca8 VMOVUPS	(%R8,%R9,1),%XMM0

  (91) 0x20fcae VMOVUPS	%XMM0,(%R8,%RAX,1)

  (91) 0x20fcb4 MOV	0x28(%RSI),%R8

  (91) 0x20fcb8 MOV	0x10(%R8,%R9,1),%R11

  (91) 0x20fcbd MOV	%R11,0x10(%R8,%RAX,1)

  (91) 0x20fcc2 VMOVUPD	(%R8,%R9,1),%XMM0

  (91) 0x20fcc8 VMOVUPD	%XMM0,(%R8,%RAX,1)

  (91) 0x20fcce MOV	0x30(%RSI),%RAX

  (91) 0x20fcd2 MOV	(%RAX,%RDX,8),%RDX

  (91) 0x20fcd6 MOV	%RDX,(%RAX,%R10,8)

  (91) 0x20fcda MOV	0xc(%RDI),%R9D

  (91) 0x20fcde CMP	%R15D,%R9D

  (91) 0x20fce1 JGE	20fce5

  (91) 0x20fce3 DECL	(%RSI)

  (91) 0x20fce5 MOV	-0x30(%RBP),%RDX

  (91) 0x20fce9 MOV	0x78(%RDI),%R11

  (91) 0x20fced CMP	(%R11,%RCX,4),%EDX

  (91) 0x20fcf1 JL	20f9b0

(90) 0x20fcf7 JMP	20f970

0x20fcfc ADD	$0x18,%RSP

0x20fd00 POP	%RBX

0x20fd01 POP	%R12

0x20fd03 POP	%R13

0x20fd05 POP	%R14

0x20fd07 POP	%R15

0x20fd09 POP	%RBP

0x20fd0a RET

0x20fd0b LEA	0x6da6(%RIP),%RAX

0x20fd12 MOV	$-0x11bd9,%RDI

0x20fd1c MOV	$-0x142e9,%RSI

0x20fd26 MOV	$-0x11d87,%RCX

0x20fd30 MOV	$0xf6,%EDX

0x20fd35 ADD	%RAX,%RDI

0x20fd38 ADD	%RAX,%RSI

0x20fd3b ADD	%RAX,%RCX

0x20fd3e CALL	214680 <@plt_start@+0x100>

0x20fd43 LEA	0x6d6e(%RIP),%RAX

0x20fd4a MOV	$-0x135c7,%RDI

0x20fd54 MOV	$-0x142e9,%RSI

0x20fd5e MOV	$-0x11d87,%RCX

0x20fd68 MOV	$0xf7,%EDX

0x20fd6d ADD	%RAX,%RDI

0x20fd70 ADD	%RAX,%RSI

0x20fd73 ADD	%RAX,%RCX

0x20fd76 CALL	214680 <@plt_start@+0x100>

0x20fd7b LEA	0x6d36(%RIP),%RAX

0x20fd82 MOV	$-0x13ca3,%RDI

0x20fd8c MOV	$-0x142e9,%RSI

0x20fd96 MOV	$-0x1490a,%RCX

0x20fda0 MOV	$0x106,%EDX

0x20fda5 ADD	%RAX,%RDI

0x20fda8 ADD	%RAX,%RSI

0x20fdab ADD	%RAX,%RCX

0x20fdae CALL	214680 <@plt_start@+0x100>

0x20fdb3 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►97.83+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○1.49	timestep	timestep.c:148	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_2

Source file and lines	linkCells.c:211-385
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-247,258-269,288-304,327-334,352,359-365,371-373,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 7.88 to 0.54 cycles (14.67x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes.

General properties

nb instructions	66
nb uops	63
loop length	334
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.88 cycles
front end	7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.00	7.00	7.00	7.00	7.00	7.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	7.00	7.00	7.00	7.00	7.00	7.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.88
Dispatch	7.00
Overall L1	7.88

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	7%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.88 cycles. At this rate:

1% of peak load performance is reached (3.56 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.88 to 7.00 cycles (1.12x speedup).

ASM code

In the binary file, the address of the function is: 20f910

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV 0xc(%RDI),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
CMP %R9D,0x14(%RDI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JLE 20f957 <updateLinkCells+0x47>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSXD %R9D,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0xc(%RDI),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 20fcfc <updateLinkCells+0x3ec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%RDI),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 20f97f <updateLinkCells+0x6f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 20fd0b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 20fd0b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
JMP 20fd0b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
JMP 20fd0b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
JMP 20fd0b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
JMP 20fd0b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
LEA 0x6da6(%RIP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $-0x11bd9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $-0x142e9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x11d87,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CALL 214680 <@plt_start@+0x100>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA 0x6d6e(%RIP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $-0x135c7,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $-0x142e9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x11d87,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CALL 214680 <@plt_start@+0x100>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA 0x6d36(%RIP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $-0x13ca3,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $-0x142e9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x1490a,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x106,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CALL 214680 <@plt_start@+0x100>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_2

Source file and lines	linkCells.c:211-385
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes.

General properties

nb instructions	66
nb uops	63
loop length	334
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.88 cycles
front end	7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.00	7.00	7.00	7.00	7.00	7.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	7.00	7.00	7.00	7.00	7.00	7.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.88
Dispatch	7.00
Overall L1	7.88

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	7%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.88 cycles. At this rate:

1% of peak load performance is reached (3.56 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 20f910

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV 0xc(%RDI),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
CMP %R9D,0x14(%RDI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JLE 20f957 <updateLinkCells+0x47>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSXD %R9D,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0xc(%RDI),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 20fcfc <updateLinkCells+0x3ec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%RDI),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 20f97f <updateLinkCells+0x6f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 20fd0b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 20fd0b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
JMP 20fd0b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
JMP 20fd0b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
JMP 20fd0b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
JMP 20fd0b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
LEA 0x6da6(%RIP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $-0x11bd9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $-0x142e9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x11d87,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CALL 214680 <@plt_start@+0x100>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA 0x6d6e(%RIP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $-0x135c7,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $-0x142e9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x11d87,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CALL 214680 <@plt_start@+0x100>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA 0x6d36(%RIP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $-0x13ca3,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $-0x142e9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x1490a,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x106,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CALL 214680 <@plt_start@+0x100>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.25	0.02
▼Loop 90 - linkCells.c:211-373 - exec–	0.00	0.01
○Loop 91 - linkCells.c:211-373 - exec	0.25	1.83
○Loop 92 - linkCells.c:384-385 - exec	0.00	0.00

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Vectorization

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code