OV - exec - Loop 91

	Loop Id: 91	Module: exec	Source: ljForce.c:178-216 [...]	Coverage: 0.28%

0x40e4d2 MOV	(%R10),%ESI

0x40e4d5 TEST	%ESI,%ESI

0x40e4d7 JS	40eb70

0x40e4dd MOVSXD	%ESI,%R15

0x40e4e0 VMOVQ	%XMM24,%RAX

0x40e4e6 VMOVD	%XMM23,%EDI

0x40e4ec MOV	(%RAX,%R15,4),%R11D

0x40e4f0 TEST	%EDI,%EDI

0x40e4f2 JLE	40e5e0

0x40e4f8 MOV	-0x34(%RBP),%EBX

0x40e4fb LEA	(%R15,%R15,2),%R8

0x40e4ff MOV	-0x40(%RBP),%R14

0x40e503 SAL	$0x6,%ESI

0x40e506 SAL	$0x9,%R8

0x40e50a MOV	%EBX,%R13D

0x40e50d NOT	%EBX

0x40e50f LEA	(%R11,%RSI,1),%EDX

0x40e513 ADD	%R9D,%EBX

0x40e516 AND	$0x7,%EBX

0x40e519 TEST	%R11D,%R11D

0x40e51c JG	40e62a

0x40e522 MOV	-0x34(%RBP),%R14D

0x40e526 MOV	-0x40(%RBP),%RCX

0x40e52a LEA	0x1(%R14),%R13D

0x40e52e LEA	0x8(%RCX),%R14

0x40e532 CMP	%R9D,%R13D

0x40e535 JGE	40e5e0

0x40e53b TEST	%EBX,%EBX

0x40e53d JE	40e5ce

0x40e543 CMP	$0x1,%EBX

0x40e546 JE	40e5bd

0x40e548 CMP	$0x2,%EBX

0x40e54b JE	40e5b1

0x40e54d CMP	$0x3,%EBX

0x40e550 JE	40e5a1

0x40e552 CMP	$0x4,%EBX

0x40e555 JE	40e591

0x40e557 CMP	$0x5,%EBX

0x40e55a JE	40e581

0x40e55c CMP	$0x6,%EBX

0x40e55f JE	40e571

0x40e561 TEST	%R11D,%R11D

0x40e564 JG	40e62a

0x40e56a INC	%R13D

0x40e56d ADD	$0x8,%R14

0x40e571 TEST	%R11D,%R11D

0x40e574 JG	40e62a

0x40e57a INC	%R13D

0x40e57d ADD	$0x8,%R14

0x40e581 TEST	%R11D,%R11D

0x40e584 JG	40e62a

0x40e58a INC	%R13D

0x40e58d ADD	$0x8,%R14

0x40e591 TEST	%R11D,%R11D

0x40e594 JG	40e62a

0x40e59a INC	%R13D

0x40e59d ADD	$0x8,%R14

0x40e5a1 TEST	%R11D,%R11D

0x40e5a4 JG	40e62a

0x40e5aa INC	%R13D

0x40e5ad ADD	$0x8,%R14

0x40e5b1 TEST	%R11D,%R11D

0x40e5b4 JG	40e62a

0x40e5b6 INC	%R13D

0x40e5b9 ADD	$0x8,%R14

0x40e5bd TEST	%R11D,%R11D

0x40e5c0 JG	40e62a

0x40e5c2 INC	%R13D

0x40e5c5 ADD	$0x8,%R14

0x40e5c9 CMP	%R9D,%R13D

0x40e5cc JGE	40e5e0

  (95) 0x40e5ce TEST	%R11D,%R11D

  (95) 0x40e5d1 JG	40e62a

  (95) 0x40e5d3 ADD	$0x8,%R13D

  (95) 0x40e5d7 ADD	$0x40,%R14

  (95) 0x40e5db CMP	%R9D,%R13D

  (95) 0x40e5de JL	40e5ce

0x40e5e0 ADD	$0x4,%R10

0x40e5e4 VMOVQ	%XMM19,%R14

0x40e5ea CMP	%R14,%R10

0x40e5ed JNE	40e4d2

0x40e62a MOV	-0x48(%RBP),%R12

0x40e62e MOV	%R10,%R11

0x40e631 MOV	%EDX,%EBX

0x40e633 MOV	%R8,%R10

0x40e636 MOV	%ESI,%R8D

0x40e639 MOV	%R13D,%ESI

0x40e63c VMOVSD	0x689c(%RIP),%XMM10

0x40e644 MOV	0x20(%R12),%R12

0x40e649 NOPL	(%RAX)

  (93) 0x40e650 MOV	0x18(%R12),%RDI

  (93) 0x40e655 LEA	(%R14,%R14,2),%R15

  (93) 0x40e659 VXORPD	%XMM4,%XMM4,%XMM4

  (93) 0x40e65d MOV	%R8D,%ECX

  (93) 0x40e660 NOT	%ECX

  (93) 0x40e662 ADD	%EBX,%ECX

  (93) 0x40e664 AND	$0x1,%ECX

  (93) 0x40e667 LEA	(%RDI,%R15,1),%R13

  (93) 0x40e66b ADD	%R10,%RDI

  (93) 0x40e66e VMOVSD	(%R13),%XMM3

  (93) 0x40e674 VSUBSD	(%RDI),%XMM3,%XMM6

  (93) 0x40e678 VMOVAPD	%XMM6,%XMM1

  (93) 0x40e67c VMOVSD	0x8(%R13),%XMM2

  (93) 0x40e682 VFMADD132SD	%XMM6,%XMM4,%XMM1

  (93) 0x40e687 VSUBSD	0x8(%RDI),%XMM2,%XMM3

  (93) 0x40e68c VMOVSD	0x10(%R13),%XMM16

  (93) 0x40e693 VSUBSD	0x10(%RDI),%XMM16,%XMM21

  (93) 0x40e69a VFMADD231SD	%XMM3,%XMM3,%XMM1

  (93) 0x40e69f VFMADD231SD	%XMM21,%XMM21,%XMM1

  (93) 0x40e6a5 VCOMISD	%XMM1,%XMM5

  (93) 0x40e6a9 JB	40e750

  (93) 0x40e6af VCOMISD	%XMM4,%XMM1

  (93) 0x40e6b3 JBE	40e750

  (93) 0x40e6b9 VDIVSD	%XMM1,%XMM9,%XMM1

  (93) 0x40e6bd VMULSD	%XMM1,%XMM1,%XMM17

  (93) 0x40e6c3 VMULSD	%XMM1,%XMM17,%XMM18

  (93) 0x40e6c9 VMULSD	%XMM12,%XMM18,%XMM22

  (93) 0x40e6cf VSUBSD	%XMM9,%XMM22,%XMM25

  (93) 0x40e6d5 VFMSUB132SD	%XMM22,%XMM11,%XMM25

  (93) 0x40e6db MOV	0x30(%R12),%RAX

  (93) 0x40e6e0 MOV	0x28(%R12),%RDX

  (93) 0x40e6e5 VMOVAPD	%XMM22,%XMM2

  (93) 0x40e6eb VMULSD	%XMM15,%XMM13,%XMM26

  (93) 0x40e6f1 VMULSD	%XMM22,%XMM26,%XMM27

  (93) 0x40e6f7 VMULSD	%XMM1,%XMM27,%XMM28

  (93) 0x40e6fd VFMADD132SD	%XMM14,%XMM10,%XMM2

  (93) 0x40e702 VFMADD231SD	%XMM8,%XMM25,%XMM7

  (93) 0x40e708 VMOVAPD	%XMM25,%XMM0

  (93) 0x40e70e ADD	%R15,%RDX

  (93) 0x40e711 ADD	%R14,%RAX

  (93) 0x40e714 VFMADD213SD	(%RAX),%XMM8,%XMM0

  (93) 0x40e719 VMULSD	%XMM28,%XMM2,%XMM1

  (93) 0x40e71f VMOVSD	%XMM0,(%RAX)

  (93) 0x40e723 VFNMADD213SD	(%RDX),%XMM1,%XMM6

  (93) 0x40e728 VFNMADD213SD	0x8(%RDX),%XMM1,%XMM3

  (93) 0x40e72e VMOVSD	%XMM6,(%RDX)

  (93) 0x40e732 VFNMADD213SD	0x10(%RDX),%XMM21,%XMM1

  (93) 0x40e739 VMOVSD	%XMM3,0x8(%RDX)

  (93) 0x40e73e VMOVSD	%XMM1,0x10(%RDX)

  (93) 0x40e743 NOPW	%CS:(%RAX,%RAX,1)

  (93) 0x40e74e XCHG	%AX,%AX

  (93) 0x40e750 LEA	0x1(%R8),%EDX

  (93) 0x40e754 LEA	0x18(%RDI),%RAX

  (93) 0x40e758 CMP	%EBX,%EDX

  (93) 0x40e75a JGE	40ea1e

  (93) 0x40e760 TEST	%ECX,%ECX

  (93) 0x40e762 JE	40e850

  (93) 0x40e768 VMOVSD	(%R13),%XMM6

  (93) 0x40e76e VSUBSD	0x18(%RDI),%XMM6,%XMM3

  (93) 0x40e773 VMOVAPD	%XMM3,%XMM0

  (93) 0x40e777 VMOVSD	0x8(%R13),%XMM2

  (93) 0x40e77d VFMADD132SD	%XMM3,%XMM4,%XMM0

  (93) 0x40e782 VSUBSD	0x8(%RAX),%XMM2,%XMM6

  (93) 0x40e787 VMOVSD	0x10(%R13),%XMM29

  (93) 0x40e78e VSUBSD	0x10(%RAX),%XMM29,%XMM30

  (93) 0x40e795 VFMADD231SD	%XMM6,%XMM6,%XMM0

  (93) 0x40e79a VFMADD231SD	%XMM30,%XMM30,%XMM0

  (93) 0x40e7a0 VCOMISD	%XMM0,%XMM5

  (93) 0x40e7a4 JB	40e840

  (93) 0x40e7aa VCOMISD	%XMM4,%XMM0

  (93) 0x40e7ae JBE	40e840

  (93) 0x40e7b4 VDIVSD	%XMM0,%XMM9,%XMM1

  (93) 0x40e7b8 VMULSD	%XMM1,%XMM1,%XMM31

  (93) 0x40e7be VMULSD	%XMM1,%XMM31,%XMM16

  (93) 0x40e7c4 VMULSD	%XMM12,%XMM16,%XMM21

  (93) 0x40e7ca VSUBSD	%XMM9,%XMM21,%XMM17

  (93) 0x40e7d0 VFMSUB132SD	%XMM21,%XMM11,%XMM17

  (93) 0x40e7d6 MOV	0x30(%R12),%RDI

  (93) 0x40e7db MOV	0x28(%R12),%RCX

  (93) 0x40e7e0 VMOVAPD	%XMM21,%XMM2

  (93) 0x40e7e6 VMULSD	%XMM15,%XMM13,%XMM18

  (93) 0x40e7ec VMULSD	%XMM21,%XMM18,%XMM22

  (93) 0x40e7f2 VMULSD	%XMM1,%XMM22,%XMM25

  (93) 0x40e7f8 VFMADD132SD	%XMM14,%XMM10,%XMM2

  (93) 0x40e7fd VFMADD231SD	%XMM8,%XMM17,%XMM7

  (93) 0x40e803 VMOVAPD	%XMM17,%XMM0

  (93) 0x40e809 ADD	%R15,%RCX

  (93) 0x40e80c ADD	%R14,%RDI

  (93) 0x40e80f VFMADD213SD	(%RDI),%XMM8,%XMM0

  (93) 0x40e814 VMULSD	%XMM25,%XMM2,%XMM1

  (93) 0x40e81a VMOVSD	%XMM0,(%RDI)

  (93) 0x40e81e VFNMADD213SD	(%RCX),%XMM1,%XMM3

  (93) 0x40e823 VFNMADD213SD	0x8(%RCX),%XMM1,%XMM6

  (93) 0x40e829 VMOVSD	%XMM3,(%RCX)

  (93) 0x40e82d VFNMADD213SD	0x10(%RCX),%XMM30,%XMM1

  (93) 0x40e834 VMOVSD	%XMM6,0x8(%RCX)

  (93) 0x40e839 VMOVSD	%XMM1,0x10(%RCX)

  (93) 0x40e83e XCHG	%AX,%AX

  (93) 0x40e840 INC	%EDX

  (93) 0x40e842 ADD	$0x18,%RAX

  (93) 0x40e846 CMP	%EBX,%EDX

  (93) 0x40e848 JGE	40ea1e

  (93) 0x40e84e XCHG	%AX,%AX

    (94) 0x40e850 VMOVSD	(%R13),%XMM3

    (94) 0x40e856 VSUBSD	(%RAX),%XMM3,%XMM6

    (94) 0x40e85a VMOVAPD	%XMM6,%XMM0

    (94) 0x40e85e VMOVSD	0x8(%R13),%XMM2

    (94) 0x40e864 VFMADD132SD	%XMM6,%XMM4,%XMM0

    (94) 0x40e869 VSUBSD	0x8(%RAX),%XMM2,%XMM1

    (94) 0x40e86e VMOVSD	0x10(%R13),%XMM3

    (94) 0x40e874 VSUBSD	0x10(%RAX),%XMM3,%XMM2

    (94) 0x40e879 VFMADD231SD	%XMM1,%XMM1,%XMM0

    (94) 0x40e87e VFMADD231SD	%XMM2,%XMM2,%XMM0

    (94) 0x40e883 VCOMISD	%XMM0,%XMM5

    (94) 0x40e887 JB	40e930

    (94) 0x40e88d VCOMISD	%XMM4,%XMM0

    (94) 0x40e891 JBE	40e930

    (94) 0x40e897 VDIVSD	%XMM0,%XMM9,%XMM0

    (94) 0x40e89b VMULSD	%XMM0,%XMM0,%XMM26

    (94) 0x40e8a1 VMULSD	%XMM0,%XMM26,%XMM27

    (94) 0x40e8a7 VMULSD	%XMM12,%XMM27,%XMM28

    (94) 0x40e8ad VSUBSD	%XMM9,%XMM28,%XMM29

    (94) 0x40e8b3 VFMSUB132SD	%XMM28,%XMM11,%XMM29

    (94) 0x40e8b9 MOV	0x30(%R12),%RDI

    (94) 0x40e8be MOV	0x28(%R12),%RCX

    (94) 0x40e8c3 VMULSD	%XMM15,%XMM13,%XMM31

    (94) 0x40e8c9 VMULSD	%XMM28,%XMM31,%XMM16

    (94) 0x40e8cf VFMADD132SD	%XMM14,%XMM10,%XMM28

    (94) 0x40e8d5 VMULSD	%XMM0,%XMM16,%XMM21

    (94) 0x40e8db VFMADD231SD	%XMM8,%XMM29,%XMM7

    (94) 0x40e8e1 VMOVAPD	%XMM29,%XMM30

    (94) 0x40e8e7 ADD	%R15,%RCX

    (94) 0x40e8ea ADD	%R14,%RDI

    (94) 0x40e8ed VMULSD	%XMM21,%XMM28,%XMM17

    (94) 0x40e8f3 VFMADD213SD	(%RDI),%XMM8,%XMM30

    (94) 0x40e8f9 VMOVSD	%XMM30,(%RDI)

    (94) 0x40e8ff VFNMADD213SD	(%RCX),%XMM17,%XMM6

    (94) 0x40e905 VFNMADD213SD	0x8(%RCX),%XMM17,%XMM1

    (94) 0x40e90c VFNMADD213SD	0x10(%RCX),%XMM17,%XMM2

    (94) 0x40e913 VMOVSD	%XMM6,(%RCX)

    (94) 0x40e917 VMOVSD	%XMM1,0x8(%RCX)

    (94) 0x40e91c VMOVSD	%XMM2,0x10(%RCX)

    (94) 0x40e921 NOPW	%CS:(%RAX,%RAX,1)

    (94) 0x40e92c NOPL	(%RAX)

    (94) 0x40e930 VMOVSD	(%R13),%XMM6

    (94) 0x40e936 VSUBSD	0x18(%RAX),%XMM6,%XMM2

    (94) 0x40e93b VMOVAPD	%XMM2,%XMM0

    (94) 0x40e93f VMOVSD	0x8(%R13),%XMM1

    (94) 0x40e945 VFMADD132SD	%XMM2,%XMM4,%XMM0

    (94) 0x40e94a VSUBSD	0x20(%RAX),%XMM1,%XMM6

    (94) 0x40e94f VMOVSD	0x10(%R13),%XMM3

    (94) 0x40e955 VSUBSD	0x28(%RAX),%XMM3,%XMM1

    (94) 0x40e95a INC	%EDX

    (94) 0x40e95c LEA	0x18(%RAX),%RDI

    (94) 0x40e960 VFMADD231SD	%XMM6,%XMM6,%XMM0

    (94) 0x40e965 VFMADD231SD	%XMM1,%XMM1,%XMM0

    (94) 0x40e96a VCOMISD	%XMM0,%XMM5

    (94) 0x40e96e JB	40ea10

    (94) 0x40e974 VCOMISD	%XMM4,%XMM0

    (94) 0x40e978 JBE	40ea10

    (94) 0x40e97e VDIVSD	%XMM0,%XMM9,%XMM0

    (94) 0x40e982 VMULSD	%XMM0,%XMM0,%XMM18

    (94) 0x40e988 VMULSD	%XMM0,%XMM18,%XMM22

    (94) 0x40e98e VMULSD	%XMM12,%XMM22,%XMM25

    (94) 0x40e994 VSUBSD	%XMM9,%XMM25,%XMM26

    (94) 0x40e99a VFMSUB132SD	%XMM25,%XMM11,%XMM26

    (94) 0x40e9a0 MOV	0x30(%R12),%RAX

    (94) 0x40e9a5 MOV	0x28(%R12),%RCX

    (94) 0x40e9aa VMULSD	%XMM15,%XMM13,%XMM28

    (94) 0x40e9b0 VMULSD	%XMM25,%XMM28,%XMM29

    (94) 0x40e9b6 VFMADD132SD	%XMM14,%XMM10,%XMM25

    (94) 0x40e9bc VMULSD	%XMM0,%XMM29,%XMM30

    (94) 0x40e9c2 VFMADD231SD	%XMM8,%XMM26,%XMM7

    (94) 0x40e9c8 VMOVAPD	%XMM26,%XMM27

    (94) 0x40e9ce ADD	%R15,%RCX

    (94) 0x40e9d1 ADD	%R14,%RAX

    (94) 0x40e9d4 VMULSD	%XMM30,%XMM25,%XMM31

    (94) 0x40e9da VFMADD213SD	(%RAX),%XMM8,%XMM27

    (94) 0x40e9e0 VMOVSD	%XMM27,(%RAX)

    (94) 0x40e9e6 VFNMADD213SD	(%RCX),%XMM31,%XMM2

    (94) 0x40e9ec VFNMADD213SD	0x8(%RCX),%XMM31,%XMM6

    (94) 0x40e9f3 VFNMADD213SD	0x10(%RCX),%XMM31,%XMM1

    (94) 0x40e9fa VMOVSD	%XMM2,(%RCX)

    (94) 0x40e9fe VMOVSD	%XMM6,0x8(%RCX)

    (94) 0x40ea03 VMOVSD	%XMM1,0x10(%RCX)

    (94) 0x40ea08 NOPL	(%RAX,%RAX,1)

    (94) 0x40ea10 INC	%EDX

    (94) 0x40ea12 LEA	0x18(%RDI),%RAX

    (94) 0x40ea16 CMP	%EBX,%EDX

    (94) 0x40ea18 JL	40e850

  (93) 0x40ea1e INC	%ESI

  (93) 0x40ea20 ADD	$0x8,%R14

  (93) 0x40ea24 CMP	%ESI,%R9D

  (93) 0x40ea27 JG	40e650

0x40ea2d MOV	%R11,%R10

0x40ea30 VMOVQ	%XMM19,%R14

0x40ea36 ADD	$0x4,%R10

0x40ea3a CMP	%R14,%R10

0x40ea3d JNE	40e4d2

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 178 - 216

--------------------------------------------------------------------------------

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module
○99.56	gomp_thread_start	team.c:130	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	15.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P0, P1, P2, P3, P4, P5,
Function	ljForce._omp_fn.1
Source	ljForce.c:178-184,ljForce.c:187-187,ljForce.c:191-191,ljForce.c:213-213
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.17
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	11.17
CQA cycles if fully vectorized	0.72
Front-end cycles	10.88
P0 cycles	11.17
P1 cycles	11.17
P2 cycles	11.17
P3 cycles	11.17
P4 cycles	11.17
P5 cycles	11.17
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	89.00
Nb uops	87.00
Nb loads	9.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.01
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.19
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	7.29

Metric	Value
CQA speedup if no scalar integer	1.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	15.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P0, P1, P2, P3, P4, P5,
Function	ljForce._omp_fn.1
Source	ljForce.c:178-184,ljForce.c:187-187,ljForce.c:191-191,ljForce.c:213-213
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.17
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	11.17
CQA cycles if fully vectorized	0.72
Front-end cycles	10.88
P0 cycles	11.17
P1 cycles	11.17
P2 cycles	11.17
P3 cycles	11.17
P4 cycles	11.17
P5 cycles	11.17
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	89.00
Nb uops	87.00
Nb loads	9.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.01
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.19
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	7.29

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:178-216
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-191,197-216.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-184,187,191,213.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 4457 paths individually, rerun with max-paths=4457
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 4457 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.17 to 7.00 cycles (1.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.17 to 0.72 cycles (15.54x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes.

General properties

nb instructions	89
nb uops	87
loop length	331
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.88 cycles
front end	10.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	11.17	11.17	11.17	11.17	11.17	11.17	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	2.00	2.00
cycles	11.17	11.17	11.17	11.17	11.17	11.17	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.88
Dispatch	11.17
Overall L1	11.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	7%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.17 cycles. At this rate:

1% of peak load performance is reached (5.01 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40e4d2

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
MOV (%R10),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
TEST %ESI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JS 40eb70 <ljForce._omp_fn.1+0x7c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
MOVSXD %ESI,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM24,%RAX	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVD %XMM23,%EDI	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	scal (6.3%)
MOV (%RAX,%R15,4),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
TEST %EDI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40e5e0 <ljForce._omp_fn.1+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
MOV -0x34(%RBP),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
LEA (%R15,%R15,2),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
SAL $0x9,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %EBX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOT %EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA (%R11,%RSI,1),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %R9D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e62a <ljForce._omp_fn.1+0x27a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
MOV -0x34(%RBP),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA 0x1(%R14),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA 0x8(%RCX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R9D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40e5e0 <ljForce._omp_fn.1+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
TEST %EBX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40e5ce <ljForce._omp_fn.1+0x21e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40e5bd <ljForce._omp_fn.1+0x20d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40e5b1 <ljForce._omp_fn.1+0x201>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x3,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40e5a1 <ljForce._omp_fn.1+0x1f1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x4,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40e591 <ljForce._omp_fn.1+0x1e1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x5,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40e581 <ljForce._omp_fn.1+0x1d1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x6,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40e571 <ljForce._omp_fn.1+0x1c1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e62a <ljForce._omp_fn.1+0x27a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e62a <ljForce._omp_fn.1+0x27a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e62a <ljForce._omp_fn.1+0x27a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e62a <ljForce._omp_fn.1+0x27a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e62a <ljForce._omp_fn.1+0x27a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e62a <ljForce._omp_fn.1+0x27a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e62a <ljForce._omp_fn.1+0x27a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R9D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40e5e0 <ljForce._omp_fn.1+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
ADD $0x4,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM19,%R14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R14,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 40e4d2 <ljForce._omp_fn.1+0x122>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
MOV -0x48(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R10,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ESI,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x689c(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV 0x20(%R12),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %R11,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM19,%R14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD $0x4,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R14,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JNE 40e4d2 <ljForce._omp_fn.1+0x122>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:178-216
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 4457 paths individually, rerun with max-paths=4457
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.17 to 7.00 cycles (1.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes.

General properties

nb instructions	89
nb uops	87
loop length	331
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.88 cycles
front end	10.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	11.17	11.17	11.17	11.17	11.17	11.17	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	2.00	2.00
cycles	11.17	11.17	11.17	11.17	11.17	11.17	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.88
Dispatch	11.17
Overall L1	11.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	7%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.17 cycles. At this rate:

1% of peak load performance is reached (5.01 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40e4d2

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
MOV (%R10),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
TEST %ESI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JS 40eb70 <ljForce._omp_fn.1+0x7c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
MOVSXD %ESI,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM24,%RAX	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVD %XMM23,%EDI	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	scal (6.3%)
MOV (%RAX,%R15,4),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
TEST %EDI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40e5e0 <ljForce._omp_fn.1+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
MOV -0x34(%RBP),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
LEA (%R15,%R15,2),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
SAL $0x9,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %EBX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOT %EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA (%R11,%RSI,1),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %R9D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e62a <ljForce._omp_fn.1+0x27a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
MOV -0x34(%RBP),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA 0x1(%R14),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA 0x8(%RCX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R9D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40e5e0 <ljForce._omp_fn.1+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
TEST %EBX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40e5ce <ljForce._omp_fn.1+0x21e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40e5bd <ljForce._omp_fn.1+0x20d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40e5b1 <ljForce._omp_fn.1+0x201>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x3,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40e5a1 <ljForce._omp_fn.1+0x1f1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x4,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40e591 <ljForce._omp_fn.1+0x1e1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x5,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40e581 <ljForce._omp_fn.1+0x1d1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x6,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40e571 <ljForce._omp_fn.1+0x1c1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e62a <ljForce._omp_fn.1+0x27a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e62a <ljForce._omp_fn.1+0x27a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e62a <ljForce._omp_fn.1+0x27a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e62a <ljForce._omp_fn.1+0x27a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e62a <ljForce._omp_fn.1+0x27a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e62a <ljForce._omp_fn.1+0x27a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e62a <ljForce._omp_fn.1+0x27a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R9D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40e5e0 <ljForce._omp_fn.1+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
ADD $0x4,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM19,%R14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R14,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 40e4d2 <ljForce._omp_fn.1+0x122>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
MOV -0x48(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R10,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ESI,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x689c(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV 0x20(%R12),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %R11,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM19,%R14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD $0x4,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R14,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JNE 40e4d2 <ljForce._omp_fn.1+0x122>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code