OV - exec - Loop 105

	Loop Id: 105	Module: exec	Source: timestep.c:71-78	Coverage: 1.04%

0x4116a0 VMOVQ	%XMM7,%RSI

0x4116a5 MOVSXD	(%RSI,%RDI,4),%RCX

0x4116a9 TEST	%ECX,%ECX

0x4116ab JLE	411a91

0x4116b1 MOV	0x20(%R11),%R8

0x4116b5 LEA	-0x1(%RCX),%R15D

0x4116b9 MOV	%ECX,%R14D

0x4116bc MOV	0x20(%R8),%R10

0x4116c0 MOV	0x28(%R8),%R13

0x4116c4 LEA	(%R10,%R9,1),%RBX

0x4116c8 LEA	(%R13,%R9,1),%R12

0x4116cd CMP	$0x2,%R15D

0x4116d1 JBE	411ac0

0x4116d7 LEA	(%R13,%R9,1),%R12

0x4116dc LEA	0xc0(%R10,%R9,1),%RDX

0x4116e4 LEA	0xc0(%R9),%RAX

0x4116eb LEA	(%R10,%R9,1),%RBX

0x4116ef CMP	%RDX,%R12

0x4116f2 JAE	411700

0x4116f4 ADD	%R13,%RAX

0x4116f7 CMP	%RAX,%RBX

0x4116fa JB	411ac0

0x411700 MOV	%EDI,%R8D

0x411703 SAL	$0x6,%R8D

0x411707 CMP	$0x6,%R15D

0x41170b JBE	411e8b

0x411711 MOV	%ECX,%ESI

0x411713 MOV	$0x2aaaaaaaaaaaaab,%R15

0x41171d MOV	%RBX,%RAX

0x411720 MOV	%R12,%RDX

0x411723 SHR	$0x3,%ESI

0x411726 LEA	(%RSI,%RSI,2),%RSI

0x41172a SAL	$0x6,%RSI

0x41172e LEA	(%RBX,%RSI,1),%R14

0x411732 SUB	$0xc0,%RSI

0x411739 SHR	$0x6,%RSI

0x41173d IMUL	%R15,%RSI

0x411741 INC	%RSI

0x411744 AND	$0x3,%ESI

0x411747 JE	411844

0x41174d CMP	$0x1,%RSI

0x411751 JE	4117f2

0x411757 CMP	$0x2,%RSI

0x41175b JE	4117a9

0x41175d VMOVUPD	(%R12),%ZMM6

0x411764 VMOVUPD	0x40(%R12),%ZMM5

0x41176c VMOVUPD	0x80(%R12),%ZMM4

0x411774 VFMADD213PD	(%RBX),%ZMM0,%ZMM6

0x41177a VFMADD213PD	0x40(%RBX),%ZMM0,%ZMM5

0x411781 VFMADD213PD	0x80(%RBX),%ZMM0,%ZMM4

0x411788 VMOVUPD	%ZMM6,(%RBX)

0x41178e ADD	$0xc0,%RAX

0x411794 VMOVUPD	%ZMM5,0x40(%RBX)

0x41179b ADD	$0xc0,%RDX

0x4117a2 VMOVUPD	%ZMM4,0x80(%RBX)

0x4117a9 VMOVUPD	(%RDX),%ZMM2

0x4117af VMOVUPD	0x40(%RDX),%ZMM8

0x4117b6 VMOVUPD	0x80(%RDX),%ZMM9

0x4117bd VFMADD213PD	(%RAX),%ZMM0,%ZMM2

0x4117c3 VFMADD213PD	0x40(%RAX),%ZMM0,%ZMM8

0x4117ca VFMADD213PD	0x80(%RAX),%ZMM0,%ZMM9

0x4117d1 VMOVUPD	%ZMM2,(%RAX)

0x4117d7 ADD	$0xc0,%RDX

0x4117de VMOVUPD	%ZMM8,0x40(%RAX)

0x4117e5 ADD	$0xc0,%RAX

0x4117eb VMOVUPD	%ZMM9,-0x40(%RAX)

0x4117f2 VMOVUPD	(%RDX),%ZMM10

0x4117f8 VMOVUPD	0x40(%RDX),%ZMM11

0x4117ff VMOVUPD	0x80(%RDX),%ZMM12

0x411806 VFMADD213PD	(%RAX),%ZMM0,%ZMM10

0x41180c VFMADD213PD	0x40(%RAX),%ZMM0,%ZMM11

0x411813 VFMADD213PD	0x80(%RAX),%ZMM0,%ZMM12

0x41181a VMOVUPD	%ZMM10,(%RAX)

0x411820 ADD	$0xc0,%RAX

0x411826 VMOVUPD	%ZMM11,-0x80(%RAX)

0x41182d ADD	$0xc0,%RDX

0x411834 VMOVUPD	%ZMM12,-0x40(%RAX)

0x41183b CMP	%R14,%RAX

0x41183e JE	411953

  (107) 0x411844 VMOVUPD	(%RDX),%ZMM13

  (107) 0x41184a VMOVUPD	0x40(%RDX),%ZMM14

  (107) 0x411851 VMOVUPD	0x80(%RDX),%ZMM15

  (107) 0x411858 VFMADD213PD	(%RAX),%ZMM0,%ZMM13

  (107) 0x41185e VFMADD213PD	0x40(%RAX),%ZMM0,%ZMM14

  (107) 0x411865 VMOVUPD	%ZMM13,(%RAX)

  (107) 0x41186b VFMADD213PD	0x80(%RAX),%ZMM0,%ZMM15

  (107) 0x411872 ADD	$0x300,%RAX

  (107) 0x411878 VMOVUPD	%ZMM14,-0x2c0(%RAX)

  (107) 0x41187f ADD	$0x300,%RDX

  (107) 0x411886 VMOVUPD	%ZMM15,-0x280(%RAX)

  (107) 0x41188d VMOVUPD	-0x240(%RDX),%ZMM5

  (107) 0x411894 VMOVUPD	-0x200(%RDX),%ZMM6

  (107) 0x41189b VMOVUPD	-0x1c0(%RDX),%ZMM4

  (107) 0x4118a2 VFMADD213PD	-0x240(%RAX),%ZMM0,%ZMM5

  (107) 0x4118a9 VFMADD213PD	-0x200(%RAX),%ZMM0,%ZMM6

  (107) 0x4118b0 VMOVUPD	%ZMM5,-0x240(%RAX)

  (107) 0x4118b7 VFMADD213PD	-0x1c0(%RAX),%ZMM0,%ZMM4

  (107) 0x4118be VMOVUPD	%ZMM6,-0x200(%RAX)

  (107) 0x4118c5 VMOVUPD	%ZMM4,-0x1c0(%RAX)

  (107) 0x4118cc VMOVUPD	-0x180(%RDX),%ZMM8

  (107) 0x4118d3 VMOVUPD	-0x140(%RDX),%ZMM9

  (107) 0x4118da VMOVUPD	-0x100(%RDX),%ZMM2

  (107) 0x4118e1 VFMADD213PD	-0x180(%RAX),%ZMM0,%ZMM8

  (107) 0x4118e8 VFMADD213PD	-0x140(%RAX),%ZMM0,%ZMM9

  (107) 0x4118ef VMOVUPD	%ZMM8,-0x180(%RAX)

  (107) 0x4118f6 VFMADD213PD	-0x100(%RAX),%ZMM0,%ZMM2

  (107) 0x4118fd VMOVUPD	%ZMM9,-0x140(%RAX)

  (107) 0x411904 VMOVUPD	%ZMM2,-0x100(%RAX)

  (107) 0x41190b VMOVUPD	-0xc0(%RDX),%ZMM10

  (107) 0x411912 VMOVUPD	-0x80(%RDX),%ZMM11

  (107) 0x411919 VFMADD213PD	-0xc0(%RAX),%ZMM0,%ZMM10

  (107) 0x411920 VFMADD213PD	-0x80(%RAX),%ZMM0,%ZMM11

  (107) 0x411927 VMOVUPD	-0x40(%RDX),%ZMM12

  (107) 0x41192e VFMADD213PD	-0x40(%RAX),%ZMM0,%ZMM12

  (107) 0x411935 VMOVUPD	%ZMM10,-0xc0(%RAX)

  (107) 0x41193c VMOVUPD	%ZMM11,-0x80(%RAX)

  (107) 0x411943 VMOVUPD	%ZMM12,-0x40(%RAX)

  (107) 0x41194a CMP	%R14,%RAX

  (107) 0x41194d JNE	411844

0x411953 MOV	%ECX,%EAX

0x411955 AND	$-0x8,%EAX

0x411958 MOV	%EAX,%R15D

0x41195b ADD	%EAX,%R8D

0x41195e CMP	%EAX,%ECX

0x411960 JE	411a91

0x411966 MOV	%ECX,%R14D

0x411969 SUB	%EAX,%R14D

0x41196c LEA	-0x1(%R14),%EBX

0x411970 CMP	$0x2,%EBX

0x411973 JBE	4119c8

0x411975 LEA	(%R15,%R15,2),%R12

0x411979 MOV	%R14D,%R15D

0x41197c AND	$-0x4,%R15D

0x411980 LEA	(%R9,%R12,8),%RSI

0x411984 LEA	(%R10,%RSI,1),%RDX

0x411988 ADD	%R15D,%EAX

0x41198b ADD	%R13,%RSI

0x41198e ADD	%R15D,%R8D

0x411991 AND	$0x3,%R14D

0x411995 VMOVUPD	(%RSI),%YMM13

0x411999 VMOVUPD	0x20(%RSI),%YMM14

0x41199e VMOVUPD	0x40(%RSI),%YMM15

0x4119a3 VFMADD213PD	(%RDX),%YMM3,%YMM13

0x4119a8 VFMADD213PD	0x20(%RDX),%YMM3,%YMM14

0x4119ae VFMADD213PD	0x40(%RDX),%YMM3,%YMM15

0x4119b4 VMOVUPD	%YMM13,(%RDX)

0x4119b8 VMOVUPD	%YMM14,0x20(%RDX)

0x4119bd VMOVUPD	%YMM15,0x40(%RDX)

0x4119c2 JE	411a91

0x4119c8 MOVSXD	%R8D,%R8

0x4119cb LEA	0x1(%RAX),%ESI

0x4119ce LEA	(%R8,%R8,2),%R14

0x4119d2 SAL	$0x3,%R14

0x4119d6 LEA	(%R10,%R14,1),%RBX

0x4119da LEA	(%R13,%R14,1),%R12

0x4119df VMOVSD	(%R12),%XMM5

0x4119e5 VFMADD213SD	(%RBX),%XMM1,%XMM5

0x4119ea VMOVSD	%XMM5,(%RBX)

0x4119ee VMOVSD	0x8(%R12),%XMM6

0x4119f5 VFMADD213SD	0x8(%RBX),%XMM1,%XMM6

0x4119fb VMOVSD	%XMM6,0x8(%RBX)

0x411a00 VMOVSD	0x10(%R12),%XMM4

0x411a07 VFMADD213SD	0x10(%RBX),%XMM1,%XMM4

0x411a0d VMOVSD	%XMM4,0x10(%RBX)

0x411a12 CMP	%ESI,%ECX

0x411a14 JLE	411a91

0x411a16 LEA	0x18(%R10,%R14,1),%RDX

0x411a1b LEA	0x18(%R13,%R14,1),%R15

0x411a20 ADD	$0x2,%EAX

0x411a23 VMOVSD	(%R15),%XMM8

0x411a28 VFMADD213SD	(%RDX),%XMM1,%XMM8

0x411a2d VMOVSD	%XMM8,(%RDX)

0x411a31 VMOVSD	0x8(%R15),%XMM9

0x411a37 VFMADD213SD	0x8(%RDX),%XMM1,%XMM9

0x411a3d VMOVSD	%XMM9,0x8(%RDX)

0x411a42 VMOVSD	0x10(%R15),%XMM2

0x411a48 VFMADD213SD	0x10(%RDX),%XMM1,%XMM2

0x411a4e VMOVSD	%XMM2,0x10(%RDX)

0x411a53 CMP	%EAX,%ECX

0x411a55 JLE	411a91

0x411a57 LEA	0x30(%R10,%R14,1),%RCX

0x411a5c LEA	0x30(%R13,%R14,1),%R10

0x411a61 VMOVSD	(%R10),%XMM10

0x411a66 VFMADD213SD	(%RCX),%XMM1,%XMM10

0x411a6b VMOVSD	%XMM10,(%RCX)

0x411a6f VMOVSD	0x8(%R10),%XMM11

0x411a75 VFMADD213SD	0x8(%RCX),%XMM1,%XMM11

0x411a7b VMOVSD	%XMM11,0x8(%RCX)

0x411a80 VMOVSD	0x10(%R10),%XMM12

0x411a86 VFMADD213SD	0x10(%RCX),%XMM1,%XMM12

0x411a8c VMOVSD	%XMM12,0x10(%RCX)

0x411a91 INC	%RDI

0x411a94 ADD	$0x600,%R9

0x411a9b CMP	%EDI,0x3c(%RSP)

0x411a9f JG	4116a0

0x411ac0 LEA	(%RCX,%RCX,2),%R8

0x411ac4 MOV	$0xaaaaaaaaaaaaaab,%RDX

0x411ace MOV	%RBX,%R13

0x411ad1 MOV	%R12,%RAX

0x411ad4 LEA	-0x18(,%R8,8),%RSI

0x411adc LEA	(%RBX,%R8,8),%R14

0x411ae0 SHR	$0x3,%RSI

0x411ae4 IMUL	%RDX,%RSI

0x411ae8 INC	%RSI

0x411aeb AND	$0x7,%ESI

0x411aee JE	411c91

0x411af4 CMP	$0x1,%RSI

0x411af8 JE	411c4e

0x411afe CMP	$0x2,%RSI

0x411b02 JE	411c14

0x411b08 CMP	$0x3,%RSI

0x411b0c JE	411bda

0x411b12 CMP	$0x4,%RSI

0x411b16 JE	411ba0

0x411b1c CMP	$0x5,%RSI

0x411b20 JE	411b66

0x411b22 CMP	$0x6,%RSI

0x411b26 JNE	411e9e

0x411b2c VMOVSD	(%RAX),%XMM5

0x411b30 ADD	$0x18,%R13

0x411b34 VFMADD213SD	-0x18(%R13),%XMM1,%XMM5

0x411b3a ADD	$0x18,%RAX

0x411b3e VMOVSD	%XMM5,-0x18(%R13)

0x411b44 VMOVSD	-0x10(%RAX),%XMM6

0x411b49 VFMADD213SD	-0x10(%R13),%XMM1,%XMM6

0x411b4f VMOVSD	%XMM6,-0x10(%R13)

0x411b55 VMOVSD	-0x8(%RAX),%XMM4

0x411b5a VFMADD213SD	-0x8(%R13),%XMM1,%XMM4

0x411b60 VMOVSD	%XMM4,-0x8(%R13)

0x411b66 VMOVSD	(%RAX),%XMM8

0x411b6a ADD	$0x18,%R13

0x411b6e VFMADD213SD	-0x18(%R13),%XMM1,%XMM8

0x411b74 ADD	$0x18,%RAX

0x411b78 VMOVSD	%XMM8,-0x18(%R13)

0x411b7e VMOVSD	-0x10(%RAX),%XMM9

0x411b83 VFMADD213SD	-0x10(%R13),%XMM1,%XMM9

0x411b89 VMOVSD	%XMM9,-0x10(%R13)

0x411b8f VMOVSD	-0x8(%RAX),%XMM2

0x411b94 VFMADD213SD	-0x8(%R13),%XMM1,%XMM2

0x411b9a VMOVSD	%XMM2,-0x8(%R13)

0x411ba0 VMOVSD	(%RAX),%XMM10

0x411ba4 ADD	$0x18,%R13

0x411ba8 VFMADD213SD	-0x18(%R13),%XMM1,%XMM10

0x411bae ADD	$0x18,%RAX

0x411bb2 VMOVSD	%XMM10,-0x18(%R13)

0x411bb8 VMOVSD	-0x10(%RAX),%XMM11

0x411bbd VFMADD213SD	-0x10(%R13),%XMM1,%XMM11

0x411bc3 VMOVSD	%XMM11,-0x10(%R13)

0x411bc9 VMOVSD	-0x8(%RAX),%XMM12

0x411bce VFMADD213SD	-0x8(%R13),%XMM1,%XMM12

0x411bd4 VMOVSD	%XMM12,-0x8(%R13)

0x411bda VMOVSD	(%RAX),%XMM13

0x411bde ADD	$0x18,%R13

0x411be2 VFMADD213SD	-0x18(%R13),%XMM1,%XMM13

0x411be8 ADD	$0x18,%RAX

0x411bec VMOVSD	%XMM13,-0x18(%R13)

0x411bf2 VMOVSD	-0x10(%RAX),%XMM14

0x411bf7 VFMADD213SD	-0x10(%R13),%XMM1,%XMM14

0x411bfd VMOVSD	%XMM14,-0x10(%R13)

0x411c03 VMOVSD	-0x8(%RAX),%XMM15

0x411c08 VFMADD213SD	-0x8(%R13),%XMM1,%XMM15

0x411c0e VMOVSD	%XMM15,-0x8(%R13)

0x411c14 VMOVSD	(%RAX),%XMM5

0x411c18 ADD	$0x18,%R13

0x411c1c VFMADD213SD	-0x18(%R13),%XMM1,%XMM5

0x411c22 ADD	$0x18,%RAX

0x411c26 VMOVSD	%XMM5,-0x18(%R13)

0x411c2c VMOVSD	-0x10(%RAX),%XMM6

0x411c31 VFMADD213SD	-0x10(%R13),%XMM1,%XMM6

0x411c37 VMOVSD	%XMM6,-0x10(%R13)

0x411c3d VMOVSD	-0x8(%RAX),%XMM4

0x411c42 VFMADD213SD	-0x8(%R13),%XMM1,%XMM4

0x411c48 VMOVSD	%XMM4,-0x8(%R13)

0x411c4e VMOVSD	(%RAX),%XMM8

0x411c52 ADD	$0x18,%R13

0x411c56 VFMADD213SD	-0x18(%R13),%XMM1,%XMM8

0x411c5c VMOVSD	%XMM8,-0x18(%R13)

0x411c62 VMOVSD	0x8(%RAX),%XMM9

0x411c67 VFMADD213SD	-0x10(%R13),%XMM1,%XMM9

0x411c6d VMOVSD	%XMM9,-0x10(%R13)

0x411c73 VMOVSD	0x10(%RAX),%XMM2

0x411c78 ADD	$0x18,%RAX

0x411c7c VFMADD213SD	-0x8(%R13),%XMM1,%XMM2

0x411c82 VMOVSD	%XMM2,-0x8(%R13)

0x411c88 CMP	%R13,%R14

0x411c8b JE	411a91

  (106) 0x411c91 VMOVSD	(%RAX),%XMM10

  (106) 0x411c95 ADD	$0xc0,%R13

  (106) 0x411c9c VFMADD213SD	-0xc0(%R13),%XMM1,%XMM10

  (106) 0x411ca5 VMOVSD	%XMM10,-0xc0(%R13)

  (106) 0x411cae VMOVSD	0x8(%RAX),%XMM11

  (106) 0x411cb3 VFMADD213SD	-0xb8(%R13),%XMM1,%XMM11

  (106) 0x411cbc VMOVSD	%XMM11,-0xb8(%R13)

  (106) 0x411cc5 VMOVSD	0x10(%RAX),%XMM12

  (106) 0x411cca VFMADD213SD	-0xb0(%R13),%XMM1,%XMM12

  (106) 0x411cd3 VMOVSD	%XMM12,-0xb0(%R13)

  (106) 0x411cdc VMOVSD	0x18(%RAX),%XMM13

  (106) 0x411ce1 VFMADD213SD	-0xa8(%R13),%XMM1,%XMM13

  (106) 0x411cea VMOVSD	%XMM13,-0xa8(%R13)

  (106) 0x411cf3 VMOVSD	0x20(%RAX),%XMM14

  (106) 0x411cf8 VFMADD213SD	-0xa0(%R13),%XMM1,%XMM14

  (106) 0x411d01 VMOVSD	%XMM14,-0xa0(%R13)

  (106) 0x411d0a VMOVSD	0x28(%RAX),%XMM15

  (106) 0x411d0f VFMADD213SD	-0x98(%R13),%XMM1,%XMM15

  (106) 0x411d18 VMOVSD	%XMM15,-0x98(%R13)

  (106) 0x411d21 VMOVSD	0x30(%RAX),%XMM5

  (106) 0x411d26 VFMADD213SD	-0x90(%R13),%XMM1,%XMM5

  (106) 0x411d2f VMOVSD	%XMM5,-0x90(%R13)

  (106) 0x411d38 VMOVSD	0x38(%RAX),%XMM6

  (106) 0x411d3d VFMADD213SD	-0x88(%R13),%XMM1,%XMM6

  (106) 0x411d46 VMOVSD	%XMM6,-0x88(%R13)

  (106) 0x411d4f VMOVSD	0x40(%RAX),%XMM4

  (106) 0x411d54 VFMADD213SD	-0x80(%R13),%XMM1,%XMM4

  (106) 0x411d5a VMOVSD	%XMM4,-0x80(%R13)

  (106) 0x411d60 VMOVSD	0x48(%RAX),%XMM8

  (106) 0x411d65 VFMADD213SD	-0x78(%R13),%XMM1,%XMM8

  (106) 0x411d6b VMOVSD	%XMM8,-0x78(%R13)

  (106) 0x411d71 VMOVSD	0x50(%RAX),%XMM9

  (106) 0x411d76 VFMADD213SD	-0x70(%R13),%XMM1,%XMM9

  (106) 0x411d7c VMOVSD	%XMM9,-0x70(%R13)

  (106) 0x411d82 VMOVSD	0x58(%RAX),%XMM2

  (106) 0x411d87 VFMADD213SD	-0x68(%R13),%XMM1,%XMM2

  (106) 0x411d8d VMOVSD	%XMM2,-0x68(%R13)

  (106) 0x411d93 VMOVSD	0x60(%RAX),%XMM10

  (106) 0x411d98 VFMADD213SD	-0x60(%R13),%XMM1,%XMM10

  (106) 0x411d9e VMOVSD	%XMM10,-0x60(%R13)

  (106) 0x411da4 VMOVSD	0x68(%RAX),%XMM11

  (106) 0x411da9 VFMADD213SD	-0x58(%R13),%XMM1,%XMM11

  (106) 0x411daf VMOVSD	%XMM11,-0x58(%R13)

  (106) 0x411db5 VMOVSD	0x70(%RAX),%XMM12

  (106) 0x411dba VFMADD213SD	-0x50(%R13),%XMM1,%XMM12

  (106) 0x411dc0 VMOVSD	%XMM12,-0x50(%R13)

  (106) 0x411dc6 VMOVSD	0x78(%RAX),%XMM13

  (106) 0x411dcb VFMADD213SD	-0x48(%R13),%XMM1,%XMM13

  (106) 0x411dd1 VMOVSD	%XMM13,-0x48(%R13)

  (106) 0x411dd7 VMOVSD	0x80(%RAX),%XMM14

  (106) 0x411ddf VFMADD213SD	-0x40(%R13),%XMM1,%XMM14

  (106) 0x411de5 VMOVSD	%XMM14,-0x40(%R13)

  (106) 0x411deb VMOVSD	0x88(%RAX),%XMM15

  (106) 0x411df3 VFMADD213SD	-0x38(%R13),%XMM1,%XMM15

  (106) 0x411df9 VMOVSD	%XMM15,-0x38(%R13)

  (106) 0x411dff VMOVSD	0x90(%RAX),%XMM5

  (106) 0x411e07 VFMADD213SD	-0x30(%R13),%XMM1,%XMM5

  (106) 0x411e0d VMOVSD	%XMM5,-0x30(%R13)

  (106) 0x411e13 VMOVSD	0x98(%RAX),%XMM6

  (106) 0x411e1b VFMADD213SD	-0x28(%R13),%XMM1,%XMM6

  (106) 0x411e21 VMOVSD	%XMM6,-0x28(%R13)

  (106) 0x411e27 VMOVSD	0xa0(%RAX),%XMM4

  (106) 0x411e2f VFMADD213SD	-0x20(%R13),%XMM1,%XMM4

  (106) 0x411e35 VMOVSD	%XMM4,-0x20(%R13)

  (106) 0x411e3b VMOVSD	0xa8(%RAX),%XMM8

  (106) 0x411e43 VFMADD213SD	-0x18(%R13),%XMM1,%XMM8

  (106) 0x411e49 VMOVSD	%XMM8,-0x18(%R13)

  (106) 0x411e4f VMOVSD	0xb0(%RAX),%XMM9

  (106) 0x411e57 VFMADD213SD	-0x10(%R13),%XMM1,%XMM9

  (106) 0x411e5d VMOVSD	%XMM9,-0x10(%R13)

  (106) 0x411e63 VMOVSD	0xb8(%RAX),%XMM2

  (106) 0x411e6b ADD	$0xc0,%RAX

  (106) 0x411e71 VFMADD213SD	-0x8(%R13),%XMM1,%XMM2

  (106) 0x411e77 VMOVSD	%XMM2,-0x8(%R13)

  (106) 0x411e7d CMP	%R13,%R14

  (106) 0x411e80 JNE	411c91

0x411e86 JMP	411a91

0x411e8b XOR	%R15D,%R15D

0x411e8e XOR	%EAX,%EAX

0x411e90 JMP	411975

0x411e9e VMOVSD	(%R12),%XMM13

0x411ea4 ADD	$0x18,%R13

0x411ea8 VFMADD213SD	(%RBX),%XMM1,%XMM13

0x411ead ADD	$0x18,%RAX

0x411eb1 VMOVSD	%XMM13,(%RBX)

0x411eb5 VMOVSD	0x8(%R12),%XMM14

0x411ebc VFMADD213SD	0x8(%RBX),%XMM1,%XMM14

0x411ec2 VMOVSD	%XMM14,0x8(%RBX)

0x411ec7 VMOVSD	0x10(%R12),%XMM15

0x411ece VFMADD213SD	0x10(%RBX),%XMM1,%XMM15

0x411ed4 VMOVSD	%XMM15,0x10(%RBX)

0x411ed9 JMP	411b2c

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

Coverage (%)	Name	Source Location	Module
○99.17	gomp_thread_start	team.c:130	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.09
CQA speedup if FP arith vectorized	1.01
CQA speedup if fully vectorized	1.63
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	micro-operation queue,
Function	advanceVelocity._omp_fn.0
Source	timestep.c:71-71,timestep.c:74-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	34.50
CQA cycles if no scalar integer	31.75
CQA cycles if FP arith vectorized	34.00
CQA cycles if fully vectorized	21.17
Front-end cycles	34.50
P0 cycles	19.83
P1 cycles	19.83
P2 cycles	19.83
P3 cycles	19.83
P4 cycles	19.83
P5 cycles	19.83
P6 cycles	34.00
P7 cycles	34.00
P8 cycles	34.00
P9 cycles	34.00
P10 cycles	21.00
P11 cycles	21.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	26.00
P15 cycles	26.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	262.00
Nb uops	276.00
Nb loads	89.00
Nb stores	42.00
Nb stack references	1.00
FLOP/cycle	6.61
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	114.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	80.23
Bytes prefetched	0.00
Bytes loaded	1856.00
Bytes stored	912.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	24.49
Vectorization ratio load	28.24
Vectorization ratio store	28.57
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	28.57
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	30.53
Vector-efficiency ratio load	33.60
Vector-efficiency ratio store	33.93
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	33.93
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.12

Metric	Value
CQA speedup if no scalar integer	1.09
CQA speedup if FP arith vectorized	1.01
CQA speedup if fully vectorized	1.63
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	micro-operation queue,
Function	advanceVelocity._omp_fn.0
Source	timestep.c:71-71,timestep.c:74-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	34.50
CQA cycles if no scalar integer	31.75
CQA cycles if FP arith vectorized	34.00
CQA cycles if fully vectorized	21.17
Front-end cycles	34.50
P0 cycles	19.83
P1 cycles	19.83
P2 cycles	19.83
P3 cycles	19.83
P4 cycles	19.83
P5 cycles	19.83
P6 cycles	34.00
P7 cycles	34.00
P8 cycles	34.00
P9 cycles	34.00
P10 cycles	21.00
P11 cycles	21.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	26.00
P15 cycles	26.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	262.00
Nb uops	276.00
Nb loads	89.00
Nb stores	42.00
Nb stack references	1.00
FLOP/cycle	6.61
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	114.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	80.23
Bytes prefetched	0.00
Bytes loaded	1856.00
Bytes stored	912.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	24.49
Vectorization ratio load	28.24
Vectorization ratio store	28.57
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	28.57
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	30.53
Vector-efficiency ratio load	33.60
Vector-efficiency ratio store	33.93
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	33.93
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.12

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advanceVelocity._omp_fn.0
Source file and lines	timestep.c:71-78
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71,74-78.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 151 paths individually, rerun with max-paths=151
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 151 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 34.50 to 31.75 cycles (1.09x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 30% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 34.50 to 21.17 cycles (1.63x speedup).

Details

24% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
28% of SSE/AVX stores are used in vector version.
28% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 114 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 5 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
VMOVUPD: 9 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76

Vector unaligned load/store instructions

Detected 18 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 18 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

30 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time). 9 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 228 FP arithmetical operations:

114: addition or subtraction (all inside FMA instructions)
114: multiply (all inside FMA instructions)

The binary loop is loading 1856 bytes (232 double precision FP elements). The binary loop is storing 912 bytes (114 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	262
nb uops	276
loop length	1302
used x86 registers	15
used mmx registers	0
used xmm registers	14
used ymm registers	4
used zmm registers	10
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	34.50 cycles
front end	34.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	19.83	19.83	19.83	19.83	19.83	19.83	34.00	34.00	34.00	34.00	21.00	21.00	0.00	0.00	26.00	26.00
cycles	19.83	19.83	19.83	19.83	19.83	19.83	34.00	34.00	34.00	34.00	21.00	21.00	0.00	0.00	26.00	26.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	34.50
Dispatch	34.00
Overall L1	34.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	28%
load	28%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	28%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	24%
load	28%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	28%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	33%
load	33%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	33%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	30%
load	33%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	33%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 34.50 cycles. At this rate:

21% of peak load performance is reached (53.80 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (26.43 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 4116a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
VMOVQ %XMM7,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSXD (%RSI,%RDI,4),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 411a91 <advanceVelocity._omp_fn.0+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x20(%R11),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA -0x1(%RCX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x20(%R8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%R8),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA (%R10,%R9,1),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R13,%R9,1),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JBE 411ac0 <advanceVelocity._omp_fn.0+0x490>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
LEA (%R13,%R9,1),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0xc0(%R10,%R9,1),%RDX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
LEA 0xc0(%R9),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R10,%R9,1),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 411700 <advanceVelocity._omp_fn.0+0xd0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
ADD %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 411ac0 <advanceVelocity._omp_fn.0+0x490>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x6,%R8D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP $0x6,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JBE 411e8b <advanceVelocity._omp_fn.0+0x85b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x2aaaaaaaaaaaaab,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RSI,%RSI,2),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RBX,%RSI,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0xc0,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x6,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
IMUL %R15,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 411844 <advanceVelocity._omp_fn.0+0x214>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 4117f2 <advanceVelocity._omp_fn.0+0x1c2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x2,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 4117a9 <advanceVelocity._omp_fn.0+0x179>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VMOVUPD (%R12),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R12),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%R12),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD213PD (%RBX),%ZMM0,%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x40(%RBX),%ZMM0,%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x80(%RBX),%ZMM0,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM6,(%RBX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
ADD $0xc0,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM5,0x40(%RBX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
ADD $0xc0,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM4,0x80(%RBX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
VMOVUPD (%RDX),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RDX),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%RDX),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD213PD (%RAX),%ZMM0,%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x40(%RAX),%ZMM0,%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x80(%RAX),%ZMM0,%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM2,(%RAX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
ADD $0xc0,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM8,0x40(%RAX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
ADD $0xc0,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM9,-0x40(%RAX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
VMOVUPD (%RDX),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RDX),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%RDX),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD213PD (%RAX),%ZMM0,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x40(%RAX),%ZMM0,%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x80(%RAX),%ZMM0,%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM10,(%RAX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
ADD $0xc0,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM11,-0x80(%RAX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
ADD $0xc0,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM12,-0x40(%RAX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
CMP %R14,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 411953 <advanceVelocity._omp_fn.0+0x323>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %EAX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 411a91 <advanceVelocity._omp_fn.0+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %EAX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%R14),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JBE 4119c8 <advanceVelocity._omp_fn.0+0x398>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
LEA (%R15,%R15,2),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R9,%R12,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R10,%RSI,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R15D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%RSI),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x20(%RSI),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x40(%RSI),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VFMADD213PD (%RDX),%YMM3,%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD213PD 0x20(%RDX),%YMM3,%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD213PD 0x40(%RDX),%YMM3,%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM13,(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD %YMM14,0x20(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD %YMM15,0x40(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (50.0%)
JE 411a91 <advanceVelocity._omp_fn.0+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOVSXD %R8D,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R8,%R8,2),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x3,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R10,%R14,1),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R13,%R14,1),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%R12),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%RBX),%XMM1,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x8(%R12),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x8(%RBX),%XMM1,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM6,0x8(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x10(%R12),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x10(%RBX),%XMM1,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,0x10(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %ESI,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 411a91 <advanceVelocity._omp_fn.0+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
LEA 0x18(%R10,%R14,1),%RDX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
LEA 0x18(%R13,%R14,1),%R15	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%R15),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%RDX),%XMM1,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM8,(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x8(%R15),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x8(%RDX),%XMM1,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM9,0x8(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x10(%R15),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x10(%RDX),%XMM1,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,0x10(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 411a91 <advanceVelocity._omp_fn.0+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
LEA 0x30(%R10,%R14,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
LEA 0x30(%R13,%R14,1),%R10	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSD (%R10),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%RCX),%XMM1,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM10,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x8(%R10),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x8(%RCX),%XMM1,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM11,0x8(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x10(%R10),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x10(%RCX),%XMM1,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM12,0x10(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x600,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDI,0x3c(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
JG 4116a0 <advanceVelocity._omp_fn.0+0x70>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
LEA (%RCX,%RCX,2),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0xaaaaaaaaaaaaaab,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x18(,%R8,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RBX,%R8,8),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
IMUL %RDX,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 411c91 <advanceVelocity._omp_fn.0+0x661>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 411c4e <advanceVelocity._omp_fn.0+0x61e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x2,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 411c14 <advanceVelocity._omp_fn.0+0x5e4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x3,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 411bda <advanceVelocity._omp_fn.0+0x5aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 411ba0 <advanceVelocity._omp_fn.0+0x570>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x5,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 411b66 <advanceVelocity._omp_fn.0+0x536>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x6,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 411e9e <advanceVelocity._omp_fn.0+0x86e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VMOVSD (%RAX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%R13),%XMM1,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM5,-0x18(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RAX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%R13),%XMM1,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM6,-0x10(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RAX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%R13),%XMM1,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,-0x8(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%R13),%XMM1,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM8,-0x18(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RAX),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%R13),%XMM1,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM9,-0x10(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RAX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%R13),%XMM1,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x8(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%R13),%XMM1,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM10,-0x18(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RAX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%R13),%XMM1,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM11,-0x10(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RAX),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%R13),%XMM1,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM12,-0x8(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%R13),%XMM1,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM13,-0x18(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RAX),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%R13),%XMM1,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM14,-0x10(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RAX),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%R13),%XMM1,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM15,-0x8(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%R13),%XMM1,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM5,-0x18(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RAX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%R13),%XMM1,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM6,-0x10(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RAX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%R13),%XMM1,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,-0x8(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%R13),%XMM1,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM8,-0x18(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%R13),%XMM1,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM9,-0x10(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x10(%RAX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x8(%R13),%XMM1,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x8(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R13,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 411a91 <advanceVelocity._omp_fn.0+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
JMP 411a91 <advanceVelocity._omp_fn.0+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 411975 <advanceVelocity._omp_fn.0+0x345>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R12),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD (%RBX),%XMM1,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM13,(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x8(%R12),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x8(%RBX),%XMM1,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM14,0x8(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x10(%R12),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x10(%RBX),%XMM1,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM15,0x10(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
JMP 411b2c <advanceVelocity._omp_fn.0+0x4fc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.50	N/A

Function	advanceVelocity._omp_fn.0
Source file and lines	timestep.c:71-78
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 151 paths individually, rerun with max-paths=151
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

24% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
28% of SSE/AVX stores are used in vector version.
28% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 114 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 5 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
VMOVUPD: 9 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76

Vector unaligned load/store instructions

Detected 18 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 18 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 228 FP arithmetical operations:

114: addition or subtraction (all inside FMA instructions)
114: multiply (all inside FMA instructions)

The binary loop is loading 1856 bytes (232 double precision FP elements). The binary loop is storing 912 bytes (114 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	262
nb uops	276
loop length	1302
used x86 registers	15
used mmx registers	0
used xmm registers	14
used ymm registers	4
used zmm registers	10
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	34.50 cycles
front end	34.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	19.83	19.83	19.83	19.83	19.83	19.83	34.00	34.00	34.00	34.00	21.00	21.00	0.00	0.00	26.00	26.00
cycles	19.83	19.83	19.83	19.83	19.83	19.83	34.00	34.00	34.00	34.00	21.00	21.00	0.00	0.00	26.00	26.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	34.50
Dispatch	34.00
Overall L1	34.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	28%
load	28%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	28%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	24%
load	28%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	28%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	33%
load	33%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	33%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	30%
load	33%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	33%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 34.50 cycles. At this rate:

21% of peak load performance is reached (53.80 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (26.43 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 4116a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
VMOVQ %XMM7,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSXD (%RSI,%RDI,4),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 411a91 <advanceVelocity._omp_fn.0+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x20(%R11),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA -0x1(%RCX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x20(%R8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%R8),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA (%R10,%R9,1),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R13,%R9,1),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JBE 411ac0 <advanceVelocity._omp_fn.0+0x490>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
LEA (%R13,%R9,1),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0xc0(%R10,%R9,1),%RDX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
LEA 0xc0(%R9),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R10,%R9,1),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 411700 <advanceVelocity._omp_fn.0+0xd0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
ADD %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 411ac0 <advanceVelocity._omp_fn.0+0x490>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x6,%R8D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP $0x6,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JBE 411e8b <advanceVelocity._omp_fn.0+0x85b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x2aaaaaaaaaaaaab,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RSI,%RSI,2),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RBX,%RSI,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0xc0,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x6,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
IMUL %R15,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 411844 <advanceVelocity._omp_fn.0+0x214>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 4117f2 <advanceVelocity._omp_fn.0+0x1c2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x2,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 4117a9 <advanceVelocity._omp_fn.0+0x179>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VMOVUPD (%R12),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R12),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%R12),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD213PD (%RBX),%ZMM0,%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x40(%RBX),%ZMM0,%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x80(%RBX),%ZMM0,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM6,(%RBX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
ADD $0xc0,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM5,0x40(%RBX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
ADD $0xc0,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM4,0x80(%RBX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
VMOVUPD (%RDX),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RDX),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%RDX),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD213PD (%RAX),%ZMM0,%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x40(%RAX),%ZMM0,%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x80(%RAX),%ZMM0,%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM2,(%RAX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
ADD $0xc0,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM8,0x40(%RAX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
ADD $0xc0,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM9,-0x40(%RAX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
VMOVUPD (%RDX),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RDX),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%RDX),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD213PD (%RAX),%ZMM0,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x40(%RAX),%ZMM0,%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x80(%RAX),%ZMM0,%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM10,(%RAX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
ADD $0xc0,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM11,-0x80(%RAX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
ADD $0xc0,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM12,-0x40(%RAX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	4	1	vect (100.0%)
CMP %R14,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 411953 <advanceVelocity._omp_fn.0+0x323>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %EAX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 411a91 <advanceVelocity._omp_fn.0+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %EAX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%R14),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JBE 4119c8 <advanceVelocity._omp_fn.0+0x398>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
LEA (%R15,%R15,2),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R9,%R12,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R10,%RSI,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R15D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%RSI),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x20(%RSI),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x40(%RSI),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VFMADD213PD (%RDX),%YMM3,%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD213PD 0x20(%RDX),%YMM3,%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD213PD 0x40(%RDX),%YMM3,%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM13,(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD %YMM14,0x20(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD %YMM15,0x40(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (50.0%)
JE 411a91 <advanceVelocity._omp_fn.0+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOVSXD %R8D,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R8,%R8,2),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x3,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R10,%R14,1),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R13,%R14,1),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%R12),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%RBX),%XMM1,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x8(%R12),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x8(%RBX),%XMM1,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM6,0x8(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x10(%R12),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x10(%RBX),%XMM1,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,0x10(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %ESI,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 411a91 <advanceVelocity._omp_fn.0+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
LEA 0x18(%R10,%R14,1),%RDX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
LEA 0x18(%R13,%R14,1),%R15	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%R15),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%RDX),%XMM1,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM8,(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x8(%R15),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x8(%RDX),%XMM1,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM9,0x8(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x10(%R15),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x10(%RDX),%XMM1,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,0x10(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 411a91 <advanceVelocity._omp_fn.0+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
LEA 0x30(%R10,%R14,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
LEA 0x30(%R13,%R14,1),%R10	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSD (%R10),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%RCX),%XMM1,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM10,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x8(%R10),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x8(%RCX),%XMM1,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM11,0x8(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x10(%R10),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x10(%RCX),%XMM1,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM12,0x10(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x600,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDI,0x3c(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
JG 4116a0 <advanceVelocity._omp_fn.0+0x70>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
LEA (%RCX,%RCX,2),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0xaaaaaaaaaaaaaab,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x18(,%R8,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RBX,%R8,8),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
IMUL %RDX,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 411c91 <advanceVelocity._omp_fn.0+0x661>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 411c4e <advanceVelocity._omp_fn.0+0x61e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x2,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 411c14 <advanceVelocity._omp_fn.0+0x5e4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x3,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 411bda <advanceVelocity._omp_fn.0+0x5aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 411ba0 <advanceVelocity._omp_fn.0+0x570>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x5,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 411b66 <advanceVelocity._omp_fn.0+0x536>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x6,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 411e9e <advanceVelocity._omp_fn.0+0x86e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VMOVSD (%RAX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%R13),%XMM1,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM5,-0x18(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RAX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%R13),%XMM1,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM6,-0x10(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RAX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%R13),%XMM1,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,-0x8(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%R13),%XMM1,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM8,-0x18(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RAX),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%R13),%XMM1,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM9,-0x10(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RAX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%R13),%XMM1,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x8(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%R13),%XMM1,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM10,-0x18(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RAX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%R13),%XMM1,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM11,-0x10(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RAX),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%R13),%XMM1,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM12,-0x8(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%R13),%XMM1,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM13,-0x18(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RAX),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%R13),%XMM1,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM14,-0x10(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RAX),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%R13),%XMM1,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM15,-0x8(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%R13),%XMM1,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM5,-0x18(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x10(%RAX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%R13),%XMM1,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM6,-0x10(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x8(%RAX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x8(%R13),%XMM1,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,-0x8(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%R13),%XMM1,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM8,-0x18(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD -0x10(%R13),%XMM1,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM9,-0x10(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x10(%RAX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x8(%R13),%XMM1,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x8(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R13,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 411a91 <advanceVelocity._omp_fn.0+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A
JMP 411a91 <advanceVelocity._omp_fn.0+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 411975 <advanceVelocity._omp_fn.0+0x345>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R12),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x18,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD (%RBX),%XMM1,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM13,(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x8(%R12),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x8(%RBX),%XMM1,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM14,0x8(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x10(%R12),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x10(%RBX),%XMM1,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM15,0x10(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
JMP 411b2c <advanceVelocity._omp_fn.0+0x4fc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code