OV - exec - Function kineticEnergy._omp

	Function: kineticEnergy._omp_fn.0	Module: exec	Source: timestep.c:107-116	Coverage (incl. loops): 0.13% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 107 - 116

--------------------------------------------------------------------------------

107:    #pragma omp parallel for reduction(+:kenergy)

108:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

109:    {

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

0x411ee0 PUSH	%RBP

0x411ee1 MOV	%RSP,%RBP

0x411ee4 PUSH	%R14

0x411ee6 PUSH	%R13

0x411ee8 PUSH	%R12

0x411eea PUSH	%RBX

0x411eeb MOV	(%RDI),%RBX

0x411eee MOV	%RDI,%R12

0x411ef1 CALL	4032e0 <omp_get_num_threads@plt>

0x411ef6 MOV	%EAX,%R13D

0x411ef9 CALL	403290 <omp_get_thread_num@plt>

0x411efe MOV	%EAX,%ECX

0x411f00 MOV	0x18(%RBX),%R14

0x411f04 MOV	0xc(%R14),%EAX

0x411f08 CLTD

0x411f09 IDIV	%R13D

0x411f0c CMP	%EDX,%ECX

0x411f0e JL	412173

0x411f14 IMUL	%EAX,%ECX

0x411f17 VXORPD	%XMM0,%XMM0,%XMM0

0x411f1b ADD	%ECX,%EDX

0x411f1d LEA	(%RAX,%RDX,1),%ESI

0x411f20 CMP	%ESI,%EDX

0x411f22 JGE	41214b

0x411f28 MOV	0x78(%R14),%RDI

0x411f2c MOVSXD	%EDX,%R10

0x411f2f MOV	%EAX,%R11D

0x411f32 VMOVSD	0x2bfe(%RIP),%XMM3

0x411f3a ADD	%R10,%R11

0x411f3d LEA	(%R10,%R10,2),%R13

0x411f41 MOV	%R10,%R8

0x411f44 SAL	$0x9,%R13

0x411f48 SAL	$0x6,%R8

0x411f4c LEA	(%RDI,%R10,4),%R9

0x411f50 LEA	(%R11,%R11,2),%R10

0x411f54 SAL	$0x9,%R10

0x411f58 NOPL	(%RAX,%RAX,1)

(109) 0x411f60 MOVSXD	(%R9),%RCX

(109) 0x411f63 TEST	%ECX,%ECX

(109) 0x411f65 JLE	412133

(109) 0x411f6b MOV	0x20(%RBX),%R14

(109) 0x411f6f ADD	%R8,%RCX

(109) 0x411f72 MOVSXD	%R8D,%RAX

(109) 0x411f75 MOV	0x28(%RBX),%RDI

(109) 0x411f79 MOV	0x10(%R14),%RSI

(109) 0x411f7d LEA	(%RSI,%RCX,4),%R11

(109) 0x411f81 LEA	(%RSI,%RAX,4),%RDX

(109) 0x411f85 MOV	0x20(%R14),%RAX

(109) 0x411f89 MOV	%R11,%RCX

(109) 0x411f8c SUB	%RDX,%RCX

(109) 0x411f8f SUB	$0x4,%RCX

(109) 0x411f93 SHR	$0x2,%RCX

(109) 0x411f97 INC	%RCX

(109) 0x411f9a ADD	%R13,%RAX

(109) 0x411f9d AND	$0x3,%ECX

(109) 0x411fa0 JE	412060

(109) 0x411fa6 CMP	$0x1,%RCX

(109) 0x411faa JE	412020

(109) 0x411fac CMP	$0x2,%RCX

(109) 0x411fb0 JE	411fe9

(109) 0x411fb2 VMOVSD	(%RAX),%XMM1

(109) 0x411fb6 VMOVSD	0x8(%RAX),%XMM2

(109) 0x411fbb VMULSD	%XMM2,%XMM2,%XMM5

(109) 0x411fbf VFMADD231SD	%XMM1,%XMM1,%XMM5

(109) 0x411fc4 MOVSXD	(%RDX),%R14

(109) 0x411fc7 VMOVSD	0x10(%RAX),%XMM6

(109) 0x411fcc ADD	$0x4,%RDX

(109) 0x411fd0 ADD	$0x18,%RAX

(109) 0x411fd4 VFMADD132SD	%XMM6,%XMM5,%XMM6

(109) 0x411fd9 SAL	$0x4,%R14

(109) 0x411fdd VDIVSD	0x8(%RDI,%R14,1),%XMM3,%XMM4

(109) 0x411fe4 VFMADD231SD	%XMM6,%XMM4,%XMM0

(109) 0x411fe9 VMOVSD	(%RAX),%XMM8

(109) 0x411fed VMOVSD	0x8(%RAX),%XMM9

(109) 0x411ff2 VMULSD	%XMM9,%XMM9,%XMM10

(109) 0x411ff7 VFMADD231SD	%XMM8,%XMM8,%XMM10

(109) 0x411ffc MOVSXD	(%RDX),%RSI

(109) 0x411fff VMOVSD	0x10(%RAX),%XMM11

(109) 0x412004 ADD	$0x4,%RDX

(109) 0x412008 ADD	$0x18,%RAX

(109) 0x41200c VFMADD132SD	%XMM11,%XMM10,%XMM11

(109) 0x412011 SAL	$0x4,%RSI

(109) 0x412015 VDIVSD	0x8(%RDI,%RSI,1),%XMM3,%XMM7

(109) 0x41201b VFMADD231SD	%XMM11,%XMM7,%XMM0

(109) 0x412020 VMOVSD	(%RAX),%XMM13

(109) 0x412024 VMOVSD	0x8(%RAX),%XMM14

(109) 0x412029 VMULSD	%XMM14,%XMM14,%XMM15

(109) 0x41202e VFMADD231SD	%XMM13,%XMM13,%XMM15

(109) 0x412033 MOVSXD	(%RDX),%RCX

(109) 0x412036 VMOVSD	0x10(%RAX),%XMM4

(109) 0x41203b ADD	$0x4,%RDX

(109) 0x41203f ADD	$0x18,%RAX

(109) 0x412043 VFMADD132SD	%XMM4,%XMM15,%XMM4

(109) 0x412048 SAL	$0x4,%RCX

(109) 0x41204c VDIVSD	0x8(%RDI,%RCX,1),%XMM3,%XMM12

(109) 0x412052 VFMADD231SD	%XMM4,%XMM12,%XMM0

(109) 0x412057 CMP	%RDX,%R11

(109) 0x41205a JE	412133

  (110) 0x412060 VMOVSD	(%RAX),%XMM1

  (110) 0x412064 VMOVSD	0x8(%RAX),%XMM2

  (110) 0x412069 VMULSD	%XMM2,%XMM2,%XMM6

  (110) 0x41206d VFMADD231SD	%XMM1,%XMM1,%XMM6

  (110) 0x412072 MOVSXD	(%RDX),%R14

  (110) 0x412075 VMOVSD	0x10(%RAX),%XMM7

  (110) 0x41207a VMOVSD	0x20(%RAX),%XMM9

  (110) 0x41207f VMULSD	%XMM9,%XMM9,%XMM10

  (110) 0x412084 MOVSXD	0x4(%RDX),%RSI

  (110) 0x412088 VMOVSD	0x28(%RAX),%XMM11

  (110) 0x41208d VMOVSD	0x30(%RAX),%XMM13

  (110) 0x412092 VMOVSD	0x38(%RAX),%XMM14

  (110) 0x412097 VMULSD	%XMM14,%XMM14,%XMM15

  (110) 0x41209c VFMADD231SD	%XMM13,%XMM13,%XMM15

  (110) 0x4120a1 MOVSXD	0x8(%RDX),%RCX

  (110) 0x4120a5 VMOVSD	0x40(%RAX),%XMM4

  (110) 0x4120aa VFMADD132SD	%XMM7,%XMM6,%XMM7

  (110) 0x4120af VMOVSD	0x50(%RAX),%XMM1

  (110) 0x4120b4 VMULSD	%XMM1,%XMM1,%XMM2

  (110) 0x4120b8 VMOVSD	0x58(%RAX),%XMM6

  (110) 0x4120bd ADD	$0x10,%RDX

  (110) 0x4120c1 ADD	$0x60,%RAX

  (110) 0x4120c5 SAL	$0x4,%R14

  (110) 0x4120c9 VFMADD132SD	%XMM4,%XMM15,%XMM4

  (110) 0x4120ce VDIVSD	0x8(%RDI,%R14,1),%XMM3,%XMM5

  (110) 0x4120d5 VFMADD132SD	%XMM7,%XMM0,%XMM5

  (110) 0x4120da VMOVSD	-0x48(%RAX),%XMM0

  (110) 0x4120df VFMADD231SD	%XMM0,%XMM0,%XMM10

  (110) 0x4120e4 SAL	$0x4,%RSI

  (110) 0x4120e8 VDIVSD	0x8(%RDI,%RSI,1),%XMM3,%XMM8

  (110) 0x4120ee MOVSXD	-0x4(%RDX),%R14

  (110) 0x4120f2 VFMADD132SD	%XMM11,%XMM10,%XMM11

  (110) 0x4120f7 SAL	$0x4,%RCX

  (110) 0x4120fb VDIVSD	0x8(%RDI,%RCX,1),%XMM3,%XMM12

  (110) 0x412101 VFMADD132SD	%XMM11,%XMM5,%XMM8

  (110) 0x412106 VMOVSD	-0x18(%RAX),%XMM5

  (110) 0x41210b VFMADD231SD	%XMM5,%XMM5,%XMM2

  (110) 0x412110 SAL	$0x4,%R14

  (110) 0x412114 VDIVSD	0x8(%RDI,%R14,1),%XMM3,%XMM0

  (110) 0x41211b VFMADD132SD	%XMM4,%XMM8,%XMM12

  (110) 0x412120 VFMADD132SD	%XMM6,%XMM2,%XMM6

  (110) 0x412125 VFMADD132SD	%XMM6,%XMM12,%XMM0

  (110) 0x41212a CMP	%RDX,%R11

  (110) 0x41212d JNE	412060

(109) 0x412133 ADD	$0x600,%R13

(109) 0x41213a ADD	$0x4,%R9

(109) 0x41213e ADD	$0x40,%R8

(109) 0x412142 CMP	%R13,%R10

(109) 0x412145 JNE	411f60

0x41214b MOV	0x8(%R12),%RAX

0x412150 LEA	0x8(%R12),%RBX

(108) 0x412155 VMOVQ	%RAX,%XMM3

(108) 0x41215a VADDSD	%XMM3,%XMM0,%XMM7

(108) 0x41215e VMOVQ	%XMM7,%R12

(108) 0x412163 LOCK CMPXCHG	%R12,(%RBX)

(108) 0x412168 JNE	412155

0x41216a POP	%RBX

0x41216b POP	%R12

0x41216d POP	%R13

0x41216f POP	%R14

0x412171 POP	%RBP

0x412172 RET

0x412173 INC	%EAX

0x412175 XOR	%EDX,%EDX

0x412177 JMP	411f14

0x41217c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○100.00	gomp_thread_start	team.c:130	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	timestep.c:107-116
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107-116.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.13 to 0.88 cycles (7.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.13 to 0.41 cycles (15.08x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107
omp_get_thread_num@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:108

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:108

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes.

General properties

nb instructions	49
nb uops	49
loop length	160
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.13 cycles
front end	6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.83	3.83	3.83	3.83	3.83	3.83	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.83	3.83	3.83	3.83	3.83	3.83	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	6.13
Dispatch	3.83
DIV/SQRT	6.00
Overall L1	6.13

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	7%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.13 cycles. At this rate:

2% of peak load performance is reached (7.18 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 411ee0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV (%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 4032e0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403290 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x18(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc(%R14),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 412173 <kineticEnergy._omp_fn.0+0x293>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 41214b <kineticEnergy._omp_fn.0+0x26b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %EDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x2bfe(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R10,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R10,%R10,2),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x9,%R13	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SAL $0x6,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA (%RDI,%R10,4),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R11,%R11,2),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x9,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x8(%R12),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x8(%R12),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 411f14 <kineticEnergy._omp_fn.0+0x34>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	timestep.c:107-116
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.13 to 0.88 cycles (7.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107
omp_get_thread_num@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:108

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:108

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes.

General properties

nb instructions	49
nb uops	49
loop length	160
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.13 cycles
front end	6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.83	3.83	3.83	3.83	3.83	3.83	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.83	3.83	3.83	3.83	3.83	3.83	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	6.13
Dispatch	3.83
DIV/SQRT	6.00
Overall L1	6.13

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	7%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.13 cycles. At this rate:

2% of peak load performance is reached (7.18 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 411ee0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV (%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 4032e0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403290 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x18(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc(%R14),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 412173 <kineticEnergy._omp_fn.0+0x293>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 41214b <kineticEnergy._omp_fn.0+0x26b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %EDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x2bfe(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R10,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R10,%R10,2),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x9,%R13	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SAL $0x6,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA (%RDI,%R10,4),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R11,%R11,2),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x9,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x8(%R12),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x8(%R12),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 411f14 <kineticEnergy._omp_fn.0+0x34>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

Name	Coverage (%)	Time (s)
▼kineticEnergy._omp_fn.0–	0.13	0.01
▼Loop 109 - timestep.c:110-116 - exec–	0.01	0.01
○Loop 110 - timestep.c:110-116 - exec	0.11	0.01
○Loop 108 - timestep.c:107-107 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code