OV - exec - Function ljForce._omp

	Function: ljForce._omp_fn.1	Module: exec	Source: ljForce.c:172-216 [...]	Coverage (incl. loops): 66.07% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 172 - 216

--------------------------------------------------------------------------------

172:    #pragma omp parallel for reduction(+:ePot)

173:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

174:    {

175:       int nIBox = s->boxes->nAtoms[iBox];

176:

177:       // loop over neighbors of iBox

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

0x40e3b0 PUSH	%RBP

0x40e3b1 MOV	%RSP,%RBP

0x40e3b4 PUSH	%R15

0x40e3b6 PUSH	%R14

0x40e3b8 PUSH	%R13

0x40e3ba PUSH	%R12

0x40e3bc PUSH	%RBX

0x40e3bd MOV	%RDI,%RBX

0x40e3c0 SUB	$0x38,%RSP

0x40e3c4 MOV	(%RDI),%RAX

0x40e3c7 MOV	0x18(%RAX),%R12

0x40e3cb MOV	%RAX,-0x48(%RBP)

0x40e3cf CALL	4032e0 <omp_get_num_threads@plt>

0x40e3d4 MOV	%EAX,%R13D

0x40e3d7 CALL	403290 <omp_get_thread_num@plt>

0x40e3dc MOV	%EAX,%ECX

0x40e3de MOV	0xc(%R12),%EAX

0x40e3e3 CLTD

0x40e3e4 IDIV	%R13D

0x40e3e7 CMP	%EDX,%ECX

0x40e3e9 JL	40ea85

0x40e3ef IMUL	%EAX,%ECX

0x40e3f2 ADD	%ECX,%EDX

0x40e3f4 LEA	(%RAX,%RDX,1),%R11D

0x40e3f8 CMP	%R11D,%EDX

0x40e3fb JGE	40ea9b

0x40e401 MOV	0x30(%RBX),%R8D

0x40e405 MOVSXD	%EDX,%RSI

0x40e408 MOV	%EDX,%R9D

0x40e40b MOV	0x78(%R12),%R15

0x40e410 MOV	%RSI,%RDI

0x40e413 VMOVSD	0x20(%RBX),%XMM11

0x40e418 VMOVSD	0x18(%RBX),%XMM12

0x40e41d VMOVSD	0x10(%RBX),%XMM5

0x40e422 NOT	%RDI

0x40e425 VMOVSD	0x8(%RBX),%XMM13

0x40e42a ADD	%R11D,%EDI

0x40e42d SAL	$0x6,%R9D

0x40e431 MOVSXD	%R8D,%R10

0x40e434 AND	$0x7,%EDI

0x40e437 SAL	$0x2,%R10

0x40e43b TEST	%R8D,%R8D

0x40e43e JLE	40eaa1

0x40e444 MOV	(%R15,%RSI,4),%R14D

0x40e448 MOV	0x80(%R12),%RDI

0x40e450 MOV	%R10,%RAX

0x40e453 VXORPD	%XMM7,%XMM7,%XMM7

0x40e457 VMOVSD	0x6a61(%RIP),%XMM9

0x40e45f VMOVSD	0x6a61(%RIP),%XMM8

0x40e467 VMOVSD	0x6a61(%RIP),%XMM15

0x40e46f VMOVSD	0x6a61(%RIP),%XMM14

0x40e477 MOV	%R9D,-0x34(%RBP)

0x40e47b MOV	%RBX,-0x50(%RBP)

0x40e47f VMOVD	%R14D,%XMM23

(92) 0x40e485 MOV	(%RDI,%RSI,8),%RCX

(92) 0x40e489 MOV	-0x34(%RBP),%R13D

(92) 0x40e48d MOV	%ESI,%R8D

(92) 0x40e490 VMOVD	%XMM23,%EBX

(92) 0x40e496 VMOVQ	%R15,%XMM24

(92) 0x40e49c VMOVQ	%RDI,%XMM20

(92) 0x40e4a2 MOV	%R11D,-0x38(%RBP)

(92) 0x40e4a6 MOV	%RSI,-0x58(%RBP)

(92) 0x40e4aa SAL	$0x6,%R8D

(92) 0x40e4ae MOV	%RAX,-0x60(%RBP)

(92) 0x40e4b2 MOVSXD	%R8D,%R10

(92) 0x40e4b5 LEA	(%RAX,%RCX,1),%RDX

(92) 0x40e4b9 LEA	(,%R10,8),%R12

(92) 0x40e4c1 LEA	(%RBX,%R13,1),%R9D

(92) 0x40e4c5 MOV	%RCX,%R10

(92) 0x40e4c8 VMOVQ	%RDX,%XMM19

(92) 0x40e4ce MOV	%R12,-0x40(%RBP)

  (91) 0x40e4d2 MOV	(%R10),%ESI

  (91) 0x40e4d5 TEST	%ESI,%ESI

  (91) 0x40e4d7 JS	40eb70

  (91) 0x40e4dd MOVSXD	%ESI,%R15

  (91) 0x40e4e0 VMOVQ	%XMM24,%RAX

  (91) 0x40e4e6 VMOVD	%XMM23,%EDI

  (91) 0x40e4ec MOV	(%RAX,%R15,4),%R11D

  (91) 0x40e4f0 TEST	%EDI,%EDI

  (91) 0x40e4f2 JLE	40e5e0

  (91) 0x40e4f8 MOV	-0x34(%RBP),%EBX

  (91) 0x40e4fb LEA	(%R15,%R15,2),%R8

  (91) 0x40e4ff MOV	-0x40(%RBP),%R14

  (91) 0x40e503 SAL	$0x6,%ESI

  (91) 0x40e506 SAL	$0x9,%R8

  (91) 0x40e50a MOV	%EBX,%R13D

  (91) 0x40e50d NOT	%EBX

  (91) 0x40e50f LEA	(%R11,%RSI,1),%EDX

  (91) 0x40e513 ADD	%R9D,%EBX

  (91) 0x40e516 AND	$0x7,%EBX

  (91) 0x40e519 TEST	%R11D,%R11D

  (91) 0x40e51c JG	40e62a

  (91) 0x40e522 MOV	-0x34(%RBP),%R14D

  (91) 0x40e526 MOV	-0x40(%RBP),%RCX

  (91) 0x40e52a LEA	0x1(%R14),%R13D

  (91) 0x40e52e LEA	0x8(%RCX),%R14

  (91) 0x40e532 CMP	%R9D,%R13D

  (91) 0x40e535 JGE	40e5e0

  (91) 0x40e53b TEST	%EBX,%EBX

  (91) 0x40e53d JE	40e5ce

  (91) 0x40e543 CMP	$0x1,%EBX

  (91) 0x40e546 JE	40e5bd

  (91) 0x40e548 CMP	$0x2,%EBX

  (91) 0x40e54b JE	40e5b1

  (91) 0x40e54d CMP	$0x3,%EBX

  (91) 0x40e550 JE	40e5a1

  (91) 0x40e552 CMP	$0x4,%EBX

  (91) 0x40e555 JE	40e591

  (91) 0x40e557 CMP	$0x5,%EBX

  (91) 0x40e55a JE	40e581

  (91) 0x40e55c CMP	$0x6,%EBX

  (91) 0x40e55f JE	40e571

  (91) 0x40e561 TEST	%R11D,%R11D

  (91) 0x40e564 JG	40e62a

  (91) 0x40e56a INC	%R13D

  (91) 0x40e56d ADD	$0x8,%R14

  (91) 0x40e571 TEST	%R11D,%R11D

  (91) 0x40e574 JG	40e62a

  (91) 0x40e57a INC	%R13D

  (91) 0x40e57d ADD	$0x8,%R14

  (91) 0x40e581 TEST	%R11D,%R11D

  (91) 0x40e584 JG	40e62a

  (91) 0x40e58a INC	%R13D

  (91) 0x40e58d ADD	$0x8,%R14

  (91) 0x40e591 TEST	%R11D,%R11D

  (91) 0x40e594 JG	40e62a

  (91) 0x40e59a INC	%R13D

  (91) 0x40e59d ADD	$0x8,%R14

  (91) 0x40e5a1 TEST	%R11D,%R11D

  (91) 0x40e5a4 JG	40e62a

  (91) 0x40e5aa INC	%R13D

  (91) 0x40e5ad ADD	$0x8,%R14

  (91) 0x40e5b1 TEST	%R11D,%R11D

  (91) 0x40e5b4 JG	40e62a

  (91) 0x40e5b6 INC	%R13D

  (91) 0x40e5b9 ADD	$0x8,%R14

  (91) 0x40e5bd TEST	%R11D,%R11D

  (91) 0x40e5c0 JG	40e62a

  (91) 0x40e5c2 INC	%R13D

  (91) 0x40e5c5 ADD	$0x8,%R14

  (91) 0x40e5c9 CMP	%R9D,%R13D

  (91) 0x40e5cc JGE	40e5e0

    (95) 0x40e5ce TEST	%R11D,%R11D

    (95) 0x40e5d1 JG	40e62a

    (95) 0x40e5d3 ADD	$0x8,%R13D

    (95) 0x40e5d7 ADD	$0x40,%R14

    (95) 0x40e5db CMP	%R9D,%R13D

    (95) 0x40e5de JL	40e5ce

  (91) 0x40e5e0 ADD	$0x4,%R10

  (91) 0x40e5e4 VMOVQ	%XMM19,%R14

  (91) 0x40e5ea CMP	%R14,%R10

  (91) 0x40e5ed JNE	40e4d2

(92) 0x40e5f3 MOV	-0x58(%RBP),%RSI

(92) 0x40e5f7 MOV	-0x38(%RBP),%R11D

(92) 0x40e5fb MOV	-0x60(%RBP),%RAX

(92) 0x40e5ff VMOVQ	%XMM24,%R15

(92) 0x40e605 VMOVQ	%XMM20,%RDI

(92) 0x40e60b ADDL	$0x40,-0x34(%RBP)

(92) 0x40e60f INC	%RSI

(92) 0x40e612 CMP	%ESI,%R11D

(92) 0x40e615 JLE	40ea48

(92) 0x40e61b MOV	(%R15,%RSI,4),%R9D

(92) 0x40e61f VMOVD	%R9D,%XMM23

(92) 0x40e625 JMP	40e485

  (91) 0x40e62a MOV	-0x48(%RBP),%R12

  (91) 0x40e62e MOV	%R10,%R11

  (91) 0x40e631 MOV	%EDX,%EBX

  (91) 0x40e633 MOV	%R8,%R10

  (91) 0x40e636 MOV	%ESI,%R8D

  (91) 0x40e639 MOV	%R13D,%ESI

  (91) 0x40e63c VMOVSD	0x689c(%RIP),%XMM10

  (91) 0x40e644 MOV	0x20(%R12),%R12

  (91) 0x40e649 NOPL	(%RAX)

    (93) 0x40e650 MOV	0x18(%R12),%RDI

    (93) 0x40e655 LEA	(%R14,%R14,2),%R15

    (93) 0x40e659 VXORPD	%XMM4,%XMM4,%XMM4

    (93) 0x40e65d MOV	%R8D,%ECX

    (93) 0x40e660 NOT	%ECX

    (93) 0x40e662 ADD	%EBX,%ECX

    (93) 0x40e664 AND	$0x1,%ECX

    (93) 0x40e667 LEA	(%RDI,%R15,1),%R13

    (93) 0x40e66b ADD	%R10,%RDI

    (93) 0x40e66e VMOVSD	(%R13),%XMM3

    (93) 0x40e674 VSUBSD	(%RDI),%XMM3,%XMM6

    (93) 0x40e678 VMOVAPD	%XMM6,%XMM1

    (93) 0x40e67c VMOVSD	0x8(%R13),%XMM2

    (93) 0x40e682 VFMADD132SD	%XMM6,%XMM4,%XMM1

    (93) 0x40e687 VSUBSD	0x8(%RDI),%XMM2,%XMM3

    (93) 0x40e68c VMOVSD	0x10(%R13),%XMM16

    (93) 0x40e693 VSUBSD	0x10(%RDI),%XMM16,%XMM21

    (93) 0x40e69a VFMADD231SD	%XMM3,%XMM3,%XMM1

    (93) 0x40e69f VFMADD231SD	%XMM21,%XMM21,%XMM1

    (93) 0x40e6a5 VCOMISD	%XMM1,%XMM5

    (93) 0x40e6a9 JB	40e750

    (93) 0x40e6af VCOMISD	%XMM4,%XMM1

    (93) 0x40e6b3 JBE	40e750

    (93) 0x40e6b9 VDIVSD	%XMM1,%XMM9,%XMM1

    (93) 0x40e6bd VMULSD	%XMM1,%XMM1,%XMM17

    (93) 0x40e6c3 VMULSD	%XMM1,%XMM17,%XMM18

    (93) 0x40e6c9 VMULSD	%XMM12,%XMM18,%XMM22

    (93) 0x40e6cf VSUBSD	%XMM9,%XMM22,%XMM25

    (93) 0x40e6d5 VFMSUB132SD	%XMM22,%XMM11,%XMM25

    (93) 0x40e6db MOV	0x30(%R12),%RAX

    (93) 0x40e6e0 MOV	0x28(%R12),%RDX

    (93) 0x40e6e5 VMOVAPD	%XMM22,%XMM2

    (93) 0x40e6eb VMULSD	%XMM15,%XMM13,%XMM26

    (93) 0x40e6f1 VMULSD	%XMM22,%XMM26,%XMM27

    (93) 0x40e6f7 VMULSD	%XMM1,%XMM27,%XMM28

    (93) 0x40e6fd VFMADD132SD	%XMM14,%XMM10,%XMM2

    (93) 0x40e702 VFMADD231SD	%XMM8,%XMM25,%XMM7

    (93) 0x40e708 VMOVAPD	%XMM25,%XMM0

    (93) 0x40e70e ADD	%R15,%RDX

    (93) 0x40e711 ADD	%R14,%RAX

    (93) 0x40e714 VFMADD213SD	(%RAX),%XMM8,%XMM0

    (93) 0x40e719 VMULSD	%XMM28,%XMM2,%XMM1

    (93) 0x40e71f VMOVSD	%XMM0,(%RAX)

    (93) 0x40e723 VFNMADD213SD	(%RDX),%XMM1,%XMM6

    (93) 0x40e728 VFNMADD213SD	0x8(%RDX),%XMM1,%XMM3

    (93) 0x40e72e VMOVSD	%XMM6,(%RDX)

    (93) 0x40e732 VFNMADD213SD	0x10(%RDX),%XMM21,%XMM1

    (93) 0x40e739 VMOVSD	%XMM3,0x8(%RDX)

    (93) 0x40e73e VMOVSD	%XMM1,0x10(%RDX)

    (93) 0x40e743 NOPW	%CS:(%RAX,%RAX,1)

    (93) 0x40e74e XCHG	%AX,%AX

    (93) 0x40e750 LEA	0x1(%R8),%EDX

    (93) 0x40e754 LEA	0x18(%RDI),%RAX

    (93) 0x40e758 CMP	%EBX,%EDX

    (93) 0x40e75a JGE	40ea1e

    (93) 0x40e760 TEST	%ECX,%ECX

    (93) 0x40e762 JE	40e850

    (93) 0x40e768 VMOVSD	(%R13),%XMM6

    (93) 0x40e76e VSUBSD	0x18(%RDI),%XMM6,%XMM3

    (93) 0x40e773 VMOVAPD	%XMM3,%XMM0

    (93) 0x40e777 VMOVSD	0x8(%R13),%XMM2

    (93) 0x40e77d VFMADD132SD	%XMM3,%XMM4,%XMM0

    (93) 0x40e782 VSUBSD	0x8(%RAX),%XMM2,%XMM6

    (93) 0x40e787 VMOVSD	0x10(%R13),%XMM29

    (93) 0x40e78e VSUBSD	0x10(%RAX),%XMM29,%XMM30

    (93) 0x40e795 VFMADD231SD	%XMM6,%XMM6,%XMM0

    (93) 0x40e79a VFMADD231SD	%XMM30,%XMM30,%XMM0

    (93) 0x40e7a0 VCOMISD	%XMM0,%XMM5

    (93) 0x40e7a4 JB	40e840

    (93) 0x40e7aa VCOMISD	%XMM4,%XMM0

    (93) 0x40e7ae JBE	40e840

    (93) 0x40e7b4 VDIVSD	%XMM0,%XMM9,%XMM1

    (93) 0x40e7b8 VMULSD	%XMM1,%XMM1,%XMM31

    (93) 0x40e7be VMULSD	%XMM1,%XMM31,%XMM16

    (93) 0x40e7c4 VMULSD	%XMM12,%XMM16,%XMM21

    (93) 0x40e7ca VSUBSD	%XMM9,%XMM21,%XMM17

    (93) 0x40e7d0 VFMSUB132SD	%XMM21,%XMM11,%XMM17

    (93) 0x40e7d6 MOV	0x30(%R12),%RDI

    (93) 0x40e7db MOV	0x28(%R12),%RCX

    (93) 0x40e7e0 VMOVAPD	%XMM21,%XMM2

    (93) 0x40e7e6 VMULSD	%XMM15,%XMM13,%XMM18

    (93) 0x40e7ec VMULSD	%XMM21,%XMM18,%XMM22

    (93) 0x40e7f2 VMULSD	%XMM1,%XMM22,%XMM25

    (93) 0x40e7f8 VFMADD132SD	%XMM14,%XMM10,%XMM2

    (93) 0x40e7fd VFMADD231SD	%XMM8,%XMM17,%XMM7

    (93) 0x40e803 VMOVAPD	%XMM17,%XMM0

    (93) 0x40e809 ADD	%R15,%RCX

    (93) 0x40e80c ADD	%R14,%RDI

    (93) 0x40e80f VFMADD213SD	(%RDI),%XMM8,%XMM0

    (93) 0x40e814 VMULSD	%XMM25,%XMM2,%XMM1

    (93) 0x40e81a VMOVSD	%XMM0,(%RDI)

    (93) 0x40e81e VFNMADD213SD	(%RCX),%XMM1,%XMM3

    (93) 0x40e823 VFNMADD213SD	0x8(%RCX),%XMM1,%XMM6

    (93) 0x40e829 VMOVSD	%XMM3,(%RCX)

    (93) 0x40e82d VFNMADD213SD	0x10(%RCX),%XMM30,%XMM1

    (93) 0x40e834 VMOVSD	%XMM6,0x8(%RCX)

    (93) 0x40e839 VMOVSD	%XMM1,0x10(%RCX)

    (93) 0x40e83e XCHG	%AX,%AX

    (93) 0x40e840 INC	%EDX

    (93) 0x40e842 ADD	$0x18,%RAX

    (93) 0x40e846 CMP	%EBX,%EDX

    (93) 0x40e848 JGE	40ea1e

    (93) 0x40e84e XCHG	%AX,%AX

      (94) 0x40e850 VMOVSD	(%R13),%XMM3

      (94) 0x40e856 VSUBSD	(%RAX),%XMM3,%XMM6

      (94) 0x40e85a VMOVAPD	%XMM6,%XMM0

      (94) 0x40e85e VMOVSD	0x8(%R13),%XMM2

      (94) 0x40e864 VFMADD132SD	%XMM6,%XMM4,%XMM0

      (94) 0x40e869 VSUBSD	0x8(%RAX),%XMM2,%XMM1

      (94) 0x40e86e VMOVSD	0x10(%R13),%XMM3

      (94) 0x40e874 VSUBSD	0x10(%RAX),%XMM3,%XMM2

      (94) 0x40e879 VFMADD231SD	%XMM1,%XMM1,%XMM0

      (94) 0x40e87e VFMADD231SD	%XMM2,%XMM2,%XMM0

      (94) 0x40e883 VCOMISD	%XMM0,%XMM5

      (94) 0x40e887 JB	40e930

      (94) 0x40e88d VCOMISD	%XMM4,%XMM0

      (94) 0x40e891 JBE	40e930

      (94) 0x40e897 VDIVSD	%XMM0,%XMM9,%XMM0

      (94) 0x40e89b VMULSD	%XMM0,%XMM0,%XMM26

      (94) 0x40e8a1 VMULSD	%XMM0,%XMM26,%XMM27

      (94) 0x40e8a7 VMULSD	%XMM12,%XMM27,%XMM28

      (94) 0x40e8ad VSUBSD	%XMM9,%XMM28,%XMM29

      (94) 0x40e8b3 VFMSUB132SD	%XMM28,%XMM11,%XMM29

      (94) 0x40e8b9 MOV	0x30(%R12),%RDI

      (94) 0x40e8be MOV	0x28(%R12),%RCX

      (94) 0x40e8c3 VMULSD	%XMM15,%XMM13,%XMM31

      (94) 0x40e8c9 VMULSD	%XMM28,%XMM31,%XMM16

      (94) 0x40e8cf VFMADD132SD	%XMM14,%XMM10,%XMM28

      (94) 0x40e8d5 VMULSD	%XMM0,%XMM16,%XMM21

      (94) 0x40e8db VFMADD231SD	%XMM8,%XMM29,%XMM7

      (94) 0x40e8e1 VMOVAPD	%XMM29,%XMM30

      (94) 0x40e8e7 ADD	%R15,%RCX

      (94) 0x40e8ea ADD	%R14,%RDI

      (94) 0x40e8ed VMULSD	%XMM21,%XMM28,%XMM17

      (94) 0x40e8f3 VFMADD213SD	(%RDI),%XMM8,%XMM30

      (94) 0x40e8f9 VMOVSD	%XMM30,(%RDI)

      (94) 0x40e8ff VFNMADD213SD	(%RCX),%XMM17,%XMM6

      (94) 0x40e905 VFNMADD213SD	0x8(%RCX),%XMM17,%XMM1

      (94) 0x40e90c VFNMADD213SD	0x10(%RCX),%XMM17,%XMM2

      (94) 0x40e913 VMOVSD	%XMM6,(%RCX)

      (94) 0x40e917 VMOVSD	%XMM1,0x8(%RCX)

      (94) 0x40e91c VMOVSD	%XMM2,0x10(%RCX)

      (94) 0x40e921 NOPW	%CS:(%RAX,%RAX,1)

      (94) 0x40e92c NOPL	(%RAX)

      (94) 0x40e930 VMOVSD	(%R13),%XMM6

      (94) 0x40e936 VSUBSD	0x18(%RAX),%XMM6,%XMM2

      (94) 0x40e93b VMOVAPD	%XMM2,%XMM0

      (94) 0x40e93f VMOVSD	0x8(%R13),%XMM1

      (94) 0x40e945 VFMADD132SD	%XMM2,%XMM4,%XMM0

      (94) 0x40e94a VSUBSD	0x20(%RAX),%XMM1,%XMM6

      (94) 0x40e94f VMOVSD	0x10(%R13),%XMM3

      (94) 0x40e955 VSUBSD	0x28(%RAX),%XMM3,%XMM1

      (94) 0x40e95a INC	%EDX

      (94) 0x40e95c LEA	0x18(%RAX),%RDI

      (94) 0x40e960 VFMADD231SD	%XMM6,%XMM6,%XMM0

      (94) 0x40e965 VFMADD231SD	%XMM1,%XMM1,%XMM0

      (94) 0x40e96a VCOMISD	%XMM0,%XMM5

      (94) 0x40e96e JB	40ea10

      (94) 0x40e974 VCOMISD	%XMM4,%XMM0

      (94) 0x40e978 JBE	40ea10

      (94) 0x40e97e VDIVSD	%XMM0,%XMM9,%XMM0

      (94) 0x40e982 VMULSD	%XMM0,%XMM0,%XMM18

      (94) 0x40e988 VMULSD	%XMM0,%XMM18,%XMM22

      (94) 0x40e98e VMULSD	%XMM12,%XMM22,%XMM25

      (94) 0x40e994 VSUBSD	%XMM9,%XMM25,%XMM26

      (94) 0x40e99a VFMSUB132SD	%XMM25,%XMM11,%XMM26

      (94) 0x40e9a0 MOV	0x30(%R12),%RAX

      (94) 0x40e9a5 MOV	0x28(%R12),%RCX

      (94) 0x40e9aa VMULSD	%XMM15,%XMM13,%XMM28

      (94) 0x40e9b0 VMULSD	%XMM25,%XMM28,%XMM29

      (94) 0x40e9b6 VFMADD132SD	%XMM14,%XMM10,%XMM25

      (94) 0x40e9bc VMULSD	%XMM0,%XMM29,%XMM30

      (94) 0x40e9c2 VFMADD231SD	%XMM8,%XMM26,%XMM7

      (94) 0x40e9c8 VMOVAPD	%XMM26,%XMM27

      (94) 0x40e9ce ADD	%R15,%RCX

      (94) 0x40e9d1 ADD	%R14,%RAX

      (94) 0x40e9d4 VMULSD	%XMM30,%XMM25,%XMM31

      (94) 0x40e9da VFMADD213SD	(%RAX),%XMM8,%XMM27

      (94) 0x40e9e0 VMOVSD	%XMM27,(%RAX)

      (94) 0x40e9e6 VFNMADD213SD	(%RCX),%XMM31,%XMM2

      (94) 0x40e9ec VFNMADD213SD	0x8(%RCX),%XMM31,%XMM6

      (94) 0x40e9f3 VFNMADD213SD	0x10(%RCX),%XMM31,%XMM1

      (94) 0x40e9fa VMOVSD	%XMM2,(%RCX)

      (94) 0x40e9fe VMOVSD	%XMM6,0x8(%RCX)

      (94) 0x40ea03 VMOVSD	%XMM1,0x10(%RCX)

      (94) 0x40ea08 NOPL	(%RAX,%RAX,1)

      (94) 0x40ea10 INC	%EDX

      (94) 0x40ea12 LEA	0x18(%RDI),%RAX

      (94) 0x40ea16 CMP	%EBX,%EDX

      (94) 0x40ea18 JL	40e850

    (93) 0x40ea1e INC	%ESI

    (93) 0x40ea20 ADD	$0x8,%R14

    (93) 0x40ea24 CMP	%ESI,%R9D

    (93) 0x40ea27 JG	40e650

  (91) 0x40ea2d MOV	%R11,%R10

  (91) 0x40ea30 VMOVQ	%XMM19,%R14

  (91) 0x40ea36 ADD	$0x4,%R10

  (91) 0x40ea3a CMP	%R14,%R10

  (91) 0x40ea3d JNE	40e4d2

(92) 0x40ea43 JMP	40e5f3

0x40ea48 MOV	-0x50(%RBP),%RBX

0x40ea4c MOV	0x28(%RBX),%RDX

0x40ea50 LEA	0x28(%RBX),%R13

(90) 0x40ea54 VMOVQ	%RDX,%XMM4

(90) 0x40ea59 MOV	%RDX,%RAX

(90) 0x40ea5c VADDSD	%XMM4,%XMM7,%XMM2

(90) 0x40ea60 VMOVQ	%XMM2,%RCX

(90) 0x40ea65 LOCK CMPXCHG	%RCX,(%R13)

(90) 0x40ea6b MOV	%RDX,%R8

(90) 0x40ea6e MOV	%RAX,%RDX

(90) 0x40ea71 CMP	%RAX,%R8

(90) 0x40ea74 JNE	40ea54

0x40ea76 ADD	$0x38,%RSP

0x40ea7a POP	%RBX

0x40ea7b POP	%R12

0x40ea7d POP	%R13

0x40ea7f POP	%R14

0x40ea81 POP	%R15

0x40ea83 POP	%RBP

0x40ea84 RET

0x40ea85 INC	%EAX

0x40ea87 XOR	%EDX,%EDX

0x40ea89 IMUL	%EAX,%ECX

0x40ea8c ADD	%ECX,%EDX

0x40ea8e LEA	(%RAX,%RDX,1),%R11D

0x40ea92 CMP	%R11D,%EDX

0x40ea95 JL	40e401

0x40ea9b VXORPD	%XMM7,%XMM7,%XMM7

0x40ea9f JMP	40ea4c

0x40eaa1 INC	%RSI

0x40eaa4 ADD	$0x40,%R9D

0x40eaa8 CMP	%ESI,%R11D

0x40eaab JLE	40ea9b

0x40eaad TEST	%EDI,%EDI

0x40eaaf JE	40eb4c

0x40eab5 CMP	$0x1,%EDI

0x40eab8 JE	40eb33

0x40eaba CMP	$0x2,%EDI

0x40eabd JE	40eb23

0x40eabf CMP	$0x3,%EDI

0x40eac2 JE	40eb13

0x40eac4 CMP	$0x4,%EDI

0x40eac7 JE	40eb03

0x40eac9 CMP	$0x5,%EDI

0x40eacc JE	40eaf3

0x40eace CMP	$0x6,%EDI

0x40ead1 JE	40eae3

0x40ead3 TEST	%R8D,%R8D

0x40ead6 JG	40e444

0x40eadc INC	%RSI

0x40eadf ADD	$0x40,%R9D

0x40eae3 TEST	%R8D,%R8D

0x40eae6 JG	40e444

0x40eaec INC	%RSI

0x40eaef ADD	$0x40,%R9D

0x40eaf3 TEST	%R8D,%R8D

0x40eaf6 JG	40e444

0x40eafc INC	%RSI

0x40eaff ADD	$0x40,%R9D

0x40eb03 TEST	%R8D,%R8D

0x40eb06 JG	40e444

0x40eb0c INC	%RSI

0x40eb0f ADD	$0x40,%R9D

0x40eb13 TEST	%R8D,%R8D

0x40eb16 JG	40e444

0x40eb1c INC	%RSI

0x40eb1f ADD	$0x40,%R9D

0x40eb23 TEST	%R8D,%R8D

0x40eb26 JG	40e444

0x40eb2c INC	%RSI

0x40eb2f ADD	$0x40,%R9D

0x40eb33 TEST	%R8D,%R8D

0x40eb36 JG	40e444

0x40eb3c INC	%RSI

0x40eb3f ADD	$0x40,%R9D

0x40eb43 CMP	%ESI,%R11D

0x40eb46 JLE	40ea9b

(96) 0x40eb4c TEST	%R8D,%R8D

(96) 0x40eb4f JG	40e444

(96) 0x40eb55 ADD	$0x8,%RSI

(96) 0x40eb59 ADD	$0x200,%R9D

(96) 0x40eb60 CMP	%ESI,%R11D

(96) 0x40eb63 JG	40eb4c

0x40eb65 JMP	40ea9b

0x40eb6a NOPW	(%RAX,%RAX,1)

0x40eb70 MOV	$0x414eb0,%ECX

0x40eb75 MOV	$0xb6,%EDX

0x40eb7a MOV	$0x414378,%ESI

0x40eb7f MOV	$0x41337b,%EDI

0x40eb84 CALL	4030a0 <__assert_fail@plt>

0x40eb89 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○99.07	gomp_thread_start	team.c:130	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	ljForce.c:172-216
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172-191,197-216.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.38 to 6.67 cycles (2.46x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 16.38 to 1.13 cycles (14.55x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:182
omp_get_num_threads@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173
omp_get_thread_num@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 124 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	130
nb uops	131
loop length	482
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.38 cycles
front end	16.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	14.33	14.33	14.33	14.33	14.33	14.33	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	14.33	14.33	14.33	14.33	14.33	14.33	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	16.38
Dispatch	14.33
DIV/SQRT	6.00
Overall L1	16.38

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	20%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	6%
load	6%
store	10%
mul	6%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	15%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	8%
load	11%
store	10%
mul	6%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.38 cycles. At this rate:

2% of peak load performance is reached (7.57 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.22 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.38 to 14.33 cycles (1.14x speedup).

ASM code

In the binary file, the address of the function is: 40e3b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 4032e0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403290 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0xc(%R12),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40ea85 <ljForce._omp_fn.1+0x6d5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40ea9b <ljForce._omp_fn.1+0x6eb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x30(%RBX),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVSXD %EDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x78(%R12),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x20(%RBX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x18(%RBX),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%RBX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOT %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x8(%RBX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R11D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%R9D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
MOVSXD %R8D,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x2,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40eaa1 <ljForce._omp_fn.1+0x6f1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV (%R15,%RSI,4),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x80(%R12),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R10,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSD 0x6a61(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x6a61(%RIP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x6a61(%RIP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x6a61(%RIP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R9D,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RBX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVD %R14D,%XMM23	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5	1	scal (6.3%)
MOV -0x50(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x28(%RBX),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40e401 <ljForce._omp_fn.1+0x51>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 40ea4c <ljForce._omp_fn.1+0x69c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %ESI,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40ea9b <ljForce._omp_fn.1+0x6eb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
TEST %EDI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40eb4c <ljForce._omp_fn.1+0x79c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40eb33 <ljForce._omp_fn.1+0x783>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x2,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40eb23 <ljForce._omp_fn.1+0x773>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x3,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40eb13 <ljForce._omp_fn.1+0x763>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x4,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40eb03 <ljForce._omp_fn.1+0x753>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x5,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40eaf3 <ljForce._omp_fn.1+0x743>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x6,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40eae3 <ljForce._omp_fn.1+0x733>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e444 <ljForce._omp_fn.1+0x94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e444 <ljForce._omp_fn.1+0x94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e444 <ljForce._omp_fn.1+0x94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e444 <ljForce._omp_fn.1+0x94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e444 <ljForce._omp_fn.1+0x94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e444 <ljForce._omp_fn.1+0x94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e444 <ljForce._omp_fn.1+0x94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %ESI,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 40ea9b <ljForce._omp_fn.1+0x6eb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
JMP 40ea9b <ljForce._omp_fn.1+0x6eb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV $0x414eb0,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xb6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x414378,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x41337b,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4030a0 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	ljForce.c:172-216
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.38 to 6.67 cycles (2.46x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:182
omp_get_num_threads@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173
omp_get_thread_num@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 124 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	130
nb uops	131
loop length	482
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.38 cycles
front end	16.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	14.33	14.33	14.33	14.33	14.33	14.33	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	14.33	14.33	14.33	14.33	14.33	14.33	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	16.38
Dispatch	14.33
DIV/SQRT	6.00
Overall L1	16.38

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	20%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	6%
load	6%
store	10%
mul	6%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	15%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	8%
load	11%
store	10%
mul	6%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.38 cycles. At this rate:

2% of peak load performance is reached (7.57 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.22 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40e3b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 4032e0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403290 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0xc(%R12),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40ea85 <ljForce._omp_fn.1+0x6d5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40ea9b <ljForce._omp_fn.1+0x6eb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x30(%RBX),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVSXD %EDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x78(%R12),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x20(%RBX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x18(%RBX),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%RBX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOT %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x8(%RBX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R11D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%R9D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
MOVSXD %R8D,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x2,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40eaa1 <ljForce._omp_fn.1+0x6f1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV (%R15,%RSI,4),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x80(%R12),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R10,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSD 0x6a61(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x6a61(%RIP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x6a61(%RIP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x6a61(%RIP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R9D,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RBX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVD %R14D,%XMM23	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5	1	scal (6.3%)
MOV -0x50(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x28(%RBX),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40e401 <ljForce._omp_fn.1+0x51>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 40ea4c <ljForce._omp_fn.1+0x69c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %ESI,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40ea9b <ljForce._omp_fn.1+0x6eb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
TEST %EDI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40eb4c <ljForce._omp_fn.1+0x79c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40eb33 <ljForce._omp_fn.1+0x783>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x2,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40eb23 <ljForce._omp_fn.1+0x773>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x3,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40eb13 <ljForce._omp_fn.1+0x763>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x4,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40eb03 <ljForce._omp_fn.1+0x753>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x5,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40eaf3 <ljForce._omp_fn.1+0x743>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
CMP $0x6,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40eae3 <ljForce._omp_fn.1+0x733>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e444 <ljForce._omp_fn.1+0x94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e444 <ljForce._omp_fn.1+0x94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e444 <ljForce._omp_fn.1+0x94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e444 <ljForce._omp_fn.1+0x94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e444 <ljForce._omp_fn.1+0x94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e444 <ljForce._omp_fn.1+0x94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40e444 <ljForce._omp_fn.1+0x94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %ESI,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 40ea9b <ljForce._omp_fn.1+0x6eb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
JMP 40ea9b <ljForce._omp_fn.1+0x6eb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV $0x414eb0,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xb6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x414378,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x41337b,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4030a0 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

Name	Coverage (%)	Time (s)
▼ljForce._omp_fn.1–	66.07	4.54
▼Loop 92 - ljForce.c:175-216 - exec–	0.02	0.01
▼Loop 91 - ljForce.c:178-216 - exec–	0.28	0.01
▼Loop 93 - ljForce.c:187-216 - exec–	10.19	0.43
○Loop 94 - ljForce.c:191-216 - exec	55.58	2.35
○Loop 95 - ljForce.c:187-191 - exec	0.00	0.00
○Loop 90 - ljForce.c:172-172 - exec	0.00	0.00
○Loop 96 - ljForce.c:178-178 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code