OV - exec - Function advancePosition.extracted

	Function: advancePosition.extracted	Module: exec	Source: timestep.c:85-96	Coverage (incl. loops): 0.63% \| (excl. loops): 0.03%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 85 - 96

--------------------------------------------------------------------------------

85:    #pragma omp parallel for

86:    for (int iBox=0; iBox<nBoxes; iBox++)

87:    {

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

94:          s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass;

95:       }

96:    }

0x40f4f0 PUSH	%RBP

0x40f4f1 MOV	%RSP,%RBP

0x40f4f4 PUSH	%R15

0x40f4f6 PUSH	%R14

0x40f4f8 PUSH	%R13

0x40f4fa PUSH	%R12

0x40f4fc PUSH	%RBX

0x40f4fd SUB	$0x48,%RSP

0x40f501 MOVL	$0,-0x4c(%RBP)

0x40f508 MOV	%RCX,%R15

0x40f50b MOV	%RDX,-0x58(%RBP)

0x40f50f MOV	(%RDI),%ESI

0x40f511 MOVL	$0,-0x30(%RBP)

0x40f518 MOV	%R9D,-0x2c(%RBP)

0x40f51c MOVL	$0x1,-0x48(%RBP)

0x40f523 SUB	$0x8,%RSP

0x40f527 LEA	-0x48(%RBP),%RAX

0x40f52b LEA	-0x4c(%RBP),%RCX

0x40f52f LEA	-0x30(%RBP),%R8

0x40f533 LEA	-0x2c(%RBP),%R9

0x40f537 MOV	$0x42c950,%EDI

0x40f53c MOV	%ESI,-0x44(%RBP)

0x40f53f MOV	$0x22,%EDX

0x40f544 PUSH	$0x1

0x40f546 PUSH	$0x1

0x40f548 PUSH	%RAX

0x40f549 CALL	403250 <__kmpc_for_static_init_4@plt>

0x40f54e ADD	$0x20,%RSP

0x40f552 MOV	-0x2c(%RBP),%EAX

0x40f555 MOV	-0x30(%RBP),%EBX

0x40f558 MOV	%RAX,-0x40(%RBP)

0x40f55c CMP	%EBX,%EAX

0x40f55e JAE	40f57e

0x40f560 MOV	-0x44(%RBP),%ESI

0x40f563 MOV	$0x42c970,%EDI

0x40f568 ADD	$0x48,%RSP

0x40f56c POP	%RBX

0x40f56d POP	%R12

0x40f56f POP	%R13

0x40f571 POP	%R14

0x40f573 POP	%R15

0x40f575 POP	%RBP

0x40f576 VZEROUPPER

0x40f579 JMP	403320

0x40f57e MOV	-0x58(%RBP),%RAX

0x40f582 VPMOVSXBD	0x13c94(%RIP),%ZMM2

0x40f58c VPMOVSXBD	0x12ffb(%RIP),%YMM3

0x40f595 VPMOVSXBQ	0x11111(%RIP),%ZMM5

0x40f59f VPMOVSXBQ	0x1110f(%RIP),%ZMM6

0x40f5a9 VPMOVSXBQ	0x1110d(%RIP),%ZMM7

0x40f5b3 VPMOVSXBQ	0x1110b(%RIP),%ZMM8

0x40f5bd VPMOVSXBQ	0x11109(%RIP),%ZMM9

0x40f5c7 VPMOVSXBQ	0x11107(%RIP),%ZMM10

0x40f5d1 VMOVDQU64	0x134e5(%RIP),%ZMM11

0x40f5db VPMOVSXBQ	0x110fb(%RIP),%ZMM12

0x40f5e5 VPMOVSXBQ	0x110f9(%RIP),%ZMM13

0x40f5ef VPMOVSXBQ	0x110f7(%RIP),%ZMM14

0x40f5f9 VPMOVSXBQ	0x110f5(%RIP),%ZMM15

0x40f603 VPMOVSXBQ	0x110f3(%RIP),%ZMM16

0x40f60d VPMOVSXBQ	0x110f1(%RIP),%ZMM17

0x40f617 VMOVQ	%R15,%XMM0

0x40f61c MOV	%EBX,%ESI

0x40f61e SAL	$0x6,%ESI

0x40f621 XOR	%EDI,%EDI

0x40f623 VPXOR	%XMM4,%XMM4,%XMM4

0x40f627 VPBROADCASTQ	%XMM0,%ZMM1

0x40f62d MOV	0x18(%RAX),%RAX

0x40f631 MOV	0x78(%RAX),%RAX

0x40f635 MOV	%RAX,-0x68(%RBP)

0x40f639 MOV	-0x40(%RBP),%RAX

0x40f63d SUB	%EBX,%EAX

0x40f63f MOV	%RAX,-0x40(%RBP)

0x40f643 MOV	%RBX,-0x38(%RBP)

0x40f647 JMP	40f904

(107) 0x40f64c VPBROADCASTD	%XMM19,%ZMM19

(107) 0x40f652 MOV	%R14D,%ECX

(107) 0x40f655 LEA	(%R10,%RCX,1),%RAX

(107) 0x40f659 VPBROADCASTD	%XMM18,%ZMM18

(107) 0x40f65f VXORPD	%XMM22,%XMM22,%XMM22

(107) 0x40f665 VXORPD	%XMM24,%XMM24,%XMM24

(107) 0x40f66b VXORPD	%XMM25,%XMM25,%XMM25

(107) 0x40f671 VXORPD	%XMM26,%XMM26,%XMM26

(107) 0x40f677 VXORPD	%XMM27,%XMM27,%XMM27

(107) 0x40f67d VXORPD	%XMM28,%XMM28,%XMM28

(107) 0x40f683 LEA	(%RCX,%RCX,2),%RCX

(107) 0x40f687 VPCMPNLEUD	%ZMM2,%ZMM19,%K1

(107) 0x40f68e VPCMPNLEUD	%YMM2,%YMM19,%K3

(107) 0x40f695 VPCMPNLEUD	%YMM3,%YMM19,%K2

(107) 0x40f69c VPADDD	%ZMM2,%ZMM18,%ZMM18

(107) 0x40f6a2 VMOVDQU32	(%R15,%RAX,4),%ZMM20{%K1}{z}

(107) 0x40f6a9 KMOVQ	%K3,%K4

(107) 0x40f6ae LEA	(%R10,%R10,2),%RAX

(107) 0x40f6b2 LEA	(%R8,%RAX,8),%RAX

(107) 0x40f6b6 LEA	0x1c0(%RAX,%RCX,8),%RAX

(107) 0x40f6be VEXTRACTI64X4	$0x1,%ZMM20,%YMM21

(107) 0x40f6c5 VPMOVSXDQ	%YMM20,%ZMM20

(107) 0x40f6cb VPMOVSXDQ	%YMM21,%ZMM21

(107) 0x40f6d1 VPADDQ	%ZMM20,%ZMM20,%ZMM19

(107) 0x40f6d7 VPXORD	%XMM20,%XMM20,%XMM20

(107) 0x40f6dd VGATHERQPD	0x8(%R11,%ZMM19,8),%ZMM20{%K4}

(107) 0x40f6e5 VPADDQ	%ZMM21,%ZMM21,%ZMM19

(107) 0x40f6eb KMOVQ	%K2,%K4

(107) 0x40f6f0 VGATHERQPD	0x8(%R11,%ZMM19,8),%ZMM22{%K4}

(107) 0x40f6f8 VEXTRACTI64X4	$0x1,%ZMM18,%YMM19

(107) 0x40f6ff VPMOVZXDQ	%YMM18,%ZMM18

(107) 0x40f705 KMOVQ	%K3,%K4

(107) 0x40f70a VPMOVZXDQ	%YMM19,%ZMM19

(107) 0x40f710 VDIVPD	%ZMM20,%ZMM1,%ZMM21

(107) 0x40f716 VDIVPD	%ZMM22,%ZMM1,%ZMM20

(107) 0x40f71c VPBROADCASTQ	%R10,%ZMM22

(107) 0x40f722 VPADDQ	%ZMM18,%ZMM22,%ZMM18

(107) 0x40f728 VPADDQ	%ZMM19,%ZMM22,%ZMM19

(107) 0x40f72e VPADDQ	%ZMM18,%ZMM18,%ZMM22

(107) 0x40f734 VPADDQ	%ZMM19,%ZMM19,%ZMM23

(107) 0x40f73a VPADDQ	%ZMM18,%ZMM22,%ZMM22

(107) 0x40f740 VPXORD	%XMM18,%XMM18,%XMM18

(107) 0x40f746 VPADDQ	%ZMM19,%ZMM23,%ZMM23

(107) 0x40f74c VPXORD	%XMM19,%XMM19,%XMM19

(107) 0x40f752 VGATHERQPD	(%R9,%ZMM22,8),%ZMM24{%K4}

(107) 0x40f759 KMOVQ	%K3,%K4

(107) 0x40f75e VGATHERQPD	(%R8,%ZMM22,8),%ZMM18{%K4}

(107) 0x40f765 KMOVQ	%K3,%K4

(107) 0x40f76a VGATHERQPD	0x8(%R9,%ZMM22,8),%ZMM25{%K4}

(107) 0x40f772 KMOVQ	%K3,%K4

(107) 0x40f777 VGATHERQPD	0x8(%R8,%ZMM22,8),%ZMM26{%K4}

(107) 0x40f77f KMOVQ	%K2,%K4

(107) 0x40f784 VGATHERQPD	(%R9,%ZMM23,8),%ZMM27{%K4}

(107) 0x40f78b KMOVQ	%K2,%K4

(107) 0x40f790 VGATHERQPD	(%R8,%ZMM23,8),%ZMM19{%K4}

(107) 0x40f797 KMOVQ	%K2,%K4

(107) 0x40f79c VGATHERQPD	0x8(%R9,%ZMM23,8),%ZMM28{%K4}

(107) 0x40f7a4 KMOVQ	%K2,%K4

(107) 0x40f7a9 VFMADD231PD	%ZMM24,%ZMM21,%ZMM18

(107) 0x40f7af VXORPD	%XMM24,%XMM24,%XMM24

(107) 0x40f7b5 VGATHERQPD	0x8(%R8,%ZMM23,8),%ZMM24{%K4}

(107) 0x40f7bd KMOVQ	%K3,%K4

(107) 0x40f7c2 VFMADD231PD	%ZMM25,%ZMM21,%ZMM26

(107) 0x40f7c8 VXORPD	%XMM25,%XMM25,%XMM25

(107) 0x40f7ce VGATHERQPD	0x10(%R9,%ZMM22,8),%ZMM25{%K4}

(107) 0x40f7d6 KMOVQ	%K2,%K4

(107) 0x40f7db VFMADD231PD	%ZMM27,%ZMM20,%ZMM19

(107) 0x40f7e1 VXORPD	%XMM27,%XMM27,%XMM27

(107) 0x40f7e7 VGATHERQPD	0x10(%R9,%ZMM23,8),%ZMM27{%K4}

(107) 0x40f7ef VFMADD231PD	%ZMM28,%ZMM20,%ZMM24

(107) 0x40f7f5 VXORPD	%XMM28,%XMM28,%XMM28

(107) 0x40f7fb VGATHERQPD	0x10(%R8,%ZMM22,8),%ZMM28{%K3}

(107) 0x40f803 VXORPD	%XMM22,%XMM22,%XMM22

(107) 0x40f809 VGATHERQPD	0x10(%R8,%ZMM23,8),%ZMM22{%K2}

(107) 0x40f811 VMOVAPD	%ZMM26,%ZMM23

(107) 0x40f817 VPERMT2PD	%ZMM18,%ZMM5,%ZMM23

(107) 0x40f81d VMOVAPD	%ZMM24,%ZMM29

(107) 0x40f823 VPERMT2PD	%ZMM19,%ZMM5,%ZMM29

(107) 0x40f829 VFMADD231PD	%ZMM25,%ZMM21,%ZMM28

(107) 0x40f82f VMOVAPD	%ZMM18,%ZMM21

(107) 0x40f835 VPERMT2PD	%ZMM26,%ZMM6,%ZMM21

(107) 0x40f83b VPERMT2PD	%ZMM26,%ZMM7,%ZMM18

(107) 0x40f841 VMOVAPD	%ZMM19,%ZMM26

(107) 0x40f847 VPERMT2PD	%ZMM24,%ZMM6,%ZMM26

(107) 0x40f84d VPERMT2PD	%ZMM24,%ZMM7,%ZMM19

(107) 0x40f853 VFMADD231PD	%ZMM27,%ZMM20,%ZMM22

(107) 0x40f859 VPMOVM2B	%K1,%ZMM20

(107) 0x40f85f VPERMT2B	%ZMM4,%ZMM11,%ZMM20

(107) 0x40f865 VPERMT2PD	%ZMM22,%ZMM10,%ZMM29

(107) 0x40f86b VPERMT2PD	%ZMM28,%ZMM10,%ZMM23

(107) 0x40f871 VPERMT2PD	%ZMM22,%ZMM8,%ZMM19

(107) 0x40f877 VPERMT2PD	%ZMM22,%ZMM9,%ZMM26

(107) 0x40f87d VPMOVB2M	%ZMM20,%K1

(107) 0x40f883 VPERMT2PD	%ZMM28,%ZMM8,%ZMM18

(107) 0x40f889 VPERMT2PD	%ZMM28,%ZMM9,%ZMM21

(107) 0x40f88f KSHIFTRQ	$0x30,%K1,%K2

(107) 0x40f895 KSHIFTRQ	$0x28,%K1,%K3

(107) 0x40f89b KSHIFTRQ	$0x20,%K1,%K4

(107) 0x40f8a1 VMOVUPD	%ZMM0,(%RAX){%K2}

(107) 0x40f8a7 VMOVUPD	%ZMM0,-0x40(%RAX){%K2}

(107) 0x40f8ae KSHIFTRQ	$0x18,%K1,%K2

(107) 0x40f8b4 VMOVUPD	%ZMM29,-0x80(%RAX){%K3}

(107) 0x40f8bb VMOVUPD	%ZMM26,-0xc0(%RAX){%K4}

(107) 0x40f8c2 VMOVUPD	%ZMM19,-0x100(%RAX){%K2}

(107) 0x40f8c9 KSHIFTRQ	$0x10,%K1,%K2

(107) 0x40f8cf VMOVUPD	%ZMM23,-0x140(%RAX){%K2}

(107) 0x40f8d6 KSHIFTRQ	$0x8,%K1,%K2

(107) 0x40f8dc VMOVUPD	%ZMM21,-0x180(%RAX){%K2}

(107) 0x40f8e3 VMOVUPD	%ZMM18,-0x1c0(%RAX){%K1}

(107) 0x40f8ea NOPW	(%RAX,%RAX,1)

(107) 0x40f8f0 ADD	$0x40,%ESI

(107) 0x40f8f3 LEA	0x1(%RDI),%RAX

(107) 0x40f8f7 CMP	-0x40(%RBP),%RDI

(107) 0x40f8fb MOV	%RAX,%RDI

(107) 0x40f8fe JE	40f560

(107) 0x40f904 MOV	-0x68(%RBP),%RCX

(107) 0x40f908 LEA	(%RDI,%RBX,1),%RAX

(107) 0x40f90c MOVSXD	(%RCX,%RAX,4),%R12

(107) 0x40f910 TEST	%R12,%R12

(107) 0x40f913 JLE	40f8f0

(107) 0x40f915 MOV	-0x58(%RBP),%RDX

(107) 0x40f919 LEA	(%RDI,%RBX,1),%R10D

(107) 0x40f91d MOV	%ESI,%R13D

(107) 0x40f920 LEA	(,%R13,8),%RAX

(107) 0x40f928 SAL	$0x2,%R13

(107) 0x40f92c SAL	$0x6,%R10D

(107) 0x40f930 MOV	0x20(%RDX),%RCX

(107) 0x40f934 MOV	0x28(%RDX),%R11

(107) 0x40f938 LEA	(,%R10,8),%RDX

(107) 0x40f940 LEA	(%RDX,%RDX,2),%RDX

(107) 0x40f944 MOV	0x20(%RCX),%R9

(107) 0x40f948 MOV	0x18(%RCX),%R8

(107) 0x40f94c MOV	0x10(%RCX),%R15

(107) 0x40f950 LEA	(%R12,%R10,1),%RCX

(107) 0x40f954 LEA	(%RCX,%RCX,2),%RCX

(107) 0x40f958 LEA	-0x8(%R9,%RCX,8),%RBX

(107) 0x40f95d LEA	(%R8,%RDX,1),%R14

(107) 0x40f961 CMP	%R14,%RBX

(107) 0x40f964 JB	40fa00

(107) 0x40f96a LEA	-0x8(%R8,%RCX,8),%RCX

(107) 0x40f96f ADD	%R9,%RDX

(107) 0x40f972 CMP	%RDX,%RCX

(107) 0x40f975 JB	40fa00

(107) 0x40f97b MOV	-0x38(%RBP),%RBX

(107) 0x40f97f LEA	0x10(%RAX,%RAX,2),%RAX

(107) 0x40f984 ADD	%R13,%R15

(107) 0x40f987 XOR	%ECX,%ECX

(107) 0x40f989 NOPL	(%RAX)

  (110) 0x40f990 MOVSXD	(%R15,%RCX,4),%RDX

  (110) 0x40f994 VMOVSD	-0x10(%R9,%RAX,1),%XMM19

  (110) 0x40f99c INC	%RCX

  (110) 0x40f99f SAL	$0x4,%RDX

  (110) 0x40f9a3 VDIVSD	0x8(%R11,%RDX,1),%XMM0,%XMM18

  (110) 0x40f9ab VFMADD213SD	-0x10(%R8,%RAX,1),%XMM18,%XMM19

  (110) 0x40f9b3 VMOVSD	%XMM19,-0x10(%R8,%RAX,1)

  (110) 0x40f9bb VMOVSD	-0x8(%R9,%RAX,1),%XMM19

  (110) 0x40f9c3 VFMADD213SD	-0x8(%R8,%RAX,1),%XMM18,%XMM19

  (110) 0x40f9cb VMOVSD	%XMM19,-0x8(%R8,%RAX,1)

  (110) 0x40f9d3 VMOVSD	(%R9,%RAX,1),%XMM19

  (110) 0x40f9da VFMADD213SD	(%R8,%RAX,1),%XMM18,%XMM19

  (110) 0x40f9e1 VMOVSD	%XMM19,(%R8,%RAX,1)

  (110) 0x40f9e8 ADD	$0x18,%RAX

  (110) 0x40f9ec CMP	%ECX,%R12D

  (110) 0x40f9ef JNE	40f990

(107) 0x40f9f1 JMP	40f8f0

0x40f9f6 NOPW	%CS:(%RAX,%RAX,1)

(107) 0x40fa00 MOV	-0x38(%RBP),%RBX

(107) 0x40fa04 LEA	(%RAX,%RAX,2),%RDX

(107) 0x40fa08 MOV	%R12D,%R14D

(107) 0x40fa0b AND	$0x7ffffff0,%R14D

(107) 0x40fa12 JE	40fc73

(107) 0x40fa18 XOR	%EAX,%EAX

(107) 0x40fa1a CMP	$0xa,%R12D

(107) 0x40fa1e JB	40fc9a

(107) 0x40fa24 LEA	(%R15,%R13,1),%RCX

(107) 0x40fa28 XOR	%EBX,%EBX

(107) 0x40fa2a MOV	%RDX,-0x60(%RBP)

(107) 0x40fa2e XCHG	%AX,%AX

  (109) 0x40fa30 VPMOVSXDQ	0x20(%RCX,%RBX,4),%ZMM19

  (109) 0x40fa38 VPMOVSXDQ	(%RCX,%RBX,4),%ZMM18

  (109) 0x40fa3f VMOVUPD	0xc0(%R9,%RDX,1),%ZMM25

  (109) 0x40fa47 VMOVUPD	0x100(%R9,%RDX,1),%ZMM20

  (109) 0x40fa4f LEA	0x140(%R8,%RDX,1),%RAX

  (109) 0x40fa57 VPCMPEQB	%XMM0,%XMM0,%K1

  (109) 0x40fa5d VXORPD	%XMM22,%XMM22,%XMM22

  (109) 0x40fa63 VMOVUPD	(%R9,%RDX,1),%ZMM21

  (109) 0x40fa6a VMOVUPD	0x40(%R9,%RDX,1),%ZMM28

  (109) 0x40fa72 VMOVUPD	0x80(%R9,%RDX,1),%ZMM31

  (109) 0x40fa7a ADD	$0x10,%RBX

  (109) 0x40fa7e VMOVUPD	-0x140(%RAX),%ZMM26

  (109) 0x40fa85 VMOVAPD	%ZMM25,%ZMM24

  (109) 0x40fa8b VMOVAPD	%ZMM25,%ZMM23

  (109) 0x40fa91 VPERMT2PD	%ZMM20,%ZMM12,%ZMM24

  (109) 0x40fa97 VPERMT2PD	%ZMM20,%ZMM14,%ZMM23

  (109) 0x40fa9d VPERMT2PD	%ZMM25,%ZMM16,%ZMM20

  (109) 0x40faa3 VXORPD	%XMM25,%XMM25,%XMM25

  (109) 0x40faa9 VMOVAPD	%ZMM21,%ZMM29

  (109) 0x40faaf VMOVAPD	%ZMM21,%ZMM30

  (109) 0x40fab5 VPERMT2PD	%ZMM28,%ZMM12,%ZMM29

  (109) 0x40fabb VPERMT2PD	%ZMM28,%ZMM14,%ZMM30

  (109) 0x40fac1 VPERMT2PD	%ZMM21,%ZMM16,%ZMM28

  (109) 0x40fac7 VMOVAPD	%ZMM26,%ZMM21

  (109) 0x40facd VPADDQ	%ZMM19,%ZMM19,%ZMM19

  (109) 0x40fad3 VPADDQ	%ZMM18,%ZMM18,%ZMM27

  (109) 0x40fad9 VMOVUPD	-0x100(%RAX),%ZMM18

  (109) 0x40fae0 VGATHERQPD	0x8(%R11,%ZMM19,8),%ZMM22{%K1}

  (109) 0x40fae8 VPCMPEQB	%XMM0,%XMM0,%K1

  (109) 0x40faee VMOVAPD	%ZMM26,%ZMM19

  (109) 0x40faf4 VGATHERQPD	0x8(%R11,%ZMM27,8),%ZMM25{%K1}

  (109) 0x40fafc VMOVUPD	-0xc0(%RAX),%ZMM27

  (109) 0x40fb03 VPERMT2PD	%ZMM31,%ZMM13,%ZMM29

  (109) 0x40fb09 VPERMT2PD	%ZMM31,%ZMM15,%ZMM30

  (109) 0x40fb0f VPERMT2PD	%ZMM31,%ZMM17,%ZMM28

  (109) 0x40fb15 VMOVUPD	-0x80(%RAX),%ZMM31

  (109) 0x40fb1c VDIVPD	%ZMM22,%ZMM1,%ZMM22

  (109) 0x40fb22 VDIVPD	%ZMM25,%ZMM1,%ZMM25

  (109) 0x40fb28 VPERMT2PD	%ZMM18,%ZMM12,%ZMM21

  (109) 0x40fb2e VPERMT2PD	%ZMM18,%ZMM14,%ZMM19

  (109) 0x40fb34 VPERMT2PD	%ZMM26,%ZMM16,%ZMM18

  (109) 0x40fb3a VPERMT2PD	%ZMM27,%ZMM13,%ZMM21

  (109) 0x40fb40 VPERMT2PD	%ZMM27,%ZMM15,%ZMM19

  (109) 0x40fb46 VPERMT2PD	%ZMM27,%ZMM17,%ZMM18

  (109) 0x40fb4c VMOVUPD	-0x40(%RAX),%ZMM27

  (109) 0x40fb53 VFMADD231PD	%ZMM29,%ZMM25,%ZMM21

  (109) 0x40fb59 VMOVUPD	0x140(%R9,%RDX,1),%ZMM29

  (109) 0x40fb61 VFMADD231PD	%ZMM30,%ZMM25,%ZMM19

  (109) 0x40fb67 VMOVUPD	(%RAX),%ZMM30

  (109) 0x40fb6d VFMADD231PD	%ZMM28,%ZMM25,%ZMM18

  (109) 0x40fb73 VMOVAPD	%ZMM31,%ZMM25

  (109) 0x40fb79 VMOVAPD	%ZMM31,%ZMM28

  (109) 0x40fb7f ADD	$0x180,%RDX

  (109) 0x40fb86 VPERMT2PD	%ZMM27,%ZMM12,%ZMM25

  (109) 0x40fb8c VPERMT2PD	%ZMM27,%ZMM14,%ZMM28

  (109) 0x40fb92 VPERMT2PD	%ZMM31,%ZMM16,%ZMM27

  (109) 0x40fb98 VPERMT2PD	%ZMM29,%ZMM13,%ZMM24

  (109) 0x40fb9e VPERMT2PD	%ZMM30,%ZMM13,%ZMM25

  (109) 0x40fba4 VPERMT2PD	%ZMM29,%ZMM15,%ZMM23

  (109) 0x40fbaa VPERMT2PD	%ZMM30,%ZMM15,%ZMM28

  (109) 0x40fbb0 VPERMT2PD	%ZMM29,%ZMM17,%ZMM20

  (109) 0x40fbb6 VPERMT2PD	%ZMM30,%ZMM17,%ZMM27

  (109) 0x40fbbc VFMADD231PD	%ZMM23,%ZMM22,%ZMM28

  (109) 0x40fbc2 VFMADD231PD	%ZMM24,%ZMM22,%ZMM25

  (109) 0x40fbc8 VMOVAPD	%ZMM21,%ZMM23

  (109) 0x40fbce VFMADD231PD	%ZMM20,%ZMM22,%ZMM27

  (109) 0x40fbd4 VMOVAPD	%ZMM21,%ZMM22

  (109) 0x40fbda VPERMT2PD	%ZMM19,%ZMM6,%ZMM23

  (109) 0x40fbe0 VPERMT2PD	%ZMM19,%ZMM7,%ZMM22

  (109) 0x40fbe6 VPERMT2PD	%ZMM21,%ZMM5,%ZMM19

  (109) 0x40fbec VMOVAPD	%ZMM25,%ZMM20

  (109) 0x40fbf2 VMOVAPD	%ZMM28,%ZMM21

  (109) 0x40fbf8 VPERMT2PD	%ZMM25,%ZMM5,%ZMM21

  (109) 0x40fbfe VPERMT2PD	%ZMM28,%ZMM7,%ZMM20

  (109) 0x40fc04 VPERMT2PD	%ZMM28,%ZMM6,%ZMM25

  (109) 0x40fc0a VPERMT2PD	%ZMM18,%ZMM10,%ZMM19

  (109) 0x40fc10 VPERMT2PD	%ZMM18,%ZMM8,%ZMM22

  (109) 0x40fc16 VPERMT2PD	%ZMM18,%ZMM9,%ZMM23

  (109) 0x40fc1c VPERMT2PD	%ZMM27,%ZMM9,%ZMM25

  (109) 0x40fc22 VPERMT2PD	%ZMM27,%ZMM10,%ZMM21

  (109) 0x40fc28 VPERMT2PD	%ZMM27,%ZMM8,%ZMM20

  (109) 0x40fc2e VMOVUPD	%ZMM23,-0x100(%RAX)

  (109) 0x40fc35 VMOVUPD	%ZMM22,-0x140(%RAX)

  (109) 0x40fc3c VMOVUPD	%ZMM19,-0xc0(%RAX)

  (109) 0x40fc43 VMOVUPD	%ZMM20,-0x80(%RAX)

  (109) 0x40fc4a VMOVUPD	%ZMM21,(%RAX)

  (109) 0x40fc50 VMOVUPD	%ZMM25,-0x40(%RAX)

  (109) 0x40fc57 CMP	%R14D,%EBX

  (109) 0x40fc5a JB	40fa30

(107) 0x40fc60 MOV	-0x38(%RBP),%RBX

(107) 0x40fc64 MOV	-0x60(%RBP),%RDX

(107) 0x40fc68 CMP	%R14D,%R12D

(107) 0x40fc6b JE	40f8f0

(107) 0x40fc71 JMP	40fc76

(107) 0x40fc73 XOR	%R14D,%R14D

(107) 0x40fc76 VMOVD	%R12D,%XMM19

(107) 0x40fc7c VMOVD	%R14D,%XMM18

(107) 0x40fc82 VPSUBD	%ZMM18,%ZMM19,%ZMM19

(107) 0x40fc88 VMOVD	%XMM19,%EAX

(107) 0x40fc8e CMP	$0xa,%EAX

(107) 0x40fc91 JAE	40f64c

(107) 0x40fc97 MOV	%R14D,%EAX

(107) 0x40fc9a MOV	%EAX,%EAX

(107) 0x40fc9c LEA	(%RAX,%RAX,2),%RCX

(107) 0x40fca0 ADD	%R13,%R15

(107) 0x40fca3 LEA	(%RDX,%RCX,8),%RCX

(107) 0x40fca7 ADD	%RCX,%R8

(107) 0x40fcaa ADD	%RCX,%R9

(107) 0x40fcad XOR	%ECX,%ECX

(107) 0x40fcaf NOP

  (108) 0x40fcb0 MOVSXD	(%R15,%RAX,4),%RDX

  (108) 0x40fcb4 VMOVSD	(%R9,%RCX,1),%XMM19

  (108) 0x40fcbb INC	%RAX

  (108) 0x40fcbe SAL	$0x4,%RDX

  (108) 0x40fcc2 VDIVSD	0x8(%R11,%RDX,1),%XMM0,%XMM18

  (108) 0x40fcca VFMADD213SD	(%R8,%RCX,1),%XMM18,%XMM19

  (108) 0x40fcd1 VMOVDDUP	%XMM18,%XMM18

  (108) 0x40fcd7 VMOVSD	%XMM19,(%R8,%RCX,1)

  (108) 0x40fcde VMOVUPD	0x8(%R9,%RCX,1),%XMM19

  (108) 0x40fce9 VFMADD213PD	0x8(%R8,%RCX,1),%XMM19,%XMM18

  (108) 0x40fcf4 VMOVUPD	%XMM18,0x8(%R8,%RCX,1)

  (108) 0x40fcff ADD	$0x18,%RCX

  (108) 0x40fd03 CMP	%EAX,%R12D

  (108) 0x40fd06 JNE	40fcb0

(107) 0x40fd08 JMP	40f8f0

0x40fd0d NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run icx_0

Source file and lines	timestep.c:85-96
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-96.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.38 to 7.50 cycles (1.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 9.38 to 5.67 cycles (1.65x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_4@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88
VPMOVSXBQ: 12 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 232 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	76
nb uops	75
loop length	361
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	15
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.38 cycles
front end	9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.17	3.17	3.17	3.17	3.17	3.17	8.50	8.50	8.50	8.50	0.00	7.50	7.50	0.00	0.00	0.00
cycles	3.17	3.17	3.17	3.17	3.17	3.17	8.50	8.50	8.50	8.50	0.00	7.50	7.50	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.38
Dispatch	8.50
Overall L1	9.38

Vectorization ratios

all	42%
load	88%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Vector efficiency ratios

all	13%
load	17%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.38 cycles. At this rate:

9% of peak load performance is reached (24.75 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.38 to 8.50 cycles (1.10x speedup).

ASM code

In the binary file, the address of the function is: 40f4f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVL $0,-0x4c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R9D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x48(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x4c(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $0x42c950,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 403250 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x30(%RBP),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
CMP %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 40f57e <advancePosition.extracted+0x8e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOV $0x42c970,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 403320 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VPMOVSXBD 0x13c94(%RIP),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (25.0%)
VPMOVSXBD 0x12ffb(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (12.5%)
VPMOVSXBQ 0x11111(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x1110f(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x1110d(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x1110b(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x11109(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x11107(%RIP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VMOVDQU64 0x134e5(%RIP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VPMOVSXBQ 0x110fb(%RIP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x110f9(%RIP),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x110f7(%RIP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x110f5(%RIP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x110f3(%RIP),%ZMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x110f1(%RIP),%ZMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VMOVQ %R15,%XMM0	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPXOR %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPBROADCASTQ %XMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x18(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x78(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
SUB %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RBX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 40f904 <advancePosition.extracted+0x414>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run icx_0

Source file and lines	timestep.c:85-96
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.38 to 7.50 cycles (1.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_4@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88
VPMOVSXBQ: 12 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 232 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	76
nb uops	75
loop length	361
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	15
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.38 cycles
front end	9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.17	3.17	3.17	3.17	3.17	3.17	8.50	8.50	8.50	8.50	0.00	7.50	7.50	0.00	0.00	0.00
cycles	3.17	3.17	3.17	3.17	3.17	3.17	8.50	8.50	8.50	8.50	0.00	7.50	7.50	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.38
Dispatch	8.50
Overall L1	9.38

Vectorization ratios

all	42%
load	88%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Vector efficiency ratios

all	13%
load	17%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.38 cycles. At this rate:

9% of peak load performance is reached (24.75 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40f4f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVL $0,-0x4c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R9D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x48(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x4c(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $0x42c950,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 403250 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x30(%RBP),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
CMP %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 40f57e <advancePosition.extracted+0x8e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOV $0x42c970,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 403320 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VPMOVSXBD 0x13c94(%RIP),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (25.0%)
VPMOVSXBD 0x12ffb(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (12.5%)
VPMOVSXBQ 0x11111(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x1110f(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x1110d(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x1110b(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x11109(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x11107(%RIP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VMOVDQU64 0x134e5(%RIP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VPMOVSXBQ 0x110fb(%RIP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x110f9(%RIP),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x110f7(%RIP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x110f5(%RIP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x110f3(%RIP),%ZMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x110f1(%RIP),%ZMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VMOVQ %R15,%XMM0	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPXOR %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPBROADCASTQ %XMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x18(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x78(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
SUB %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RBX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 40f904 <advancePosition.extracted+0x414>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

Name	Coverage (%)	Time (s)
▼advancePosition.extracted–	0.63	0.05
▼Loop 107 - timestep.c:85-96 - exec–	0.36	0.03
○Loop 109 - timestep.c:88-94 - exec	0.17	0.02
○Loop 108 - timestep.c:88-93 - exec	0.07	0.02
○Loop 110 - timestep.c:88-94 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code