OV - exec - Function advanceVelocity.extracted

	Function: advanceVelocity.extracted	Module: exec	Source: timestep.c:71-80	Coverage (incl. loops): 1.52% \| (excl. loops): 0.02%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 80

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

79:       }

80:    }

0x40f030 PUSH	%RBP

0x40f031 MOV	%RSP,%RBP

0x40f034 PUSH	%R15

0x40f036 PUSH	%R14

0x40f038 PUSH	%R13

0x40f03a PUSH	%R12

0x40f03c PUSH	%RBX

0x40f03d SUB	$0x28,%RSP

0x40f041 MOVL	$0,-0x3c(%RBP)

0x40f048 MOV	%RCX,%R15

0x40f04b MOV	%RDX,-0x48(%RBP)

0x40f04f MOV	(%RDI),%ESI

0x40f051 MOVL	$0,-0x30(%RBP)

0x40f058 MOV	%R9D,-0x2c(%RBP)

0x40f05c MOVL	$0x1,-0x38(%RBP)

0x40f063 SUB	$0x8,%RSP

0x40f067 LEA	-0x38(%RBP),%RAX

0x40f06b LEA	-0x3c(%RBP),%RCX

0x40f06f LEA	-0x30(%RBP),%R8

0x40f073 LEA	-0x2c(%RBP),%R9

0x40f077 MOV	$0x42c8f0,%EDI

0x40f07c MOV	%ESI,-0x34(%RBP)

0x40f07f MOV	$0x22,%EDX

0x40f084 PUSH	$0x1

0x40f086 PUSH	$0x1

0x40f088 PUSH	%RAX

0x40f089 CALL	403250 <__kmpc_for_static_init_4@plt>

0x40f08e ADD	$0x20,%RSP

0x40f092 MOV	-0x30(%RBP),%EAX

0x40f095 MOV	-0x2c(%RBP),%ECX

0x40f098 CMP	%EAX,%ECX

0x40f09a JAE	40f0ba

0x40f09c MOV	-0x34(%RBP),%ESI

0x40f09f MOV	$0x42c910,%EDI

0x40f0a4 ADD	$0x28,%RSP

0x40f0a8 POP	%RBX

0x40f0a9 POP	%R12

0x40f0ab POP	%R13

0x40f0ad POP	%R14

0x40f0af POP	%R15

0x40f0b1 POP	%RBP

0x40f0b2 VZEROUPPER

0x40f0b5 JMP	403320

0x40f0ba MOV	-0x48(%RBP),%RDX

0x40f0be VPMOVSXBQ	0x115e0(%RIP),%ZMM2

0x40f0c8 VPMOVSXBQ	0x115de(%RIP),%ZMM3

0x40f0d2 VPMOVSXBQ	0x115dc(%RIP),%ZMM4

0x40f0dc VPMOVSXBQ	0x115da(%RIP),%ZMM5

0x40f0e6 VPMOVSXBQ	0x115d8(%RIP),%ZMM6

0x40f0f0 VPMOVSXBQ	0x115d6(%RIP),%ZMM7

0x40f0fa VPMOVSXBQ	0x115d4(%RIP),%ZMM8

0x40f104 VMOVQ	%R15,%XMM0

0x40f109 MOV	%EAX,%ESI

0x40f10b SUB	%EAX,%ECX

0x40f10d SAL	$0x6,%ESI

0x40f110 XOR	%EDI,%EDI

0x40f112 VPBROADCASTQ	%XMM0,%ZMM1

0x40f118 MOV	0x18(%RDX),%RDX

0x40f11c MOV	0x78(%RDX),%RDX

0x40f120 MOV	%RDX,-0x50(%RBP)

0x40f124 JMP	40f143

0x40f126 NOPW	%CS:(%RAX,%RAX,1)

(102) 0x40f130 ADD	$0x40,%ESI

(102) 0x40f133 LEA	0x1(%RDI),%RDX

(102) 0x40f137 CMP	%RCX,%RDI

(102) 0x40f13a MOV	%RDX,%RDI

(102) 0x40f13d JE	40f09c

(102) 0x40f143 MOV	-0x50(%RBP),%R8

(102) 0x40f147 LEA	(%RDI,%RAX,1),%RDX

(102) 0x40f14b MOVSXD	(%R8,%RDX,4),%R8

(102) 0x40f14f TEST	%R8,%R8

(102) 0x40f152 JLE	40f130

(102) 0x40f154 MOV	-0x48(%RBP),%R9

(102) 0x40f158 LEA	(%RDI,%RAX,1),%R12D

(102) 0x40f15c MOV	%R8,%R11

(102) 0x40f15f MOV	%ESI,%EDX

(102) 0x40f161 SAL	$0x3,%RDX

(102) 0x40f165 SAL	$0x6,%R12D

(102) 0x40f169 ADD	%R12,%R11

(102) 0x40f16c LEA	(,%R12,8),%RBX

(102) 0x40f174 LEA	(%R11,%R11,2),%R11

(102) 0x40f178 LEA	(%RBX,%RBX,2),%RBX

(102) 0x40f17c MOV	0x20(%R9),%R10

(102) 0x40f180 MOV	0x20(%R10),%R9

(102) 0x40f184 MOV	0x28(%R10),%R10

(102) 0x40f188 LEA	-0x8(%R10,%R11,8),%R14

(102) 0x40f18d LEA	(%R9,%RBX,1),%R15

(102) 0x40f191 CMP	%R15,%R14

(102) 0x40f194 JB	40f200

(102) 0x40f196 LEA	-0x8(%R9,%R11,8),%R11

(102) 0x40f19b ADD	%R10,%RBX

(102) 0x40f19e CMP	%RBX,%R11

(102) 0x40f1a1 JB	40f200

(102) 0x40f1a3 LEA	0x10(%RDX,%RDX,2),%RDX

(102) 0x40f1a8 NOPL	(%RAX,%RAX,1)

  (106) 0x40f1b0 VMOVSD	-0x10(%R10,%RDX,1),%XMM9

  (106) 0x40f1b7 VFMADD213SD	-0x10(%R9,%RDX,1),%XMM0,%XMM9

  (106) 0x40f1be VMOVSD	%XMM9,-0x10(%R9,%RDX,1)

  (106) 0x40f1c5 VMOVSD	-0x8(%R10,%RDX,1),%XMM9

  (106) 0x40f1cc VFMADD213SD	-0x8(%R9,%RDX,1),%XMM0,%XMM9

  (106) 0x40f1d3 VMOVSD	%XMM9,-0x8(%R9,%RDX,1)

  (106) 0x40f1da VMOVSD	(%R10,%RDX,1),%XMM9

  (106) 0x40f1e0 VFMADD213SD	(%R9,%RDX,1),%XMM0,%XMM9

  (106) 0x40f1e6 VMOVSD	%XMM9,(%R9,%RDX,1)

  (106) 0x40f1ec ADD	$0x18,%RDX

  (106) 0x40f1f0 DEC	%R8D

  (106) 0x40f1f3 JNE	40f1b0

(102) 0x40f1f5 JMP	40f130

0x40f1fa NOPW	(%RAX,%RAX,1)

(102) 0x40f200 LEA	(%RDX,%RDX,2),%R11

(102) 0x40f204 MOV	%R8D,%R15D

(102) 0x40f207 AND	$0x7ffffff8,%R15D

(102) 0x40f20e JE	40f360

(102) 0x40f214 MOV	%R8D,%R13D

(102) 0x40f217 AND	$0x7fffffe0,%R13D

(102) 0x40f21e JE	40f368

(102) 0x40f224 XOR	%R14D,%R14D

(102) 0x40f227 MOV	%R11,%RBX

(102) 0x40f22a NOPW	(%RAX,%RAX,1)

  (105) 0x40f230 LEA	0x200(%R10,%RBX,1),%RDX

  (105) 0x40f238 ADD	$0x20,%R14D

  (105) 0x40f23c VMOVUPD	(%RDX),%ZMM9

  (105) 0x40f242 VMOVUPD	0x40(%RDX),%ZMM10

  (105) 0x40f249 VMOVUPD	0x80(%RDX),%ZMM11

  (105) 0x40f250 VMOVUPD	0xc0(%RDX),%ZMM12

  (105) 0x40f257 VMOVUPD	-0x200(%RDX),%ZMM13

  (105) 0x40f25e VMOVUPD	-0x1c0(%RDX),%ZMM14

  (105) 0x40f265 VMOVUPD	-0x180(%RDX),%ZMM15

  (105) 0x40f26c VMOVUPD	-0x140(%RDX),%ZMM16

  (105) 0x40f273 VMOVUPD	-0x100(%RDX),%ZMM17

  (105) 0x40f27a VMOVUPD	-0xc0(%RDX),%ZMM18

  (105) 0x40f281 VMOVUPD	-0x80(%RDX),%ZMM19

  (105) 0x40f288 VMOVUPD	-0x40(%RDX),%ZMM20

  (105) 0x40f28f LEA	0x1c0(%R9,%RBX,1),%RDX

  (105) 0x40f297 ADD	$0x300,%RBX

  (105) 0x40f29e VFMADD213PD	(%RDX),%ZMM1,%ZMM20

  (105) 0x40f2a4 VFMADD213PD	-0x40(%RDX),%ZMM1,%ZMM19

  (105) 0x40f2ab VFMADD213PD	-0x80(%RDX),%ZMM1,%ZMM18

  (105) 0x40f2b2 VFMADD213PD	-0xc0(%RDX),%ZMM1,%ZMM17

  (105) 0x40f2b9 VFMADD213PD	-0x100(%RDX),%ZMM1,%ZMM16

  (105) 0x40f2c0 VFMADD213PD	-0x140(%RDX),%ZMM1,%ZMM15

  (105) 0x40f2c7 VFMADD213PD	-0x180(%RDX),%ZMM1,%ZMM14

  (105) 0x40f2ce VFMADD213PD	-0x1c0(%RDX),%ZMM1,%ZMM13

  (105) 0x40f2d5 VFMADD213PD	0x100(%RDX),%ZMM1,%ZMM12

  (105) 0x40f2dc VFMADD213PD	0xc0(%RDX),%ZMM1,%ZMM11

  (105) 0x40f2e3 VFMADD213PD	0x80(%RDX),%ZMM1,%ZMM10

  (105) 0x40f2ea VFMADD213PD	0x40(%RDX),%ZMM1,%ZMM9

  (105) 0x40f2f1 VMOVUPD	%ZMM9,0x40(%RDX)

  (105) 0x40f2f8 VMOVUPD	%ZMM10,0x80(%RDX)

  (105) 0x40f2ff VMOVUPD	%ZMM11,0xc0(%RDX)

  (105) 0x40f306 VMOVUPD	%ZMM12,0x100(%RDX)

  (105) 0x40f30d VMOVUPD	%ZMM13,-0x1c0(%RDX)

  (105) 0x40f314 VMOVUPD	%ZMM14,-0x180(%RDX)

  (105) 0x40f31b VMOVUPD	%ZMM15,-0x140(%RDX)

  (105) 0x40f322 VMOVUPD	%ZMM16,-0x100(%RDX)

  (105) 0x40f329 VMOVUPD	%ZMM17,-0xc0(%RDX)

  (105) 0x40f330 VMOVUPD	%ZMM18,-0x80(%RDX)

  (105) 0x40f337 VMOVUPD	%ZMM19,-0x40(%RDX)

  (105) 0x40f33e VMOVUPD	%ZMM20,(%RDX)

  (105) 0x40f344 CMP	%R13D,%R14D

  (105) 0x40f347 JB	40f230

(102) 0x40f34d CMP	%R13D,%R15D

(102) 0x40f350 JNE	40f36b

(102) 0x40f352 CMP	%R15D,%R8D

(102) 0x40f355 JE	40f130

(102) 0x40f35b JMP	40f48e

(102) 0x40f360 XOR	%R13D,%R13D

(102) 0x40f363 JMP	40f48e

(102) 0x40f368 XOR	%R13D,%R13D

(102) 0x40f36b MOV	%R13D,%EBX

(102) 0x40f36e LEA	(%RBX,%RBX,2),%RDX

(102) 0x40f372 VPBROADCASTQ	%R12,%ZMM9

(102) 0x40f378 VPADDQ	%ZMM2,%ZMM9,%ZMM9

(102) 0x40f37e LEA	(%R11,%RDX,8),%R14

(102) 0x40f382 ADD	%R9,%R14

(102) 0x40f385 NOPW	%CS:(%RAX,%RAX,1)

  (104) 0x40f390 VPBROADCASTQ	%RBX,%ZMM10

  (104) 0x40f396 VPCMPEQB	%XMM0,%XMM0,%K1

  (104) 0x40f39c VXORPD	%XMM12,%XMM12,%XMM12

  (104) 0x40f3a1 VXORPD	%XMM13,%XMM13,%XMM13

  (104) 0x40f3a6 VXORPD	%XMM14,%XMM14,%XMM14

  (104) 0x40f3ab ADD	$0x8,%RBX

  (104) 0x40f3af VPADDQ	%ZMM10,%ZMM9,%ZMM10

  (104) 0x40f3b5 VPADDQ	%ZMM10,%ZMM10,%ZMM11

  (104) 0x40f3bb VPADDQ	%ZMM10,%ZMM11,%ZMM10

  (104) 0x40f3c1 VPXOR	%XMM11,%XMM11,%XMM11

  (104) 0x40f3c6 VGATHERQPD	(%R10,%ZMM10,8),%ZMM11{%K1}

  (104) 0x40f3cd VPCMPEQB	%XMM0,%XMM0,%K1

  (104) 0x40f3d3 VGATHERQPD	(%R9,%ZMM10,8),%ZMM12{%K1}

  (104) 0x40f3da VPCMPEQB	%XMM0,%XMM0,%K1

  (104) 0x40f3e0 VFMADD231PD	%ZMM11,%ZMM1,%ZMM12

  (104) 0x40f3e6 VXORPD	%XMM11,%XMM11,%XMM11

  (104) 0x40f3eb VGATHERQPD	0x8(%R10,%ZMM10,8),%ZMM11{%K1}

  (104) 0x40f3f3 VPCMPEQB	%XMM0,%XMM0,%K1

  (104) 0x40f3f9 VGATHERQPD	0x8(%R9,%ZMM10,8),%ZMM13{%K1}

  (104) 0x40f401 VPCMPEQB	%XMM0,%XMM0,%K1

  (104) 0x40f407 VMOVAPD	%ZMM12,%ZMM15

  (104) 0x40f40d VFMADD231PD	%ZMM11,%ZMM1,%ZMM13

  (104) 0x40f413 VXORPD	%XMM11,%XMM11,%XMM11

  (104) 0x40f418 VGATHERQPD	0x10(%R10,%ZMM10,8),%ZMM11{%K1}

  (104) 0x40f420 VPCMPEQB	%XMM0,%XMM0,%K1

  (104) 0x40f426 VGATHERQPD	0x10(%R9,%ZMM10,8),%ZMM14{%K1}

  (104) 0x40f42e VMOVAPD	%ZMM13,%ZMM10

  (104) 0x40f434 VPERMT2PD	%ZMM12,%ZMM3,%ZMM10

  (104) 0x40f43a VPERMT2PD	%ZMM13,%ZMM4,%ZMM15

  (104) 0x40f440 VPERMT2PD	%ZMM13,%ZMM5,%ZMM12

  (104) 0x40f446 VFMADD231PD	%ZMM11,%ZMM1,%ZMM14

  (104) 0x40f44c VPERMT2PD	%ZMM14,%ZMM6,%ZMM12

  (104) 0x40f452 VPERMT2PD	%ZMM14,%ZMM7,%ZMM15

  (104) 0x40f458 VPERMT2PD	%ZMM14,%ZMM8,%ZMM10

  (104) 0x40f45e VMOVUPD	%ZMM10,0x80(%R14)

  (104) 0x40f465 VMOVUPD	%ZMM15,0x40(%R14)

  (104) 0x40f46c VMOVUPD	%ZMM12,(%R14)

  (104) 0x40f472 ADD	$0xc0,%R14

  (104) 0x40f479 CMP	%R15D,%EBX

  (104) 0x40f47c JB	40f390

(102) 0x40f482 MOV	%R15D,%R13D

(102) 0x40f485 CMP	%R15D,%R8D

(102) 0x40f488 JE	40f130

(102) 0x40f48e MOV	%R13D,%EDX

(102) 0x40f491 SAL	$0x3,%RDX

(102) 0x40f495 SUB	%R13D,%R8D

(102) 0x40f498 LEA	(%RDX,%RDX,2),%RDX

(102) 0x40f49c ADD	%RDX,%R9

(102) 0x40f49f ADD	%RDX,%R10

(102) 0x40f4a2 NOPW	%CS:(%RAX,%RAX,1)

  (103) 0x40f4b0 VMOVSD	(%R10,%R11,1),%XMM9

  (103) 0x40f4b6 VFMADD213SD	(%R9,%R11,1),%XMM0,%XMM9

  (103) 0x40f4bc VMOVSD	%XMM9,(%R9,%R11,1)

  (103) 0x40f4c2 VMOVUPD	0x8(%R10,%R11,1),%XMM9

  (103) 0x40f4c9 VFMADD213PD	0x8(%R9,%R11,1),%XMM1,%XMM9

  (103) 0x40f4d0 VMOVUPD	%XMM9,0x8(%R9,%R11,1)

  (103) 0x40f4d7 ADD	$0x18,%R11

  (103) 0x40f4db DEC	%R8D

  (103) 0x40f4de JNE	40f4b0

(102) 0x40f4e0 JMP	40f130

0x40f4e5 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run icx_0

Source file and lines	timestep.c:71-80
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-80.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.75 to 4.00 cycles (1.94x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 7.75 to 0.61 cycles (12.64x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_4@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBQ: 7 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 96 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	64
nb uops	62
loop length	273
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	8
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.75 cycles
front end	7.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.17	3.17	3.17	3.17	3.17	3.17	5.50	5.50	5.50	5.50	0.00	4.00	4.00	0.00	0.00	0.00
cycles	3.17	3.17	3.17	3.17	3.17	3.17	5.50	5.50	5.50	5.50	0.00	4.00	4.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.75
Dispatch	5.50
Overall L1	7.75

Vectorization ratios

all	29%
load	77%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

all	10%
load	11%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.75 cycles. At this rate:

4% of peak load performance is reached (12.39 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.75 to 5.50 cycles (1.41x speedup).

ASM code

In the binary file, the address of the function is: 40f030

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R9D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x38(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x3c(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $0x42c8f0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 403250 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x2c(%RBP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 40f0ba <advanceVelocity.extracted+0x8a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOV $0x42c910,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 403320 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VPMOVSXBQ 0x115e0(%RIP),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x115de(%RIP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x115dc(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x115da(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x115d8(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x115d6(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x115d4(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VMOVQ %R15,%XMM0	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %XMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x18(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x78(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 40f143 <advanceVelocity.extracted+0x113>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run icx_0

Source file and lines	timestep.c:71-80
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.75 to 4.00 cycles (1.94x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_4@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBQ: 7 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 96 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	64
nb uops	62
loop length	273
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	8
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.75 cycles
front end	7.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.17	3.17	3.17	3.17	3.17	3.17	5.50	5.50	5.50	5.50	0.00	4.00	4.00	0.00	0.00	0.00
cycles	3.17	3.17	3.17	3.17	3.17	3.17	5.50	5.50	5.50	5.50	0.00	4.00	4.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.75
Dispatch	5.50
Overall L1	7.75

Vectorization ratios

all	29%
load	77%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

all	10%
load	11%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.75 cycles. At this rate:

4% of peak load performance is reached (12.39 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40f030

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R9D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x38(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x3c(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $0x42c8f0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 403250 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x2c(%RBP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 40f0ba <advanceVelocity.extracted+0x8a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOV $0x42c910,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 403320 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VPMOVSXBQ 0x115e0(%RIP),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x115de(%RIP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x115dc(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x115da(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x115d8(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x115d6(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VPMOVSXBQ 0x115d4(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (12.5%)
VMOVQ %R15,%XMM0	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %XMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x18(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x78(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 40f143 <advanceVelocity.extracted+0x113>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

Name	Coverage (%)	Time (s)
▼advanceVelocity.extracted–	1.52	0.11
▼Loop 102 - timestep.c:71-80 - exec–	0.00	0.01
○Loop 104 - timestep.c:74-78 - exec	1.27	0.09
○Loop 103 - timestep.c:74-77 - exec	0.24	0.02
○Loop 105 - timestep.c:74-78 - exec	0.00	0.01
○Loop 106 - timestep.c:74-78 - exec	0.00	0.00

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