OV - exec - Function ljForce.extracted.27

	Function: ljForce.extracted.27	Module: exec	Source: ljForce.c:157-162 [...]	Coverage (incl. loops): 1.97% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 157 - 162

--------------------------------------------------------------------------------

157:    #pragma omp parallel for

158:    for (int ii=0; ii<fSize; ++ii)

159:    {

160:       zeroReal3(s->atoms->f[ii]);

161:       s->atoms->U[ii] = 0.;

162:    }

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/mytype.h: 23 - 23

--------------------------------------------------------------------------------

23:    a[1] = 0.0;

0x40ba30 PUSH	%RBP

0x40ba31 MOV	%RSP,%RBP

0x40ba34 PUSH	%R14

0x40ba36 PUSH	%RBX

0x40ba37 SUB	$0x10,%RSP

0x40ba3b MOVL	$0,-0x20(%RBP)

0x40ba42 MOV	%RDX,%R14

0x40ba45 MOV	(%RDI),%EBX

0x40ba47 MOVL	$0,-0x18(%RBP)

0x40ba4e MOV	%R8D,-0x14(%RBP)

0x40ba52 MOVL	$0x1,-0x1c(%RBP)

0x40ba59 SUB	$0x8,%RSP

0x40ba5d MOV	$0x22,%EDX

0x40ba62 MOV	%EBX,%ESI

0x40ba64 LEA	-0x1c(%RBP),%RAX

0x40ba68 LEA	-0x20(%RBP),%RCX

0x40ba6c LEA	-0x18(%RBP),%R8

0x40ba70 LEA	-0x14(%RBP),%R9

0x40ba74 MOV	$0x42c830,%EDI

0x40ba79 PUSH	$0x1

0x40ba7b PUSH	$0x1

0x40ba7d PUSH	%RAX

0x40ba7e CALL	403250 <__kmpc_for_static_init_4@plt>

0x40ba83 ADD	$0x20,%RSP

0x40ba87 MOV	-0x18(%RBP),%EDX

0x40ba8a MOV	-0x14(%RBP),%ESI

0x40ba8d CMP	%EDX,%ESI

0x40ba8f JB	40bc00

0x40ba95 MOV	0x20(%R14),%RCX

0x40ba99 SUB	%EDX,%ESI

0x40ba9b MOV	0x28(%RCX),%RAX

0x40ba9f MOV	0x30(%RCX),%RDI

0x40baa3 LEA	0x1(%RSI),%RCX

0x40baa7 CMP	$0x7,%ESI

0x40baaa JB	40bba6

0x40bab0 LEA	(%RDX,%RDX,2),%R9

0x40bab4 MOV	%RCX,%R8

0x40bab7 SHR	$0x3,%R8

0x40babb LEA	0x38(%RDI,%RDX,8),%R10

0x40bac0 XOR	%R11D,%R11D

0x40bac3 VXORPS	%XMM0,%XMM0,%XMM0

0x40bac7 SAL	$0x6,%R8

0x40bacb LEA	(%RAX,%R9,8),%R9

0x40bacf NOP

(99) 0x40bad0 LEA	-0x38(%R10,%R11,1),%R14

(99) 0x40bad5 VMOVUPS	%XMM0,(%R9)

(99) 0x40bada MOVQ	$0,0x10(%R9)

(99) 0x40bae2 ADD	$0x40,%R11

(99) 0x40bae6 MOVQ	$0,(%R14)

(99) 0x40baed VMOVUPS	%XMM0,0x18(%R9)

(99) 0x40baf3 MOVQ	$0,0x28(%R9)

(99) 0x40bafb MOVQ	$0,0x8(%R14)

(99) 0x40bb03 VMOVUPS	%XMM0,0x30(%R9)

(99) 0x40bb09 MOVQ	$0,0x40(%R9)

(99) 0x40bb11 MOVQ	$0,0x10(%R14)

(99) 0x40bb19 VMOVUPS	%XMM0,0x48(%R9)

(99) 0x40bb1f MOVQ	$0,0x58(%R9)

(99) 0x40bb27 MOVQ	$0,0x18(%R14)

(99) 0x40bb2f VMOVUPS	%XMM0,0x60(%R9)

(99) 0x40bb35 MOVQ	$0,0x70(%R9)

(99) 0x40bb3d MOVQ	$0,0x20(%R14)

(99) 0x40bb45 VMOVUPS	%XMM0,0x78(%R9)

(99) 0x40bb4b MOVQ	$0,0x88(%R9)

(99) 0x40bb56 MOVQ	$0,0x28(%R14)

(99) 0x40bb5e VMOVUPS	%XMM0,0x90(%R9)

(99) 0x40bb67 MOVQ	$0,0xa0(%R9)

(99) 0x40bb72 MOVQ	$0,0x30(%R14)

(99) 0x40bb7a VMOVUPS	%XMM0,0xa8(%R9)

(99) 0x40bb83 MOVQ	$0,0xb8(%R9)

(99) 0x40bb8e ADD	$0xc0,%R9

(99) 0x40bb95 MOVQ	$0,0x38(%R14)

(99) 0x40bb9d CMP	%R11,%R8

(99) 0x40bba0 JNE	40bad0

0x40bba6 MOV	%ECX,%R8D

0x40bba9 AND	$-0x8,%R8D

0x40bbad CMP	%RSI,%R8

0x40bbb0 JA	40bc00

0x40bbb2 LEA	(%RDI,%RDX,8),%RSI

0x40bbb6 MOV	%ECX,%EDI

0x40bbb8 SHR	$0x3,%EDI

0x40bbbb LEA	(%RDX,%RDX,2),%RDX

0x40bbbf VXORPS	%XMM0,%XMM0,%XMM0

0x40bbc3 LEA	(%RDI,%RDI,2),%RDI

0x40bbc7 SAL	$0x6,%RDI

0x40bbcb LEA	(%RDI,%RDX,8),%RDX

0x40bbcf ADD	%RDX,%RAX

0x40bbd2 NOPW	%CS:(%RAX,%RAX,1)

(98) 0x40bbe0 VMOVUPS	%XMM0,(%RAX)

(98) 0x40bbe4 MOVQ	$0,0x10(%RAX)

(98) 0x40bbec MOVQ	$0,(%RSI,%R8,8)

(98) 0x40bbf4 INC	%R8

(98) 0x40bbf7 ADD	$0x18,%RAX

(98) 0x40bbfb CMP	%R8,%RCX

(98) 0x40bbfe JNE	40bbe0

0x40bc00 MOV	$0x42c850,%EDI

0x40bc05 MOV	%EBX,%ESI

0x40bc07 ADD	$0x10,%RSP

0x40bc0b POP	%RBX

0x40bc0c POP	%R14

0x40bc0e POP	%RBP

0x40bc0f JMP	403320

0x40bc14 NOPW	%CS:(%RAX,%RAX,1)

0x40bc1e XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	ljForce.c:157-162
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157-162
/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:23

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.13 to 1.17 cycles (6.96x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.13 to 0.53 cycles (15.31x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_4@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	67
nb uops	65
loop length	250
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.13 cycles
front end	8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.13
Dispatch	5.67
Overall L1	8.13

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Vector efficiency ratios

INT

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.13 cycles. At this rate:

1% of peak load performance is reached (4.43 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.97 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.13 to 5.67 cycles (1.43x speedup).

ASM code

In the binary file, the address of the function is: 40ba30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVL $0,-0x20(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOVL $0,-0x18(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R8D,-0x14(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0x1,-0x1c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x1c(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x20(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x18(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x14(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x42c830,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 403250 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x18(%RBP),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x14(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 40bc00 <ljForce.extracted.27+0x1d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV 0x20(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SUB %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RSI),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x7,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 40bba6 <ljForce.extracted.27+0x176>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
LEA (%RDX,%RDX,2),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SHR $0x3,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
LEA 0x38(%RDI,%RDX,8),%R10	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SAL $0x6,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
LEA (%RAX,%R9,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %ECX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
AND $-0x8,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %RSI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JA 40bc00 <ljForce.extracted.27+0x1d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
LEA (%RDI,%RDX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %ECX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%EDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA (%RDX,%RDX,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA (%RDI,%RDI,2),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SAL $0x6,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA (%RDI,%RDX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV $0x42c850,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JMP 403320 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	ljForce.c:157-162
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157-162
/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:23

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.13 to 1.17 cycles (6.96x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_4@plt: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	67
nb uops	65
loop length	250
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.13 cycles
front end	8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.13
Dispatch	5.67
Overall L1	8.13

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Vector efficiency ratios

INT

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.13 cycles. At this rate:

1% of peak load performance is reached (4.43 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.97 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40ba30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVL $0,-0x20(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOVL $0,-0x18(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R8D,-0x14(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0x1,-0x1c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x1c(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x20(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x18(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x14(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x42c830,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 403250 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x18(%RBP),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x14(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 40bc00 <ljForce.extracted.27+0x1d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV 0x20(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SUB %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RSI),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x7,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 40bba6 <ljForce.extracted.27+0x176>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
LEA (%RDX,%RDX,2),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SHR $0x3,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
LEA 0x38(%RDI,%RDX,8),%R10	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SAL $0x6,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
LEA (%RAX,%R9,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %ECX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
AND $-0x8,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %RSI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JA 40bc00 <ljForce.extracted.27+0x1d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
LEA (%RDI,%RDX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %ECX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%EDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA (%RDX,%RDX,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA (%RDI,%RDI,2),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SAL $0x6,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA (%RDI,%RDX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV $0x42c850,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JMP 403320 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼ljForce.extracted.27–	1.97	0.15
○Loop 99 - ljForce.c:158-162 - exec	1.97	0.14
○Loop 98 - ljForce.c:158-162 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code