OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:211-385 [...]	Coverage (incl. loops): 0.28% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 211 - 385

--------------------------------------------------------------------------------

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

[...]

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

[...]

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

372:    {

373:       if (iz == gridSize[2]) iz = gridSize[2] - 1;

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x40ad70 PUSH	%RBP

0x40ad71 MOV	%RSP,%RBP

0x40ad74 PUSH	%R15

0x40ad76 PUSH	%R14

0x40ad78 PUSH	%R13

0x40ad7a PUSH	%R12

0x40ad7c PUSH	%RBX

0x40ad7d SUB	$0x28,%RSP

0x40ad81 MOV	0xc(%RDI),%EAX

0x40ad84 CMP	0x14(%RDI),%EAX

0x40ad87 JGE	40ada6

0x40ad89 MOV	0x78(%RDI),%RCX

0x40ad8d CLTQ

0x40ad8f NOP

(91) 0x40ad90 MOVL	$0,(%RCX,%RAX,4)

(91) 0x40ad97 INC	%RAX

(91) 0x40ad9a MOVSXD	0x14(%RDI),%RDX

(91) 0x40ad9e CMP	%RDX,%RAX

(91) 0x40ada1 JL	40ad90

0x40ada3 MOV	0xc(%RDI),%EAX

0x40ada6 MOV	%RAX,-0x30(%RBP)

0x40adaa TEST	%EAX,%EAX

0x40adac JLE	40b188

0x40adb2 MOV	0x78(%RDI),%R10

0x40adb6 XOR	%EAX,%EAX

0x40adb8 JMP	40add0

0x40adba NOPW	(%RAX,%RAX,1)

(89) 0x40adc0 MOVSXD	-0x30(%RBP),%RCX

(89) 0x40adc4 INC	%RAX

(89) 0x40adc7 CMP	%RCX,%RAX

(89) 0x40adca JGE	40b188

(89) 0x40add0 CMPL	$0,(%R10,%RAX,4)

(89) 0x40add5 JLE	40adc0

(89) 0x40add7 MOV	%RAX,%RCX

(89) 0x40adda SAL	$0x6,%RCX

(89) 0x40adde XOR	%EDX,%EDX

(89) 0x40ade0 MOV	%RAX,-0x48(%RBP)

(89) 0x40ade4 MOV	%RCX,-0x40(%RBP)

(89) 0x40ade8 MOV	-0x30(%RBP),%RCX

(89) 0x40adec MOV	%ECX,%R14D

(89) 0x40adef JMP	40ae10

0x40adf1 NOPW	%CS:(%RAX,%RAX,1)

  (90) 0x40ae00 MOV	-0x38(%RBP),%RDX

  (90) 0x40ae04 INC	%EDX

  (90) 0x40ae06 MOV	0x78(%RDI),%R10

  (90) 0x40ae0a CMP	(%R10,%RAX,4),%EDX

  (90) 0x40ae0e JGE	40adc0

  (90) 0x40ae10 MOV	-0x40(%RBP),%RCX

  (90) 0x40ae14 MOV	0x18(%RSI),%R11

  (90) 0x40ae18 VMOVSD	0x30(%RDI),%XMM1

  (90) 0x40ae1d MOV	(%RDI),%R13D

  (90) 0x40ae20 ADD	%EDX,%ECX

  (90) 0x40ae22 MOV	%R13D,%R12D

  (90) 0x40ae25 MOVSXD	%ECX,%R9

  (90) 0x40ae28 LEA	(%R9,%R9,2),%RBX

  (90) 0x40ae2c VMOVSD	(%R11,%RBX,8),%XMM0

  (90) 0x40ae32 VUCOMISD	%XMM0,%XMM1

  (90) 0x40ae36 JBE	40ae55

  (90) 0x40ae38 VSUBSD	0x18(%RDI),%XMM0,%XMM0

  (90) 0x40ae3d VMULSD	0x60(%RDI),%XMM0,%XMM0

  (90) 0x40ae42 VROUNDSD	$0x9,%XMM0,%XMM0,%XMM0

  (90) 0x40ae48 VCVTTSD2SI	%XMM0,%R12D

  (90) 0x40ae4c CMP	%R12D,%R13D

  (90) 0x40ae4f JNE	40ae55

  (90) 0x40ae51 LEA	-0x1(%R13),%R12D

  (90) 0x40ae55 VMOVSD	0x8(%R11,%RBX,8),%XMM0

  (90) 0x40ae5c MOV	0x4(%RDI),%ECX

  (90) 0x40ae5f MOV	%R14D,%EAX

  (90) 0x40ae62 VSUBSD	0x20(%RDI),%XMM0,%XMM1

  (90) 0x40ae67 VMULSD	0x68(%RDI),%XMM1,%XMM1

  (90) 0x40ae6c VROUNDSD	$0x9,%XMM1,%XMM1,%XMM1

  (90) 0x40ae72 VCVTTSD2SI	%XMM1,%R15D

  (90) 0x40ae76 CMP	%R15D,%ECX

  (90) 0x40ae79 JNE	40ae7f

  (90) 0x40ae7b LEA	-0x1(%RCX),%R15D

  (90) 0x40ae7f VMOVSD	0x38(%RDI),%XMM1

  (90) 0x40ae84 VMOVSD	0x10(%R11,%RBX,8),%XMM2

  (90) 0x40ae8b VMOVSD	0x40(%RDI),%XMM3

  (90) 0x40ae90 MOV	0x8(%RDI),%R14D

  (90) 0x40ae94 MOV	%RDX,-0x38(%RBP)

  (90) 0x40ae98 MOV	%R15D,%EDX

  (90) 0x40ae9b VUCOMISD	%XMM0,%XMM1

  (90) 0x40ae9f CMOVBE	%ECX,%EDX

  (90) 0x40aea2 VUCOMISD	%XMM2,%XMM3

  (90) 0x40aea6 JBE	40aef0

  (90) 0x40aea8 VSUBSD	0x28(%RDI),%XMM2,%XMM2

  (90) 0x40aead VMULSD	0x70(%RDI),%XMM2,%XMM2

  (90) 0x40aeb2 VROUNDSD	$0x9,%XMM2,%XMM2,%XMM2

  (90) 0x40aeb8 VCVTTSD2SI	%XMM2,%R8D

  (90) 0x40aebc CMP	%R8D,%R14D

  (90) 0x40aebf JNE	40aec5

  (90) 0x40aec1 LEA	-0x1(%R14),%R8D

  (90) 0x40aec5 CMP	$-0x1,%R8D

  (90) 0x40aec9 JE	40af28

  (90) 0x40aecb VUCOMISD	%XMM0,%XMM1

  (90) 0x40aecf JA	40af5d

  (90) 0x40aed5 IMUL	%R14D,%ECX

  (90) 0x40aed9 ADD	$0x2,%R13D

  (90) 0x40aedd ADD	%R14D,%R8D

  (90) 0x40aee0 IMUL	%R13D,%R8D

  (90) 0x40aee4 LEA	(%R12,%RCX,2),%ECX

  (90) 0x40aee8 ADD	%R8D,%ECX

  (90) 0x40aeeb JMP	40afa1

  (90) 0x40aef0 LEA	(%RDX,%R14,2),%EDX

  (90) 0x40aef4 LEA	(%R14,%R14,1),%R8D

  (90) 0x40aef8 ADD	$0x2,%R13D

  (90) 0x40aefc ADD	%EAX,%R12D

  (90) 0x40aeff MOV	%EAX,%R14D

  (90) 0x40af02 IMUL	%ECX,%R8D

  (90) 0x40af06 LEA	0x3(%RCX,%RDX,1),%ECX

  (90) 0x40af0a IMUL	%R13D,%ECX

  (90) 0x40af0e ADD	%R8D,%R12D

  (90) 0x40af11 LEA	0x1(%RCX,%R12,1),%R15D

  (90) 0x40af16 MOV	-0x48(%RBP),%RAX

  (90) 0x40af1a TEST	%R15D,%R15D

  (90) 0x40af1d JNS	40afba

0x40af23 JMP	40b16f

  (90) 0x40af28 LEA	(%R14,%R14,1),%R8D

  (90) 0x40af2c LEA	0x1(%RDX,%R14,2),%EDX

  (90) 0x40af31 ADD	$0x2,%R13D

  (90) 0x40af35 IMUL	%R8D,%ECX

  (90) 0x40af39 IMUL	%R13D,%EDX

  (90) 0x40af3d ADD	%ECX,%R12D

  (90) 0x40af40 MOV	-0x30(%RBP),%RCX

  (90) 0x40af44 ADD	%EDX,%R12D

  (90) 0x40af47 LEA	0x1(%RCX,%R12,1),%R15D

  (90) 0x40af4c MOV	%ECX,%R14D

  (90) 0x40af4f MOV	-0x48(%RBP),%RAX

  (90) 0x40af53 TEST	%R15D,%R15D

  (90) 0x40af56 JNS	40afba

0x40af58 JMP	40b16f

  (90) 0x40af5d CMP	$-0x1,%R15D

  (90) 0x40af61 JE	40af8e

  (90) 0x40af63 CMP	%R13D,%R12D

  (90) 0x40af66 JNE	40b13b

  (90) 0x40af6c MOV	-0x30(%RBP),%RDX

  (90) 0x40af70 ADD	%R14D,%R8D

  (90) 0x40af73 IMUL	%R8D,%ECX

  (90) 0x40af77 ADD	%EDX,%R15D

  (90) 0x40af7a MOV	%EDX,%R14D

  (90) 0x40af7d ADD	%ECX,%R15D

  (90) 0x40af80 MOV	-0x48(%RBP),%RAX

  (90) 0x40af84 TEST	%R15D,%R15D

  (90) 0x40af87 JNS	40afba

0x40af89 JMP	40b16f

  (90) 0x40af8e IMUL	%ECX,%R14D

  (90) 0x40af92 ADD	$0x2,%R13D

  (90) 0x40af96 IMUL	%R8D,%R13D

  (90) 0x40af9a LEA	(%R12,%R14,2),%ECX

  (90) 0x40af9e ADD	%R13D,%ECX

  (90) 0x40afa1 MOV	-0x30(%RBP),%RDX

  (90) 0x40afa5 LEA	0x1(%RDX,%RCX,1),%R15D

  (90) 0x40afaa MOV	%EDX,%R14D

  (90) 0x40afad MOV	-0x48(%RBP),%RAX

  (90) 0x40afb1 TEST	%R15D,%R15D

  (90) 0x40afb4 JS	40b16f

  (90) 0x40afba CMP	0x14(%RDI),%R15D

  (90) 0x40afbe JGE	40b197

  (90) 0x40afc4 MOV	%R15D,%R8D

  (90) 0x40afc7 CMP	%R8,%RAX

  (90) 0x40afca JE	40ae00

  (90) 0x40afd0 MOV	0x8(%RSI),%R14

  (90) 0x40afd4 MOVSXD	(%R10,%R8,4),%R10

  (90) 0x40afd8 LEA	(%R11,%RBX,8),%RCX

  (90) 0x40afdc MOVSXD	%R15D,%RDX

  (90) 0x40afdf SAL	$0x6,%RDX

  (90) 0x40afe3 MOV	(%R14,%R9,4),%EBX

  (90) 0x40afe7 ADD	%R10,%RDX

  (90) 0x40afea MOV	%EBX,(%R14,%RDX,4)

  (90) 0x40afee MOV	0x10(%RSI),%R10

  (90) 0x40aff2 MOV	(%R10,%R9,4),%EBX

  (90) 0x40aff6 MOV	%EBX,(%R10,%RDX,4)

  (90) 0x40affa LEA	(,%RDX,8),%R10

  (90) 0x40b002 MOV	0x10(%RCX),%RBX

  (90) 0x40b006 LEA	(%R10,%R10,2),%R10

  (90) 0x40b00a MOV	%RBX,0x10(%R11,%R10,1)

  (90) 0x40b00f VMOVUPS	(%RCX),%XMM0

  (90) 0x40b013 LEA	(,%R9,8),%RCX

  (90) 0x40b01b LEA	(%RCX,%RCX,2),%RCX

  (90) 0x40b01f VMOVUPS	%XMM0,(%R11,%R10,1)

  (90) 0x40b025 MOV	0x20(%RSI),%R11

  (90) 0x40b029 MOV	0x10(%R11,%RCX,1),%RBX

  (90) 0x40b02e MOV	%RBX,0x10(%R11,%R10,1)

  (90) 0x40b033 VMOVUPS	(%R11,%RCX,1),%XMM0

  (90) 0x40b039 VMOVUPS	%XMM0,(%R11,%R10,1)

  (90) 0x40b03f MOV	0x28(%RSI),%R11

  (90) 0x40b043 MOV	0x10(%R11,%RCX,1),%RBX

  (90) 0x40b048 MOV	%RBX,0x10(%R11,%R10,1)

  (90) 0x40b04d VMOVUPD	(%R11,%RCX,1),%XMM0

  (90) 0x40b053 VMOVUPD	%XMM0,(%R11,%R10,1)

  (90) 0x40b059 MOV	0x30(%RSI),%R10

  (90) 0x40b05d MOV	(%R10,%R9,8),%R11

  (90) 0x40b061 MOV	%R11,(%R10,%RDX,8)

  (90) 0x40b065 MOV	0x78(%RDI),%R10

  (90) 0x40b069 MOV	(%R10,%R8,4),%EDX

  (90) 0x40b06d LEA	0x1(%RDX),%R11D

  (90) 0x40b071 MOV	%R11D,(%R10,%R8,4)

  (90) 0x40b075 CMP	$0x3f,%EDX

  (90) 0x40b078 JGE	40b1b0

  (90) 0x40b07e MOVSXD	(%R10,%RAX,4),%RDX

  (90) 0x40b082 DEC	%RDX

  (90) 0x40b085 MOV	%EDX,(%R10,%RAX,4)

  (90) 0x40b089 TEST	%EDX,%EDX

  (90) 0x40b08b JE	40b113

  (90) 0x40b091 ADD	-0x40(%RBP),%RDX

  (90) 0x40b095 MOV	0x8(%RSI),%R8

  (90) 0x40b099 MOV	(%R8,%RDX,4),%R10D

  (90) 0x40b09d MOV	%R10D,(%R8,%R9,4)

  (90) 0x40b0a1 MOV	0x10(%RSI),%R8

  (90) 0x40b0a5 MOV	(%R8,%RDX,4),%R10D

  (90) 0x40b0a9 MOV	%R10D,(%R8,%R9,4)

  (90) 0x40b0ad LEA	(,%RDX,8),%R8

  (90) 0x40b0b5 MOV	0x18(%RSI),%R10

  (90) 0x40b0b9 LEA	(%R8,%R8,2),%R8

  (90) 0x40b0bd MOV	0x10(%R10,%R8,1),%R11

  (90) 0x40b0c2 MOV	%R11,0x10(%R10,%RCX,1)

  (90) 0x40b0c7 VMOVUPS	(%R10,%R8,1),%XMM0

  (90) 0x40b0cd VMOVUPS	%XMM0,(%R10,%RCX,1)

  (90) 0x40b0d3 MOV	0x20(%RSI),%R10

  (90) 0x40b0d7 MOV	0x10(%R10,%R8,1),%R11

  (90) 0x40b0dc MOV	%R11,0x10(%R10,%RCX,1)

  (90) 0x40b0e1 VMOVUPS	(%R10,%R8,1),%XMM0

  (90) 0x40b0e7 VMOVUPS	%XMM0,(%R10,%RCX,1)

  (90) 0x40b0ed MOV	0x28(%RSI),%R10

  (90) 0x40b0f1 MOV	0x10(%R10,%R8,1),%R11

  (90) 0x40b0f6 MOV	%R11,0x10(%R10,%RCX,1)

  (90) 0x40b0fb VMOVUPD	(%R10,%R8,1),%XMM0

  (90) 0x40b101 VMOVUPD	%XMM0,(%R10,%RCX,1)

  (90) 0x40b107 MOV	0x30(%RSI),%RCX

  (90) 0x40b10b MOV	(%RCX,%RDX,8),%RDX

  (90) 0x40b10f MOV	%RDX,(%RCX,%R9,8)

  (90) 0x40b113 MOV	0xc(%RDI),%ECX

  (90) 0x40b116 MOV	%RCX,-0x30(%RBP)

  (90) 0x40b11a CMP	%ECX,%R15D

  (90) 0x40b11d JLE	40b121

  (90) 0x40b11f DECL	(%RSI)

  (90) 0x40b121 MOV	-0x38(%RBP),%RDX

  (90) 0x40b125 MOV	%ECX,%R14D

  (90) 0x40b128 MOV	0x78(%RDI),%R10

  (90) 0x40b12c CMP	(%R10,%RAX,4),%EDX

  (90) 0x40b130 JL	40ae10

(89) 0x40b136 JMP	40adc0

  (90) 0x40b13b IMUL	%R8D,%ECX

  (90) 0x40b13f MOV	-0x30(%RBP),%R8

  (90) 0x40b143 MOV	%EAX,%R14D

  (90) 0x40b146 ADD	%R15D,%ECX

  (90) 0x40b149 LEA	(%RCX,%R8,1),%EDX

  (90) 0x40b14d IMUL	%R13D,%ECX

  (90) 0x40b151 ADD	%R12D,%ECX

  (90) 0x40b154 CMP	$-0x1,%R12D

  (90) 0x40b158 CMOVE	%EDX,%ECX

  (90) 0x40b15b CMOVE	%R8D,%R14D

  (90) 0x40b15f MOV	%ECX,%R15D

  (90) 0x40b162 MOV	-0x48(%RBP),%RAX

  (90) 0x40b166 TEST	%R15D,%R15D

  (90) 0x40b169 JNS	40afba

0x40b16f MOV	$0x42178c,%EDI

0x40b174 MOV	$0x421687,%ESI

0x40b179 MOV	$0x421796,%ECX

0x40b17e MOV	$0xf6,%EDX

0x40b183 CALL	403070 <__assert_fail@plt>

0x40b188 ADD	$0x28,%RSP

0x40b18c POP	%RBX

0x40b18d POP	%R12

0x40b18f POP	%R13

0x40b191 POP	%R14

0x40b193 POP	%R15

0x40b195 POP	%RBP

0x40b196 RET

0x40b197 MOV	$0x4217c5,%EDI

0x40b19c MOV	$0x421687,%ESI

0x40b1a1 MOV	$0x421796,%ECX

0x40b1a6 MOV	$0xf7,%EDX

0x40b1ab CALL	403070 <__assert_fail@plt>

0x40b1b0 MOV	$0x4217df,%EDI

0x40b1b5 MOV	$0x421687,%ESI

0x40b1ba MOV	$0x4217fe,%ECX

0x40b1bf MOV	$0x106,%EDX

0x40b1c4 CALL	403070 <__assert_fail@plt>

0x40b1c9 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►74.39+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
►24.97+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	linkCells.c:211-385
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-237,246-247,258-269,288-304,327-334,352-365,371-373,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.00 to 0.40 cycles (14.81x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:384

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	50
nb uops	48
loop length	188
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.33	4.33	4.33	4.33	4.33	4.33	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.33	4.33	4.33	4.33	4.33	4.33	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	4.33
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

1% of peak load performance is reached (4.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 4.33 cycles (1.38x speedup).

ASM code

In the binary file, the address of the function is: 40ad70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xc(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP 0x14(%RDI),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JGE 40ada6 <updateLinkCells+0x36>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CLTQ																				scal (12.5%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xc(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40b188 <updateLinkCells+0x418>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 40add0 <updateLinkCells+0x60>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 40b16f <updateLinkCells+0x3ff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
JMP 40b16f <updateLinkCells+0x3ff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
JMP 40b16f <updateLinkCells+0x3ff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV $0x42178c,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x421687,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x421796,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403070 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x4217c5,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x421687,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x421796,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403070 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV $0x4217df,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x421687,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x4217fe,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x106,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403070 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	linkCells.c:211-385
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:384

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	50
nb uops	48
loop length	188
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.33	4.33	4.33	4.33	4.33	4.33	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.33	4.33	4.33	4.33	4.33	4.33	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	4.33
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

1% of peak load performance is reached (4.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40ad70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xc(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP 0x14(%RDI),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JGE 40ada6 <updateLinkCells+0x36>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CLTQ																				scal (12.5%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xc(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40b188 <updateLinkCells+0x418>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 40add0 <updateLinkCells+0x60>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 40b16f <updateLinkCells+0x3ff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
JMP 40b16f <updateLinkCells+0x3ff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
JMP 40b16f <updateLinkCells+0x3ff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV $0x42178c,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x421687,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x421796,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403070 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x4217c5,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x421687,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x421796,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403070 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV $0x4217df,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x421687,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x4217fe,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x106,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403070 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.28	0.02
▼Loop 89 - linkCells.c:211-373 - exec–	0.00	0.03
○Loop 90 - linkCells.c:211-373 - exec	0.27	1.91
○Loop 91 - linkCells.c:384-385 - exec	0.00	0.00

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