OV - exec - Function advanceVelocity.omp

	Function: advanceVelocity.omp_outlined	Module: exec	Source: timestep.c:71-78	Coverage (incl. loops): 1.31% \| (excl. loops): 0.05%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

0x211fb0 PUSH	%RBP

0x211fb1 MOV	%RSP,%RBP

0x211fb4 PUSH	%R15

0x211fb6 PUSH	%R14

0x211fb8 PUSH	%R13

0x211fba PUSH	%R12

0x211fbc PUSH	%RBX

0x211fbd SUB	$0x38,%RSP

0x211fc1 MOV	(%RDX),%R14D

0x211fc4 TEST	%R14D,%R14D

0x211fc7 JLE	212047

0x211fc9 MOV	(%RDI),%ESI

0x211fcb DEC	%R14D

0x211fce MOV	%R8,%RBX

0x211fd1 MOV	%RCX,%R15

0x211fd4 MOVL	$0,-0x30(%RBP)

0x211fdb MOVL	$0x1,-0x3c(%RBP)

0x211fe2 MOVL	$0,-0x38(%RBP)

0x211fe9 MOV	%R14D,-0x2c(%RBP)

0x211fed SUB	$0x8,%RSP

0x211ff1 LEA	-0x3c(%RBP),%RAX

0x211ff5 LEA	0x22dc(%RIP),%RDI

0x211ffc LEA	-0x38(%RBP),%RCX

0x212000 LEA	-0x30(%RBP),%R8

0x212004 LEA	-0x2c(%RBP),%R9

0x212008 MOV	%ESI,-0x34(%RBP)

0x21200b MOV	$0x22,%EDX

0x212010 PUSH	$0x1

0x212012 PUSH	$0x1

0x212014 PUSH	%RAX

0x212015 CALL	212de0 <@plt_start@+0x180>

0x21201a ADD	$0x20,%RSP

0x21201e MOV	-0x2c(%RBP),%EAX

0x212021 CMP	%R14D,%EAX

0x212024 CMOVL	%EAX,%R14D

0x212028 MOVSXD	-0x30(%RBP),%RAX

0x21202c MOV	%R14D,-0x2c(%RBP)

0x212030 CMP	%R14D,%EAX

0x212033 JLE	212056

0x212035 MOV	-0x34(%RBP),%ESI

0x212038 LEA	0x22b1(%RIP),%RDI

0x21203f VZEROUPPER

0x212042 CALL	212df0 <@plt_start@+0x190>

0x212047 ADD	$0x38,%RSP

0x21204b POP	%RBX

0x21204c POP	%R12

0x21204e POP	%R13

0x212050 POP	%R14

0x212052 POP	%R15

0x212054 POP	%RBP

0x212055 RET

0x212056 MOV	(%R15),%RDX

0x212059 VMOVAPD	-0xcee1(%RIP),%YMM0

0x212061 VMOVAPD	-0xcea9(%RIP),%YMM1

0x212069 VMOVAPD	-0xcf11(%RIP),%YMM2

0x212071 VMOVAPD	-0xcf39(%RIP),%YMM3

0x212079 VMOVAPD	-0xc503(%RIP),%ZMM4

0x212083 VMOVAPD	-0xc80d(%RIP),%ZMM5

0x21208d VMOVAPD	-0xc7d7(%RIP),%ZMM6

0x212097 VMOVAPD	-0xc7a1(%RIP),%ZMM7

0x2120a1 VMOVAPD	-0xc76b(%RIP),%ZMM8

0x2120ab VMOVAPD	-0xc735(%RIP),%ZMM9

0x2120b5 VMOVAPD	-0xc6ff(%RIP),%ZMM10

0x2120bf VMOVAPD	-0xc6c9(%RIP),%ZMM11

0x2120c9 VMOVAPD	-0xc693(%RIP),%ZMM12

0x2120d3 VMOVAPD	-0xc65d(%RIP),%ZMM13

0x2120dd VMOVAPD	-0xc627(%RIP),%ZMM14

0x2120e7 VMOVAPD	-0xc5f1(%RIP),%ZMM15

0x2120f1 VMOVAPD	-0xc5bb(%RIP),%ZMM16

0x2120fb MOV	%EAX,%ESI

0x2120fd SAL	$0x6,%ESI

0x212100 MOV	0x18(%RDX),%RCX

0x212104 MOV	%RDX,-0x50(%RBP)

0x212108 MOV	0x78(%RCX),%RDI

0x21210c MOVSXD	%R14D,%RCX

0x21210f MOV	%RCX,-0x60(%RBP)

0x212113 LEA	0x8(%RBX),%RCX

0x212117 MOV	%RCX,-0x58(%RBP)

0x21211b MOV	%RDI,-0x48(%RBP)

0x21211f JMP	212144

0x212121 NOPW	%CS:(%RAX,%RAX,1)

(106) 0x212130 ADD	$0x40,%ESI

(106) 0x212133 LEA	0x1(%RAX),%RCX

(106) 0x212137 CMP	-0x60(%RBP),%RAX

(106) 0x21213b MOV	%RCX,%RAX

(106) 0x21213e JGE	212035

(106) 0x212144 MOV	(%RDI,%RAX,4),%R9D

(106) 0x212148 TEST	%R9D,%R9D

(106) 0x21214b JLE	212130

(106) 0x21214d MOV	0x20(%RDX),%RCX

(106) 0x212151 MOVSXD	%ESI,%R15

(106) 0x212154 XOR	%R12D,%R12D

(106) 0x212157 MOV	0x20(%RCX),%R10

(106) 0x21215b MOV	0x28(%RCX),%R11

(106) 0x21215f CMP	$0x4,%R9D

(106) 0x212163 JB	212400

(106) 0x212169 LEA	(,%R15,8),%RCX

(106) 0x212171 LEA	(%RCX,%RCX,2),%R13

(106) 0x212175 LEA	-0x1(%R9),%ECX

(106) 0x212179 ADD	%R15,%RCX

(106) 0x21217c SAL	$0x3,%RCX

(106) 0x212180 LEA	(%R10,%R13,1),%R14

(106) 0x212184 ADD	%R11,%R13

(106) 0x212187 CMP	-0x58(%RBP),%R14

(106) 0x21218b LEA	(%RCX,%RCX,2),%RCX

(106) 0x21218f LEA	0x18(%R10,%RCX,1),%R8

(106) 0x212194 LEA	0x18(%R11,%RCX,1),%RCX

(106) 0x212199 SETB	%DL

(106) 0x21219c CMP	%RBX,%R8

(106) 0x21219f SETA	%DIL

(106) 0x2121a3 CMP	%RCX,%R14

(106) 0x2121a6 SETB	%CL

(106) 0x2121a9 CMP	%R8,%R13

(106) 0x2121ac SETB	%R8B

(106) 0x2121b0 TEST	%DIL,%DL

(106) 0x2121b3 JNE	2121d4

(106) 0x2121b5 MOV	-0x50(%RBP),%RDX

(106) 0x2121b9 MOV	-0x48(%RBP),%RDI

(106) 0x2121bd AND	%R8B,%CL

(106) 0x2121c0 JNE	212400

(106) 0x2121c6 CMP	$0x8,%R9D

(106) 0x2121ca JAE	2121e1

(106) 0x2121cc XOR	%R8D,%R8D

(106) 0x2121cf JMP	212318

(106) 0x2121d4 MOV	-0x50(%RBP),%RDX

(106) 0x2121d8 MOV	-0x48(%RBP),%RDI

(106) 0x2121dc JMP	212400

(106) 0x2121e1 MOV	%R9D,%ECX

(106) 0x2121e4 SHR	$0x3,%ECX

(106) 0x2121e7 MOV	%R9D,%R8D

(106) 0x2121ea AND	$-0x8,%R8D

(106) 0x2121ee SAL	$0x6,%RCX

(106) 0x2121f2 LEA	(%RCX,%RCX,2),%R12

(106) 0x2121f6 XOR	%ECX,%ECX

(106) 0x2121f8 NOPL	(%RAX,%RAX,1)

  (108) 0x212200 VMOVUPD	(%R13,%RCX,1),%ZMM18

  (108) 0x212208 VMOVUPD	0x40(%R13,%RCX,1),%ZMM19

  (108) 0x212210 VMOVUPD	0x40(%R14,%RCX,1),%ZMM26

  (108) 0x212218 VMOVUPD	0x80(%R13,%RCX,1),%ZMM20

  (108) 0x212220 VMOVUPD	0x80(%R14,%RCX,1),%ZMM23

  (108) 0x212228 VBROADCASTSD	(%RBX),%ZMM17

  (108) 0x21222e VMOVAPD	%ZMM18,%ZMM21

  (108) 0x212234 VPERMT2PD	%ZMM19,%ZMM5,%ZMM21

  (108) 0x21223a VMOVAPD	%ZMM18,%ZMM22

  (108) 0x212240 VPERMT2PD	%ZMM19,%ZMM7,%ZMM22

  (108) 0x212246 VPERMT2PD	%ZMM18,%ZMM9,%ZMM19

  (108) 0x21224c VMOVUPD	(%R14,%RCX,1),%ZMM18

  (108) 0x212253 VPERMT2PD	%ZMM20,%ZMM6,%ZMM21

  (108) 0x212259 VPERMT2PD	%ZMM20,%ZMM8,%ZMM22

  (108) 0x21225f VPERMT2PD	%ZMM20,%ZMM10,%ZMM19

  (108) 0x212265 VMOVAPD	%ZMM18,%ZMM24

  (108) 0x21226b VPERMT2PD	%ZMM26,%ZMM5,%ZMM24

  (108) 0x212271 VMOVAPD	%ZMM18,%ZMM25

  (108) 0x212277 VPERMT2PD	%ZMM26,%ZMM7,%ZMM25

  (108) 0x21227d VPERMT2PD	%ZMM18,%ZMM9,%ZMM26

  (108) 0x212283 VPERMT2PD	%ZMM23,%ZMM6,%ZMM24

  (108) 0x212289 VPERMT2PD	%ZMM23,%ZMM8,%ZMM25

  (108) 0x21228f VPERMT2PD	%ZMM23,%ZMM10,%ZMM26

  (108) 0x212295 VFMADD231PD	%ZMM21,%ZMM17,%ZMM24

  (108) 0x21229b VFMADD231PD	%ZMM22,%ZMM17,%ZMM25

  (108) 0x2122a1 VFMADD231PD	%ZMM19,%ZMM17,%ZMM26

  (108) 0x2122a7 VMOVAPD	%ZMM25,%ZMM17

  (108) 0x2122ad VPERMT2PD	%ZMM24,%ZMM11,%ZMM17

  (108) 0x2122b3 VMOVAPD	%ZMM24,%ZMM18

  (108) 0x2122b9 VPERMT2PD	%ZMM25,%ZMM13,%ZMM18

  (108) 0x2122bf VPERMT2PD	%ZMM25,%ZMM15,%ZMM24

  (108) 0x2122c5 VPERMT2PD	%ZMM26,%ZMM12,%ZMM17

  (108) 0x2122cb VPERMT2PD	%ZMM26,%ZMM14,%ZMM18

  (108) 0x2122d1 VPERMT2PD	%ZMM26,%ZMM16,%ZMM24

  (108) 0x2122d7 VMOVUPD	%ZMM24,(%R14,%RCX,1)

  (108) 0x2122de VMOVUPD	%ZMM18,0x40(%R14,%RCX,1)

  (108) 0x2122e6 VMOVUPD	%ZMM17,0x80(%R14,%RCX,1)

  (108) 0x2122ee ADD	$0xc0,%RCX

  (108) 0x2122f5 CMP	%RCX,%R12

  (108) 0x2122f8 JNE	212200

(106) 0x2122fe CMP	%R9,%R8

(106) 0x212301 JE	212130

(106) 0x212307 TEST	$0x4,%R9B

(106) 0x21230b JNE	212318

(106) 0x21230d ADD	%R8,%R15

(106) 0x212310 MOV	%R8D,%R12D

(106) 0x212313 JMP	212400

(106) 0x212318 MOV	%R9D,%R12D

(106) 0x21231b AND	$-0x4,%R12D

(106) 0x21231f MOV	%R8,%RCX

(106) 0x212322 LEA	(%R12,%R15,1),%R14

(106) 0x212326 ADD	%R8,%R15

(106) 0x212329 SUB	%R12,%RCX

(106) 0x21232c SAL	$0x3,%R15

(106) 0x212330 LEA	(%R15,%R15,2),%R8

(106) 0x212334 NOPW	%CS:(%RAX,%RAX,1)

  (109) 0x212340 VMOVUPD	(%R11,%R8,1),%ZMM18

  (109) 0x212347 VMOVUPD	0x40(%R11,%R8,1),%YMM19

  (109) 0x21234f VMOVUPD	0x40(%R10,%R8,1),%YMM22

  (109) 0x212357 VBROADCASTSD	(%RBX),%YMM17

  (109) 0x21235d VMOVAPD	%ZMM18,%ZMM20

  (109) 0x212363 VMOVAPD	%ZMM18,%ZMM21

  (109) 0x212369 VPERMT2PD	%ZMM19,%ZMM0,%ZMM20

  (109) 0x21236f VPERMT2PD	%ZMM19,%ZMM1,%ZMM21

  (109) 0x212375 VPERMT2PD	%ZMM19,%ZMM2,%ZMM18

  (109) 0x21237b VMOVUPD	(%R10,%R8,1),%ZMM19

  (109) 0x212382 VMOVAPD	%ZMM19,%ZMM23

  (109) 0x212388 VPERMT2PD	%ZMM22,%ZMM0,%ZMM23

  (109) 0x21238e VMOVAPD	%ZMM19,%ZMM24

  (109) 0x212394 VPERMT2PD	%ZMM22,%ZMM1,%ZMM24

  (109) 0x21239a VPERMT2PD	%ZMM22,%ZMM2,%ZMM19

  (109) 0x2123a0 VFMADD231PD	%YMM20,%YMM17,%YMM23

  (109) 0x2123a6 VFMADD231PD	%YMM21,%YMM17,%YMM24

  (109) 0x2123ac VFMADD231PD	%YMM18,%YMM17,%YMM19

  (109) 0x2123b2 VINSERTF64X4	$0x1,%YMM24,%ZMM23,%ZMM17

  (109) 0x2123b9 VMOVAPD	%ZMM17,%ZMM18

  (109) 0x2123bf VPERMT2PD	%ZMM19,%ZMM3,%ZMM18

  (109) 0x2123c5 VPERMT2PD	%ZMM19,%ZMM4,%ZMM17

  (109) 0x2123cb VMOVUPD	%ZMM17,(%R10,%R8,1)

  (109) 0x2123d2 VMOVUPD	%YMM18,0x40(%R10,%R8,1)

  (109) 0x2123da ADD	$0x60,%R8

  (109) 0x2123de ADD	$0x4,%RCX

  (109) 0x2123e2 JNE	212340

(106) 0x2123e8 MOV	%R14,%R15

(106) 0x2123eb CMP	%R9,%R12

(106) 0x2123ee JE	212130

(106) 0x2123f4 NOPW	%CS:(%RAX,%RAX,1)

(106) 0x212400 LEA	(%R15,%R15,2),%RCX

(106) 0x212404 SUB	%R12D,%R9D

(106) 0x212407 LEA	0x10(,%RCX,8),%RCX

(106) 0x21240f NOP

  (107) 0x212410 VMOVSD	(%RBX),%XMM17

  (107) 0x212416 VMOVSD	-0x10(%R11,%RCX,1),%XMM18

  (107) 0x21241e VFMADD213SD	-0x10(%R10,%RCX,1),%XMM17,%XMM18

  (107) 0x212426 VMOVSD	%XMM18,-0x10(%R10,%RCX,1)

  (107) 0x21242e VMOVSD	(%RBX),%XMM17

  (107) 0x212434 VMOVSD	-0x8(%R11,%RCX,1),%XMM18

  (107) 0x21243c VFMADD213SD	-0x8(%R10,%RCX,1),%XMM17,%XMM18

  (107) 0x212444 VMOVSD	%XMM18,-0x8(%R10,%RCX,1)

  (107) 0x21244c VMOVSD	(%RBX),%XMM17

  (107) 0x212452 VMOVSD	(%R11,%RCX,1),%XMM18

  (107) 0x212459 VFMADD213SD	(%R10,%RCX,1),%XMM17,%XMM18

  (107) 0x212460 VMOVSD	%XMM18,(%R10,%RCX,1)

  (107) 0x212467 ADD	$0x18,%RCX

  (107) 0x21246b DEC	%R9D

  (107) 0x21246e JNE	212410

(106) 0x212470 JMP	212130

0x212475 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.05% of application time for run orig_0

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.38 to 4.50 cycles (2.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 44% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 10.38 to 7.92 cycles (1.31x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1004 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	82
nb uops	83
loop length	395
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	4
used zmm registers	13
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.38 cycles
front end	10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.50	4.50	4.50	4.50	4.50	4.50	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.50	4.50	4.50	4.50	4.50	4.50	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.38
Dispatch	9.25
Overall L1	10.38

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	47%
load	85%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	8%
load	6%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	88%
load	88%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	44%
load	75%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.38 cycles. At this rate:

37% of peak load performance is reached (96.77 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.38 to 9.25 cycles (1.12x speedup).

ASM code

In the binary file, the address of the function is: 211fb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R14D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 212047 <advanceVelocity.omp_outlined+0x97>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DEC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0x1,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x3c(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x22dc(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 212de0 <@plt_start@+0x180>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVL %EAX,%R14D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOVSXD -0x30(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 212056 <advanceVelocity.omp_outlined+0xa6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
LEA 0x22b1(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 212df0 <@plt_start@+0x190>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV (%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVAPD -0xcee1(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xcea9(%RIP),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xcf11(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xcf39(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xc503(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc80d(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc7d7(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc7a1(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc76b(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc735(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc6ff(%RIP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc6c9(%RIP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc693(%RIP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc65d(%RIP),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc627(%RIP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc5f1(%RIP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc5bb(%RIP),%ZMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOV 0x18(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x78(%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSXD %R14D,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA 0x8(%RBX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 212144 <advanceVelocity.omp_outlined+0x194>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.05% of application time for run orig_0

Source file and lines	timestep.c:71-78
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.38 to 4.50 cycles (2.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1004 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	82
nb uops	83
loop length	395
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	4
used zmm registers	13
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.38 cycles
front end	10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.50	4.50	4.50	4.50	4.50	4.50	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.50	4.50	4.50	4.50	4.50	4.50	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.38
Dispatch	9.25
Overall L1	10.38

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	47%
load	85%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	8%
load	6%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	88%
load	88%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	44%
load	75%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.38 cycles. At this rate:

37% of peak load performance is reached (96.77 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 211fb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R14D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 212047 <advanceVelocity.omp_outlined+0x97>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DEC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0x1,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x3c(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x22dc(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 212de0 <@plt_start@+0x180>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVL %EAX,%R14D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOVSXD -0x30(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 212056 <advanceVelocity.omp_outlined+0xa6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
LEA 0x22b1(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 212df0 <@plt_start@+0x190>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV (%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVAPD -0xcee1(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xcea9(%RIP),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xcf11(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xcf39(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xc503(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc80d(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc7d7(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc7a1(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc76b(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc735(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc6ff(%RIP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc6c9(%RIP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc693(%RIP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc65d(%RIP),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc627(%RIP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc5f1(%RIP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc5bb(%RIP),%ZMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOV 0x18(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x78(%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSXD %R14D,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA 0x8(%RBX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 212144 <advanceVelocity.omp_outlined+0x194>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

Name	Coverage (%)	Time (s)
▼advanceVelocity.omp_outlined–	1.31	0.10
▼Loop 106 - timestep.c:72-78 - exec–	0.00	0.01
○Loop 108 - timestep.c:74-78 - exec	1.04	0.08
○Loop 107 - timestep.c:74-78 - exec	0.14	0.02
○Loop 109 - timestep.c:74-78 - exec	0.09	0.02

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