OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:211-385 [...]	Coverage (incl. loops): 0.25% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 211 - 385

--------------------------------------------------------------------------------

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

[...]

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

[...]

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

372:    {

373:       if (iz == gridSize[2]) iz = gridSize[2] - 1;

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x20eb40 PUSH	%RBP

0x20eb41 MOV	%RSP,%RBP

0x20eb44 PUSH	%R15

0x20eb46 PUSH	%R14

0x20eb48 PUSH	%R13

0x20eb4a PUSH	%R12

0x20eb4c PUSH	%RBX

0x20eb4d SUB	$0x18,%RSP

0x20eb51 MOV	0xc(%RDI),%R8D

0x20eb55 CMP	%R8D,0x14(%RDI)

0x20eb59 JLE	20eb87

0x20eb5b MOV	0x78(%RDI),%RCX

0x20eb5f MOVSXD	%R8D,%RAX

0x20eb62 NOPW	%CS:(%RAX,%RAX,1)

(91) 0x20eb70 MOVL	$0,(%RCX,%RAX,4)

(91) 0x20eb77 INC	%RAX

(91) 0x20eb7a MOVSXD	0x14(%RDI),%RDX

(91) 0x20eb7e CMP	%RDX,%RAX

(91) 0x20eb81 JL	20eb70

0x20eb83 MOV	0xc(%RDI),%R8D

0x20eb87 TEST	%R8D,%R8D

0x20eb8a JLE	20ef2c

0x20eb90 MOV	0x78(%RDI),%R10

0x20eb94 XOR	%EAX,%EAX

0x20eb96 JMP	20ebaf

0x20eb98 NOPL	(%RAX,%RAX,1)

(89) 0x20eba0 INC	%RAX

(89) 0x20eba3 MOVSXD	%R8D,%RCX

(89) 0x20eba6 CMP	%RCX,%RAX

(89) 0x20eba9 JGE	20ef2c

(89) 0x20ebaf CMPL	$0,(%R10,%RAX,4)

(89) 0x20ebb4 JLE	20eba0

(89) 0x20ebb6 MOVSXD	%EAX,%RCX

(89) 0x20ebb9 XOR	%EDX,%EDX

(89) 0x20ebbb SAL	$0x6,%RCX

(89) 0x20ebbf MOV	%RCX,-0x38(%RBP)

(89) 0x20ebc3 JMP	20ebe0

0x20ebc5 NOPW	%CS:(%RAX,%RAX,1)

  (90) 0x20ebd0 MOV	-0x30(%RBP),%RDX

  (90) 0x20ebd4 INC	%EDX

  (90) 0x20ebd6 MOV	0x78(%RDI),%R10

  (90) 0x20ebda CMP	%EDX,(%R10,%RAX,4)

  (90) 0x20ebde JLE	20eba0

  (90) 0x20ebe0 MOV	-0x38(%RBP),%RCX

  (90) 0x20ebe4 MOV	0x18(%RSI),%R11

  (90) 0x20ebe8 VMOVSD	0x30(%RDI),%XMM1

  (90) 0x20ebed ADD	%EDX,%ECX

  (90) 0x20ebef MOVSXD	%ECX,%R9

  (90) 0x20ebf2 LEA	(%R9,%R9,2),%RBX

  (90) 0x20ebf6 VMOVSD	(%R11,%RBX,8),%XMM0

  (90) 0x20ebfc VUCOMISD	%XMM0,%XMM1

  (90) 0x20ec00 JBE	20ec30

  (90) 0x20ec02 VSUBSD	0x18(%RDI),%XMM0,%XMM0

  (90) 0x20ec07 MOV	(%RDI),%R12D

  (90) 0x20ec0a VMULSD	0x60(%RDI),%XMM0,%XMM0

  (90) 0x20ec0f VROUNDSD	$0x9,%XMM0,%XMM0,%XMM0

  (90) 0x20ec15 VCVTTSD2SI	%XMM0,%R15D

  (90) 0x20ec19 CMP	%R15D,%R12D

  (90) 0x20ec1c JNE	20ec36

  (90) 0x20ec1e LEA	-0x1(%R12),%R15D

  (90) 0x20ec23 JMP	20ec36

0x20ec25 NOPW	%CS:(%RAX,%RAX,1)

  (90) 0x20ec30 MOV	(%RDI),%R12D

  (90) 0x20ec33 MOV	%R12D,%R15D

  (90) 0x20ec36 VMOVSD	0x8(%R11,%RBX,8),%XMM0

  (90) 0x20ec3d MOV	0x4(%RDI),%R13D

  (90) 0x20ec41 VSUBSD	0x20(%RDI),%XMM0,%XMM1

  (90) 0x20ec46 VMULSD	0x68(%RDI),%XMM1,%XMM1

  (90) 0x20ec4b VROUNDSD	$0x9,%XMM1,%XMM1,%XMM1

  (90) 0x20ec51 VCVTTSD2SI	%XMM1,%R14D

  (90) 0x20ec55 CMP	%R14D,%R13D

  (90) 0x20ec58 JNE	20ec5e

  (90) 0x20ec5a LEA	-0x1(%R13),%R14D

  (90) 0x20ec5e VMOVSD	0x38(%RDI),%XMM1

  (90) 0x20ec63 VMOVSD	0x10(%R11,%RBX,8),%XMM2

  (90) 0x20ec6a VMOVSD	0x40(%RDI),%XMM3

  (90) 0x20ec6f MOV	0x8(%RDI),%ECX

  (90) 0x20ec72 MOV	%RDX,-0x30(%RBP)

  (90) 0x20ec76 VUCOMISD	%XMM0,%XMM1

  (90) 0x20ec7a CMOVBE	%R13D,%R14D

  (90) 0x20ec7e VUCOMISD	%XMM2,%XMM3

  (90) 0x20ec82 JBE	20ece0

  (90) 0x20ec84 VSUBSD	0x28(%RDI),%XMM2,%XMM2

  (90) 0x20ec89 VMULSD	0x70(%RDI),%XMM2,%XMM2

  (90) 0x20ec8e VROUNDSD	$0x9,%XMM2,%XMM2,%XMM2

  (90) 0x20ec94 VCVTTSD2SI	%XMM2,%EDX

  (90) 0x20ec98 CMP	%EDX,%ECX

  (90) 0x20ec9a JNE	20ec9f

  (90) 0x20ec9c LEA	-0x1(%RCX),%EDX

  (90) 0x20ec9f CMP	$-0x1,%EDX

  (90) 0x20eca2 JE	20ed11

  (90) 0x20eca4 VUCOMISD	%XMM0,%XMM1

  (90) 0x20eca8 JA	20ed3a

  (90) 0x20ecae IMUL	%ECX,%R13D

  (90) 0x20ecb2 ADD	%ECX,%EDX

  (90) 0x20ecb4 ADD	$0x2,%R12D

  (90) 0x20ecb8 IMUL	%R12D,%EDX

  (90) 0x20ecbc LEA	(%R15,%R13,2),%ECX

  (90) 0x20ecc0 ADD	%R8D,%ECX

  (90) 0x20ecc3 LEA	0x1(%RDX,%RCX,1),%R14D

  (90) 0x20ecc8 TEST	%R14D,%R14D

  (90) 0x20eccb JNS	20edb0

0x20ecd1 JMP	20ef3b

0x20ecd6 NOPW	%CS:(%RAX,%RAX,1)

  (90) 0x20ece0 LEA	(%RCX,%RCX,1),%EDX

  (90) 0x20ece3 LEA	(%R14,%RCX,2),%ECX

  (90) 0x20ece7 ADD	$0x2,%R12D

  (90) 0x20eceb ADD	%R8D,%R15D

  (90) 0x20ecee IMUL	%R13D,%EDX

  (90) 0x20ecf2 LEA	0x3(%R13,%RCX,1),%ECX

  (90) 0x20ecf7 IMUL	%R12D,%ECX

  (90) 0x20ecfb ADD	%EDX,%R15D

  (90) 0x20ecfe LEA	0x1(%RCX,%R15,1),%R14D

  (90) 0x20ed03 TEST	%R14D,%R14D

  (90) 0x20ed06 JNS	20edb0

0x20ed0c JMP	20ef3b

  (90) 0x20ed11 LEA	(%RCX,%RCX,1),%EDX

  (90) 0x20ed14 LEA	0x1(%R14,%RCX,2),%ECX

  (90) 0x20ed19 ADD	$0x2,%R12D

  (90) 0x20ed1d ADD	%R8D,%R15D

  (90) 0x20ed20 IMUL	%EDX,%R13D

  (90) 0x20ed24 IMUL	%R12D,%ECX

  (90) 0x20ed28 ADD	%R13D,%R15D

  (90) 0x20ed2b LEA	0x1(%RCX,%R15,1),%R14D

  (90) 0x20ed30 TEST	%R14D,%R14D

  (90) 0x20ed33 JNS	20edb0

0x20ed35 JMP	20ef3b

  (90) 0x20ed3a CMP	$-0x1,%R14D

  (90) 0x20ed3e JE	20ed5b

  (90) 0x20ed40 CMP	%R15D,%R12D

  (90) 0x20ed43 JNE	20ed7d

  (90) 0x20ed45 ADD	%EDX,%ECX

  (90) 0x20ed47 ADD	%R8D,%R14D

  (90) 0x20ed4a IMUL	%ECX,%R13D

  (90) 0x20ed4e ADD	%R13D,%R14D

  (90) 0x20ed51 TEST	%R14D,%R14D

  (90) 0x20ed54 JNS	20edb0

0x20ed56 JMP	20ef3b

  (90) 0x20ed5b IMUL	%R13D,%ECX

  (90) 0x20ed5f ADD	$0x2,%R12D

  (90) 0x20ed63 IMUL	%EDX,%R12D

  (90) 0x20ed67 LEA	(%R15,%RCX,2),%ECX

  (90) 0x20ed6b ADD	%R8D,%ECX

  (90) 0x20ed6e LEA	0x1(%R12,%RCX,1),%R14D

  (90) 0x20ed73 TEST	%R14D,%R14D

  (90) 0x20ed76 JNS	20edb0

0x20ed78 JMP	20ef3b

  (90) 0x20ed7d IMUL	%EDX,%R13D

  (90) 0x20ed81 ADD	%R14D,%R13D

  (90) 0x20ed84 CMP	$-0x1,%R15D

  (90) 0x20ed88 JE	20ed9e

  (90) 0x20ed8a IMUL	%R13D,%R12D

  (90) 0x20ed8e ADD	%R15D,%R12D

  (90) 0x20ed91 MOV	%R12D,%R14D

  (90) 0x20ed94 TEST	%R14D,%R14D

  (90) 0x20ed97 JNS	20edb0

0x20ed99 JMP	20ef3b

  (90) 0x20ed9e ADD	%R8D,%R13D

  (90) 0x20eda1 MOV	%R13D,%R14D

  (90) 0x20eda4 TEST	%R14D,%R14D

  (90) 0x20eda7 JS	20ef3b

  (90) 0x20edad NOPL	(%RAX)

  (90) 0x20edb0 CMP	%R14D,0x14(%RDI)

  (90) 0x20edb4 JLE	20ef5a

  (90) 0x20edba MOV	%R14D,%EDX

  (90) 0x20edbd CMP	%RDX,%RAX

  (90) 0x20edc0 JE	20ebd0

  (90) 0x20edc6 MOV	0x8(%RSI),%R15

  (90) 0x20edca MOVSXD	(%R10,%RDX,4),%R10

  (90) 0x20edce LEA	(%R11,%RBX,8),%RCX

  (90) 0x20edd2 MOVSXD	%R14D,%R8

  (90) 0x20edd5 SAL	$0x6,%R8

  (90) 0x20edd9 MOV	(%R15,%R9,4),%EBX

  (90) 0x20eddd ADD	%R10,%R8

  (90) 0x20ede0 MOV	%EBX,(%R15,%R8,4)

  (90) 0x20ede4 MOV	0x10(%RSI),%R10

  (90) 0x20ede8 MOV	(%R10,%R9,4),%EBX

  (90) 0x20edec MOV	%EBX,(%R10,%R8,4)

  (90) 0x20edf0 LEA	(,%R8,8),%R10

  (90) 0x20edf8 MOV	0x10(%RCX),%RBX

  (90) 0x20edfc LEA	(%R10,%R10,2),%R10

  (90) 0x20ee00 MOV	%RBX,0x10(%R11,%R10,1)

  (90) 0x20ee05 VMOVUPS	(%RCX),%XMM0

  (90) 0x20ee09 LEA	(,%R9,8),%RCX

  (90) 0x20ee11 LEA	(%RCX,%RCX,2),%RCX

  (90) 0x20ee15 VMOVUPS	%XMM0,(%R11,%R10,1)

  (90) 0x20ee1b MOV	0x20(%RSI),%R11

  (90) 0x20ee1f MOV	0x10(%R11,%RCX,1),%RBX

  (90) 0x20ee24 MOV	%RBX,0x10(%R11,%R10,1)

  (90) 0x20ee29 VMOVUPS	(%R11,%RCX,1),%XMM0

  (90) 0x20ee2f VMOVUPS	%XMM0,(%R11,%R10,1)

  (90) 0x20ee35 MOV	0x28(%RSI),%R11

  (90) 0x20ee39 MOV	0x10(%R11,%RCX,1),%RBX

  (90) 0x20ee3e MOV	%RBX,0x10(%R11,%R10,1)

  (90) 0x20ee43 VMOVUPD	(%R11,%RCX,1),%XMM0

  (90) 0x20ee49 VMOVUPD	%XMM0,(%R11,%R10,1)

  (90) 0x20ee4f MOV	0x30(%RSI),%R10

  (90) 0x20ee53 MOV	(%R10,%R9,8),%R11

  (90) 0x20ee57 MOV	%R11,(%R10,%R8,8)

  (90) 0x20ee5b MOV	0x78(%RDI),%R8

  (90) 0x20ee5f MOV	(%R8,%RDX,4),%R10D

  (90) 0x20ee63 LEA	0x1(%R10),%R11D

  (90) 0x20ee67 MOV	%R11D,(%R8,%RDX,4)

  (90) 0x20ee6b CMP	$0x3f,%R10D

  (90) 0x20ee6f JGE	20ef79

  (90) 0x20ee75 MOVSXD	(%R8,%RAX,4),%RDX

  (90) 0x20ee79 DEC	%RDX

  (90) 0x20ee7c MOV	%EDX,(%R8,%RAX,4)

  (90) 0x20ee80 TEST	%EDX,%EDX

  (90) 0x20ee82 JE	20ef0a

  (90) 0x20ee88 ADD	-0x38(%RBP),%RDX

  (90) 0x20ee8c MOV	0x8(%RSI),%R8

  (90) 0x20ee90 MOV	(%R8,%RDX,4),%R10D

  (90) 0x20ee94 MOV	%R10D,(%R8,%R9,4)

  (90) 0x20ee98 MOV	0x10(%RSI),%R8

  (90) 0x20ee9c MOV	(%R8,%RDX,4),%R10D

  (90) 0x20eea0 MOV	%R10D,(%R8,%R9,4)

  (90) 0x20eea4 LEA	(,%RDX,8),%R10

  (90) 0x20eeac MOV	0x18(%RSI),%R8

  (90) 0x20eeb0 LEA	(%R10,%R10,2),%R10

  (90) 0x20eeb4 MOV	0x10(%R8,%R10,1),%R11

  (90) 0x20eeb9 MOV	%R11,0x10(%R8,%RCX,1)

  (90) 0x20eebe VMOVUPS	(%R8,%R10,1),%XMM0

  (90) 0x20eec4 VMOVUPS	%XMM0,(%R8,%RCX,1)

  (90) 0x20eeca MOV	0x20(%RSI),%R8

  (90) 0x20eece MOV	0x10(%R8,%R10,1),%R11

  (90) 0x20eed3 MOV	%R11,0x10(%R8,%RCX,1)

  (90) 0x20eed8 VMOVUPS	(%R8,%R10,1),%XMM0

  (90) 0x20eede VMOVUPS	%XMM0,(%R8,%RCX,1)

  (90) 0x20eee4 MOV	0x28(%RSI),%R8

  (90) 0x20eee8 MOV	0x10(%R8,%R10,1),%R11

  (90) 0x20eeed MOV	%R11,0x10(%R8,%RCX,1)

  (90) 0x20eef2 VMOVUPD	(%R8,%R10,1),%XMM0

  (90) 0x20eef8 VMOVUPD	%XMM0,(%R8,%RCX,1)

  (90) 0x20eefe MOV	0x30(%RSI),%RCX

  (90) 0x20ef02 MOV	(%RCX,%RDX,8),%RDX

  (90) 0x20ef06 MOV	%RDX,(%RCX,%R9,8)

  (90) 0x20ef0a MOV	0xc(%RDI),%R8D

  (90) 0x20ef0e CMP	%R14D,%R8D

  (90) 0x20ef11 JGE	20ef15

  (90) 0x20ef13 DECL	(%RSI)

  (90) 0x20ef15 MOV	-0x30(%RBP),%RDX

  (90) 0x20ef19 MOV	0x78(%RDI),%R10

  (90) 0x20ef1d CMP	(%R10,%RAX,4),%EDX

  (90) 0x20ef21 JL	20ebe0

(89) 0x20ef27 JMP	20eba0

0x20ef2c ADD	$0x18,%RSP

0x20ef30 POP	%RBX

0x20ef31 POP	%R12

0x20ef33 POP	%R13

0x20ef35 POP	%R14

0x20ef37 POP	%R15

0x20ef39 POP	%RBP

0x20ef3a RET

0x20ef3b LEA	-0xa0c1(%RIP),%RDI

0x20ef42 LEA	-0xc7d8(%RIP),%RSI

0x20ef49 LEA	-0xa27d(%RIP),%RCX

0x20ef50 MOV	$0xf6,%EDX

0x20ef55 CALL	212d40 <@plt_start@+0xe0>

0x20ef5a LEA	-0xbace(%RIP),%RDI

0x20ef61 LEA	-0xc7f7(%RIP),%RSI

0x20ef68 LEA	-0xa29c(%RIP),%RCX

0x20ef6f MOV	$0xf7,%EDX

0x20ef74 CALL	212d40 <@plt_start@+0xe0>

0x20ef79 LEA	-0xc1c9(%RIP),%RDI

0x20ef80 LEA	-0xc816(%RIP),%RSI

0x20ef87 LEA	-0xcde0(%RIP),%RCX

0x20ef8e MOV	$0x106,%EDX

0x20ef93 CALL	212d40 <@plt_start@+0xe0>

0x20ef98 NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►84.20+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►15.09+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	linkCells.c:211-385
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-247,258-269,288-304,327-334,352,359-365,371-373,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.38 to 0.41 cycles (15.43x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes.

General properties

nb instructions	54
nb uops	51
loop length	255
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.00	5.00	5.00	5.00	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.00	5.00	5.00	5.00	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Dispatch	5.00
Overall L1	6.38

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	8%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.38 cycles. At this rate:

1% of peak load performance is reached (4.39 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.38 to 5.00 cycles (1.27x speedup).

ASM code

In the binary file, the address of the function is: 20eb40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0xc(%RDI),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
CMP %R8D,0x14(%RDI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JLE 20eb87 <updateLinkCells+0x47>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOVSXD %R8D,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0xc(%RDI),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 20ef2c <updateLinkCells+0x3ec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 20ebaf <updateLinkCells+0x6f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 20ef3b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 20ef3b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
JMP 20ef3b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
JMP 20ef3b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
JMP 20ef3b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
JMP 20ef3b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
LEA -0xa0c1(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0xc7d8(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0xa27d(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 212d40 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA -0xbace(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0xc7f7(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0xa29c(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 212d40 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA -0xc1c9(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0xc816(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0xcde0(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x106,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 212d40 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	linkCells.c:211-385
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-374-1600/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes.

General properties

nb instructions	54
nb uops	51
loop length	255
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.00	5.00	5.00	5.00	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.00	5.00	5.00	5.00	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Dispatch	5.00
Overall L1	6.38

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	8%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.38 cycles. At this rate:

1% of peak load performance is reached (4.39 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 20eb40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0xc(%RDI),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
CMP %R8D,0x14(%RDI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JLE 20eb87 <updateLinkCells+0x47>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOVSXD %R8D,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0xc(%RDI),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 20ef2c <updateLinkCells+0x3ec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV 0x78(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 20ebaf <updateLinkCells+0x6f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 20ef3b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 20ef3b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
JMP 20ef3b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
JMP 20ef3b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
JMP 20ef3b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
JMP 20ef3b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
LEA -0xa0c1(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0xc7d8(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0xa27d(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 212d40 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA -0xbace(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0xc7f7(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0xa29c(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 212d40 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA -0xc1c9(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0xc816(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0xcde0(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x106,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 212d40 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.25	0.02
▼Loop 89 - linkCells.c:211-373 - exec–	0.00	0.00
○Loop 90 - linkCells.c:211-373 - exec	0.25	1.77
○Loop 91 - linkCells.c:384-385 - exec	0.00	0.00

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Vectorization

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CALL instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code