OV - exec - Loop 43

	Loop Id: 43	Module: exec	Source: haloExchange.c:380-389	Coverage: 0.06%

0x407320 MOV	(%R11,%R12,4),%ESI    [2]

0x407324 MOV	%ESI,(%R13)    [3]

0x407328 MOV	(%RBX,%R12,4),%ESI    [6]

0x40732c MOV	%ESI,0x4(%R13)    [3]

0x407330 VADDPD	-0x10(%R14,%RAX,4),%XMM0,%XMM2    [4]

0x407337 VMOVUPD	%XMM2,0x8(%R13)    [3]

0x40733d VADDSD	(%R14,%RAX,4),%XMM1,%XMM2    [4]

0x407343 VMOVSD	%XMM2,0x18(%R13)    [3]

0x407349 VMOVUPS	-0x10(%R15,%RAX,4),%XMM2    [5]

0x407350 VMOVUPS	%XMM2,0x20(%R13)    [3]

0x407356 VMOVSD	(%R15,%RAX,4),%XMM2    [5]

0x40735c VMOVSD	%XMM2,0x30(%R13)    [3]

0x407362 INC	%R12

0x407365 MOVSXD	(%R8,%R10,4),%RSI    [1]

0x407369 ADD	%RCX,%RSI

0x40736c ADD	$0x38,%R13

0x407370 INC	%EDI

0x407372 ADD	$0x6,%RAX

0x407376 CMP	%RSI,%R12

0x407379 JL	407320

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 380 - 389

--------------------------------------------------------------------------------

380:       for (int ii=iOff; ii<iOff+s->boxes->nAtoms[iBox]; ++ii)

381:       {

382:          buf[nBuf].gid  = s->atoms->gid[ii];

383:          buf[nBuf].type = s->atoms->iSpecies[ii];

384:          buf[nBuf].rx = s->atoms->r[ii][0] + shift[0];

385:          buf[nBuf].ry = s->atoms->r[ii][1] + shift[1];

386:          buf[nBuf].rz = s->atoms->r[ii][2] + shift[2];

387:          buf[nBuf].px = s->atoms->p[ii][0];

388:          buf[nBuf].py = s->atoms->p[ii][1];

389:          buf[nBuf].pz = s->atoms->p[ii][2];

Coverage (%)	Name	Source Location	Module
►18.04+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►14.70+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►14.70+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►14.25+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►14.03+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►12.92+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►2.90+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►2.00+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►1.78+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►1.78+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►1.56+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec

Coverage (%)	Name	Source Location	Module
►16.19+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►12.70+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►12.50+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►12.30+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►12.29+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►11.89+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►3.89+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►3.08+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►3.07+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►2.87+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►2.46+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►2.25+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

Coverage (%)	Name	Source Location	Module
►15.48+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►13.12+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►13.12+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►11.18+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►11.18+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►10.54+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►6.67+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►4.73+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►4.52+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►3.01+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►2.58+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►2.37+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

Coverage (%)	Name	Source Location	Module
►13.87+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►13.64+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►12.75+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►12.53+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►12.30+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►11.64+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►4.48+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►4.47+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►3.80+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►3.80+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►3.13+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►2.46+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

Coverage (%)	Name	Source Location	Module
►16.11+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►14.54+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►12.53+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►11.41+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►10.74+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►10.07+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►4.47+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►4.47+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►4.03+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►4.03+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►3.58+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►3.13+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

Coverage (%)	Name	Source Location	Module
►15.23+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►12.14+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►11.48+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►10.16+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►10.15+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►9.05+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►6.18+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►5.30+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►5.30+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►4.86+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►4.86+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►4.64+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

Coverage (%)	Name	Source Location	Module
►15.32+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►12.98+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►12.34+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►11.91+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►10.64+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►9.36+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►5.74+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►4.89+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►4.47+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►3.83+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►3.83+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►3.40+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.44
CQA speedup if FP arith vectorized	1.25
CQA speedup if fully vectorized	7.17
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.37
Bottlenecks	P6, P7, P8, P9,
Function	loadAtomsBuffer
Source	haloExchange.c:380-389
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.25
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	2.59
CQA cycles if fully vectorized	0.45
Front-end cycles	2.38
P0 cycles	1.17
P1 cycles	1.17
P2 cycles	1.17
P3 cycles	1.17
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	3.25
P7 cycles	3.25
P8 cycles	3.25
P9 cycles	3.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	19.00
Nb loads	7.00
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.92
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	35.69
Bytes prefetched	0.00
Bytes loaded	60.00
Bytes stored	56.00
Stride 0	1.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	36.36
Vectorization ratio load	50.00
Vectorization ratio store	33.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	33.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	15.34
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	14.58
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	14.58
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.44
CQA speedup if FP arith vectorized	1.25
CQA speedup if fully vectorized	7.17
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.37
Bottlenecks	P6, P7, P8, P9,
Function	loadAtomsBuffer
Source	haloExchange.c:380-389
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.25
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	2.59
CQA cycles if fully vectorized	0.45
Front-end cycles	2.38
P0 cycles	1.17
P1 cycles	1.17
P2 cycles	1.17
P3 cycles	1.17
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	3.25
P7 cycles	3.25
P8 cycles	3.25
P9 cycles	3.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	19.00
Nb loads	7.00
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.92
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	35.69
Bytes prefetched	0.00
Bytes loaded	60.00
Bytes stored	56.00
Stride 0	1.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	36.36
Vectorization ratio load	50.00
Vectorization ratio store	33.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	33.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	15.34
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	14.58
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	14.58
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	loadAtomsBuffer
Source file and lines	haloExchange.c:380-389
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:380-389.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.25 to 2.25 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 3.25 to 0.45 cycles (7.17x speedup).

Details

36% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 3.25 to 2.38 cycles (1.37x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary loop is loading 60 bytes (7 double precision FP elements). The binary loop is storing 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	20
nb uops	19
loop length	91
used x86 registers	12
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.38 cycles
front end	2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.17	1.17	1.17	1.17	1.17	1.17	3.25	3.25	3.25	3.25	0.00	0.00	1.00	1.00	2.00	2.00
cycles	1.17	1.17	1.17	1.17	1.17	1.17	3.25	3.25	3.25	3.25	0.00	0.00	1.00	1.00	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.38
Dispatch	3.25
Data deps.	1.00
Overall L1	3.25

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	36%
load	50%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	18%
load	18%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	15%
load	18%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.25 cycles. At this rate:

7% of peak load performance is reached (18.46 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (17.23 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 407320

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV (%R11,%R12,4),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %ESI,(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RBX,%R12,4),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %ESI,0x4(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
VADDPD -0x10(%R14,%RAX,4),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVUPD %XMM2,0x8(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VADDSD (%R14,%RAX,4),%XMM1,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM2,0x18(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPS -0x10(%R15,%RAX,4),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPS %XMM2,0x20(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSD (%R15,%RAX,4),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,0x30(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD (%R8,%R10,4),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x38,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x6,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JL 407320 <loadAtomsBuffer+0xc0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	loadAtomsBuffer
Source file and lines	haloExchange.c:380-389
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.25 to 2.25 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

36% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 3.25 to 2.38 cycles (1.37x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary loop is loading 60 bytes (7 double precision FP elements). The binary loop is storing 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	20
nb uops	19
loop length	91
used x86 registers	12
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.38 cycles
front end	2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.17	1.17	1.17	1.17	1.17	1.17	3.25	3.25	3.25	3.25	0.00	0.00	1.00	1.00	2.00	2.00
cycles	1.17	1.17	1.17	1.17	1.17	1.17	3.25	3.25	3.25	3.25	0.00	0.00	1.00	1.00	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.38
Dispatch	3.25
Data deps.	1.00
Overall L1	3.25

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	36%
load	50%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	18%
load	18%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	15%
load	18%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.25 cycles. At this rate:

7% of peak load performance is reached (18.46 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (17.23 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 407320

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV (%R11,%R12,4),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %ESI,(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RBX,%R12,4),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %ESI,0x4(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
VADDPD -0x10(%R14,%RAX,4),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVUPD %XMM2,0x8(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VADDSD (%R14,%RAX,4),%XMM1,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM2,0x18(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPS -0x10(%R15,%RAX,4),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPS %XMM2,0x20(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSD (%R15,%RAX,4),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,0x30(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD (%R8,%R10,4),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x38,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x6,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JL 407320 <loadAtomsBuffer+0xc0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

▶Scalability Runs Description

Run 8x1	Number processes: 8Number nodes: 1Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/run/oneview_runs/multicore/icx/oneview_run_1740438801OMP_NUM_THREADS: 1I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x12	Number processes: 8Number nodes: 1Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/run/oneview_runs/multicore/icx/oneview_run_1740438801OMP_NUM_THREADS: 12I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x16	Number processes: 8Number nodes: 1Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/run/oneview_runs/multicore/icx/oneview_run_1740438801OMP_NUM_THREADS: 16I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x20	Number processes: 8Number nodes: 1Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/run/oneview_runs/multicore/icx/oneview_run_1740438801OMP_NUM_THREADS: 20I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x24	Number processes: 8Number nodes: 1Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/run/oneview_runs/multicore/icx/oneview_run_1740438801OMP_NUM_THREADS: 24I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x28	Number processes: 8Number nodes: 1Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/run/oneview_runs/multicore/icx/oneview_run_1740438801OMP_NUM_THREADS: 28I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x32	Number processes: 8Number nodes: 1Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/run/oneview_runs/multicore/icx/oneview_run_1740438801OMP_NUM_THREADS: 32I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads

(8x1) Efficiency	(8x1) Potential Speed-Up (%)	(8x12) Efficiency	(8x12) Potential Speed-Up (%)	(8x16) Efficiency	(8x16) Potential Speed-Up (%)	(8x20) Efficiency	(8x20) Potential Speed-Up (%)	(8x24) Efficiency	(8x24) Potential Speed-Up (%)	(8x28) Efficiency	(8x28) Potential Speed-Up (%)	(8x32) Efficiency	(8x32) Potential Speed-Up (%)
1	0	0.92	0	0.96	0	1	-0	1	-0	0.99	0	0.95	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
8x1	8	1	1	1	0.33999991416931	0.056320089846849
8x12	8	0.92	11.02	12	0.35999992489815	0.051404427736998
8x16	8	0.96	15.42	16	0.34999996423721	0.046977315098047
8x20	8	1	20.04	20	0.32500004768372	0.040103081613779
8x24	8	1	24.03	24	0.31000000238419	0.037841469049454
8x28	8	0.99	27.66	28	0.32000002264977	0.03532761707902
8x32	8	0.95	30.49	32	0.32999992370605	0.033933352679014

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency