OV - exec - Loop 103

	Loop Id: 103	Module: exec	Source: timestep.c:85-94	Coverage: 0.47%

0x40fd2e XOR	%R14D,%R14D

0x40fd31 MOV	0x30(%RSP),%RDX

0x40fd36 VPBROADCASTD	%R14D,%YMM26

0x40fd3c VPSUBD	%YMM26,%YMM25,%YMM25

0x40fd42 VMOVDQU	0x14656(%RIP),%YMM2

0x40fd4a VPCMPNLEUD	%YMM2,%YMM25,%K1

0x40fd51 MOVSXD	%R14D,%RAX

0x40fd54 ADD	%R15,%RAX

0x40fd57 VMOVDQU32	(%R10,%RAX,4),%YMM25{%K1}{z}

0x40fd5e VMOVDQA32	%YMM25,%YMM23{%K1}

0x40fd64 VPMOVSXDQ	%YMM23,%ZMM25

0x40fd6a VPSLLQ	$0x4,%ZMM25,%ZMM25

0x40fd71 VPADDQ	%ZMM25,%ZMM24,%ZMM24

0x40fd77 VPXORD	%XMM25,%XMM25,%XMM25

0x40fd7d KMOVQ	%K1,%K2

0x40fd82 VGATHERQPD	0x8(,%ZMM24,1),%ZMM25{%K2}

0x40fd8d VPBROADCASTQ	%R15,%ZMM24

0x40fd93 VPADDD	%YMM2,%YMM26,%YMM26

0x40fd99 VPMOVSXDQ	%YMM26,%ZMM26

0x40fd9f VMOVAPD	%ZMM25,%ZMM22{%K1}

0x40fda5 VDIVPD	%ZMM22,%ZMM1,%ZMM25

0x40fdab VPADDQ	%ZMM26,%ZMM24,%ZMM24

0x40fdb1 VPMULLQ	0x1391d(%RIP){1to8},%ZMM24,%ZMM24

0x40fdbb VPXORD	%XMM26,%XMM26,%XMM26

0x40fdc1 KMOVQ	%K1,%K2

0x40fdc6 VGATHERQPD	(%R9,%ZMM24,1),%ZMM26{%K2}

0x40fdcd VMOVAPD	%ZMM26,%ZMM21{%K1}

0x40fdd3 VXORPD	%XMM26,%XMM26,%XMM26

0x40fdd9 KMOVQ	%K1,%K2

0x40fdde VGATHERQPD	(%R8,%ZMM24,1),%ZMM26{%K2}

0x40fde5 VMOVAPD	%ZMM26,%ZMM20{%K1}

0x40fdeb VMOVAPD	%ZMM21,%ZMM26

0x40fdf1 VFMADD213PD	%ZMM20,%ZMM25,%ZMM26

0x40fdf7 KMOVQ	%K1,%K2

0x40fdfc VSCATTERQPD	%ZMM26,(%R8,%ZMM24,1){%K2}

0x40fe03 VXORPD	%XMM26,%XMM26,%XMM26

0x40fe09 KMOVQ	%K1,%K2

0x40fe0e VGATHERQPD	0x8(%R9,%ZMM24,1),%ZMM26{%K2}

0x40fe16 VMOVAPD	%ZMM26,%ZMM19{%K1}

0x40fe1c VXORPD	%XMM26,%XMM26,%XMM26

0x40fe22 KMOVQ	%K1,%K2

0x40fe27 VGATHERQPD	0x8(%R8,%ZMM24,1),%ZMM26{%K2}

0x40fe2f VMOVAPD	%ZMM26,%ZMM18{%K1}

0x40fe35 VMOVAPD	%ZMM19,%ZMM26

0x40fe3b VFMADD213PD	%ZMM18,%ZMM25,%ZMM26

0x40fe41 KMOVQ	%K1,%K2

0x40fe46 VSCATTERQPD	%ZMM26,0x8(%R8,%ZMM24,1){%K2}

0x40fe4e VXORPD	%XMM26,%XMM26,%XMM26

0x40fe54 KMOVQ	%K1,%K2

0x40fe59 VGATHERQPD	0x10(%R9,%ZMM24,1),%ZMM26{%K2}

0x40fe61 VMOVAPD	%ZMM26,%ZMM17{%K1}

0x40fe67 VXORPD	%XMM26,%XMM26,%XMM26

0x40fe6d KMOVQ	%K1,%K2

0x40fe72 VGATHERQPD	0x10(%R8,%ZMM24,1),%ZMM26{%K2}

0x40fe7a VMOVAPD	%ZMM26,%ZMM16{%K1}

0x40fe80 VFMADD213PD	%ZMM16,%ZMM17,%ZMM25

0x40fe86 VSCATTERQPD	%ZMM25,0x10(%R8,%ZMM24,1){%K1}

0x40fe8e LEA	0x1(%RDI),%RAX

0x40fe92 ADD	$0x40,%ESI

0x40fe95 CMP	0x50(%RSP),%RDI

0x40fe9a MOV	%RAX,%RDI

0x40fe9d JE	40fc64

0x40fea3 LEA	(%RDI,%RDX,1),%RCX

0x40fea7 MOV	0x58(%RSP),%RAX

0x40feac MOV	(%RAX,%RCX,4),%R11D

0x40feb0 TEST	%R11D,%R11D

0x40feb3 JLE	40fe8e

0x40feb5 MOV	%ESI,%ECX

0x40feb7 LEA	(,%RCX,4),%R13

0x40febf SAL	$0x3,%RCX

0x40fec3 LEA	(%RDI,%RDX,1),%R15D

0x40fec7 SAL	$0x6,%R15D

0x40fecb MOV	0x48(%RSP),%RAX

0x40fed0 MOV	0x20(%RAX),%RDX

0x40fed4 MOV	0x28(%RAX),%R12

0x40fed8 MOV	0x10(%RDX),%R10

0x40fedc MOV	0x18(%RDX),%R8

0x40fee0 MOV	0x20(%RDX),%R9

0x40fee4 LEA	-0x1(%R11),%EDX

0x40fee8 MOVSXD	%EDX,%RDX

0x40feeb ADD	%R15,%RDX

0x40feee SAL	$0x3,%RDX

0x40fef2 LEA	(%RDX,%RDX,2),%RDX

0x40fef6 LEA	(%R9,%RDX,1),%R14

0x40fefa ADD	$0x10,%R14

0x40fefe LEA	(,%R15,8),%RBX

0x40ff06 LEA	(%RBX,%RBX,2),%RBX

0x40ff0a LEA	(%R8,%RBX,1),%RAX

0x40ff0e CMP	%RAX,%R14

0x40ff11 JB	40ffb0

0x40ff17 ADD	%R9,%RBX

0x40ff1a LEA	(%R8,%RDX,1),%RAX

0x40ff1e ADD	$0x10,%RAX

0x40ff22 CMP	%RBX,%RAX

0x40ff25 JB	40ffb0

0x40ff2b LEA	(%RCX,%RCX,2),%RCX

0x40ff2f ADD	$0x10,%RCX

0x40ff33 ADD	%R13,%R10

0x40ff36 XOR	%EDX,%EDX

0x40ff38 NOPL	(%RAX,%RAX,1)

  (105) 0x40ff40 MOVSXD	(%R10,%RDX,4),%RAX

  (105) 0x40ff44 SAL	$0x4,%RAX

  (105) 0x40ff48 VDIVSD	0x8(%R12,%RAX,1),%XMM0,%XMM2

  (105) 0x40ff4f VMOVSD	-0x10(%R9,%RCX,1),%XMM3

  (105) 0x40ff56 VFMADD213SD	-0x10(%R8,%RCX,1),%XMM2,%XMM3

  (105) 0x40ff5d VMOVSD	%XMM3,-0x10(%R8,%RCX,1)

  (105) 0x40ff64 VMOVSD	-0x8(%R9,%RCX,1),%XMM3

  (105) 0x40ff6b VFMADD213SD	-0x8(%R8,%RCX,1),%XMM2,%XMM3

  (105) 0x40ff72 VMOVSD	%XMM3,-0x8(%R8,%RCX,1)

  (105) 0x40ff79 VMOVSD	(%R9,%RCX,1),%XMM3

  (105) 0x40ff7f VFMADD213SD	(%R8,%RCX,1),%XMM2,%XMM3

  (105) 0x40ff85 VMOVSD	%XMM3,(%R8,%RCX,1)

  (105) 0x40ff8b ADD	$0x18,%RCX

  (105) 0x40ff8f INC	%RDX

  (105) 0x40ff92 CMP	%EDX,%R11D

  (105) 0x40ff95 JNE	40ff40

0x40ff97 MOV	0x30(%RSP),%RDX

0x40ff9c JMP	40fe8e

0x40ffb0 MOV	%R11D,%R14D

0x40ffb3 VPBROADCASTD	%R11D,%YMM25

0x40ffb9 VPBROADCASTQ	%R12,%ZMM24

0x40ffbf AND	$-0x8,%R14D

0x40ffc3 JE	40fd2e

0x40ffc9 VMOVUPS	%YMM23,0x60(%RSP)

0x40ffd1 VMOVUPS	%ZMM21,0x80(%RSP)

0x40ffd9 VMOVAPD	%ZMM22,%ZMM21

0x40ffdf VMOVAPD	%ZMM20,%ZMM23

0x40ffe5 VMOVAPD	%ZMM19,%ZMM22

0x40ffeb VMOVAPD	%ZMM18,%ZMM19

0x40fff1 VMOVAPD	%ZMM17,%ZMM20

0x40fff7 VMOVAPD	%ZMM16,%ZMM18

0x40fffd LEA	(%RCX,%RCX,2),%RDX

0x410001 LEA	-0x1(%R14),%ECX

0x410005 ADD	%R10,%R13

0x410008 XOR	%EBX,%EBX

0x41000a NOPW	(%RAX,%RAX,1)

  (104) 0x410010 VPMOVSXDQ	(%R13,%RBX,4),%ZMM26

  (104) 0x410018 VXORPD	%XMM27,%XMM27,%XMM27

  (104) 0x41001e KXNORW	%K0,%K0,%K1

  (104) 0x410022 VPSLLQ	$0x4,%ZMM26,%ZMM26

  (104) 0x410029 VGATHERQPD	0x8(%R12,%ZMM26,1),%ZMM27{%K1}

  (104) 0x410031 VDIVPD	%ZMM27,%ZMM1,%ZMM26

  (104) 0x410037 VMOVUPD	(%R9,%RDX,1),%ZMM27

  (104) 0x41003e VMOVUPD	0x40(%R9,%RDX,1),%ZMM28

  (104) 0x410046 VMOVUPD	0x80(%R9,%RDX,1),%ZMM29

  (104) 0x41004e VMOVAPD	%ZMM27,%ZMM30

  (104) 0x410054 VPERMT2PD	%ZMM28,%ZMM4,%ZMM30

  (104) 0x41005a VMOVAPD	%ZMM27,%ZMM31

  (104) 0x410060 VPERMT2PD	%ZMM28,%ZMM6,%ZMM31

  (104) 0x410066 VPERMT2PD	%ZMM27,%ZMM8,%ZMM28

  (104) 0x41006c VMOVUPD	(%R8,%RDX,1),%ZMM17

  (104) 0x410073 VMOVUPD	0x40(%R8,%RDX,1),%ZMM3

  (104) 0x41007b VPERMT2PD	%ZMM29,%ZMM5,%ZMM30

  (104) 0x410081 VMOVUPD	0x80(%R8,%RDX,1),%ZMM2

  (104) 0x410089 VMOVAPD	%ZMM17,%ZMM27

  (104) 0x41008f VPERMT2PD	%ZMM3,%ZMM4,%ZMM27

  (104) 0x410095 VPERMT2PD	%ZMM29,%ZMM7,%ZMM31

  (104) 0x41009b VPERMT2PD	%ZMM2,%ZMM5,%ZMM27

  (104) 0x4100a1 VMOVAPD	%ZMM17,%ZMM16

  (104) 0x4100a7 VPERMT2PD	%ZMM3,%ZMM6,%ZMM16

  (104) 0x4100ad VPERMT2PD	%ZMM29,%ZMM9,%ZMM28

  (104) 0x4100b3 VPERMT2PD	%ZMM2,%ZMM7,%ZMM16

  (104) 0x4100b9 VPERMT2PD	%ZMM17,%ZMM8,%ZMM3

  (104) 0x4100bf VFMADD231PD	%ZMM30,%ZMM26,%ZMM27

  (104) 0x4100c5 VPERMT2PD	%ZMM2,%ZMM9,%ZMM3

  (104) 0x4100cb VFMADD231PD	%ZMM31,%ZMM26,%ZMM16

  (104) 0x4100d1 VFMADD231PD	%ZMM28,%ZMM26,%ZMM3

  (104) 0x4100d7 VMOVAPD	%ZMM16,%ZMM2

  (104) 0x4100dd VPERMT2PD	%ZMM27,%ZMM10,%ZMM2

  (104) 0x4100e3 VMOVAPD	%ZMM27,%ZMM17

  (104) 0x4100e9 VPERMT2PD	%ZMM16,%ZMM11,%ZMM17

  (104) 0x4100ef VPERMT2PD	%ZMM16,%ZMM12,%ZMM27

  (104) 0x4100f5 VPERMT2PD	%ZMM3,%ZMM13,%ZMM27

  (104) 0x4100fb VPERMT2PD	%ZMM3,%ZMM14,%ZMM17

  (104) 0x410101 VPERMT2PD	%ZMM3,%ZMM15,%ZMM2

  (104) 0x410107 VMOVUPD	%ZMM2,0x80(%R8,%RDX,1)

  (104) 0x41010f VMOVUPD	%ZMM17,0x40(%R8,%RDX,1)

  (104) 0x410117 VMOVUPD	%ZMM27,(%R8,%RDX,1)

  (104) 0x41011e ADD	$0x8,%RBX

  (104) 0x410122 ADD	$0xc0,%RDX

  (104) 0x410129 CMP	%ECX,%EBX

  (104) 0x41012b JLE	410010

0x410131 CMP	%R14D,%R11D

0x410134 MOV	0x30(%RSP),%RDX

0x410139 VMOVAPD	%ZMM18,%ZMM16

0x41013f VMOVAPD	%ZMM20,%ZMM17

0x410145 VMOVAPD	%ZMM19,%ZMM18

0x41014b VMOVAPD	%ZMM22,%ZMM19

0x410151 VMOVAPD	%ZMM23,%ZMM20

0x410157 VMOVAPD	%ZMM21,%ZMM22

0x41015d VMOVUPD	0x80(%RSP),%ZMM21

0x410165 VMOVDQU64	0x60(%RSP),%YMM23

0x41016d JNE	40fd36

0x410173 JMP	40fe8e

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 85 - 94

--------------------------------------------------------------------------------

85:    #pragma omp parallel for

86:    for (int iBox=0; iBox<nBoxes; iBox++)

87:    {

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

94:          s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass;

Coverage (%)	Name	Source Location	Module
►87.10+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:43	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►12.87+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:43	exec
○	main	CoMD.c:125	exec

Coverage (%)	Name	Source Location	Module
►89.24+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►8.48+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:43	exec
○	main	CoMD.c:125	exec
►1.46+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so

Coverage (%)	Name	Source Location	Module
►93.13+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►5.89+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:43	exec
○	main	CoMD.c:125	exec

Coverage (%)	Name	Source Location	Module
►93.72+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►5.34+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:43	exec
○	main	CoMD.c:125	exec

Coverage (%)	Name	Source Location	Module
►94.26+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►4.60+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:43	exec
○	main	CoMD.c:125	exec

Coverage (%)	Name	Source Location	Module
►94.91+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.63+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:43	exec
○	main	CoMD.c:125	exec
►1.15+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so

Coverage (%)	Name	Source Location	Module
►96.08+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.27+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:43	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.10
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.11
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue,
Function	advancePosition.extracted
Source	timestep.c:85-94
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	75.38
CQA cycles if no scalar integer	68.50
CQA cycles if FP arith vectorized	75.38
CQA cycles if fully vectorized	67.74
Front-end cycles	75.38
P0 cycles	7.00
P1 cycles	7.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.00
P5 cycles	7.00
P6 cycles	24.75
P7 cycles	24.75
P8 cycles	24.75
P9 cycles	24.75
P10 cycles	37.25
P11 cycles	37.25
P12 cycles	37.17
P13 cycles	37.33
P14 cycles	63.00
P15 cycles	63.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	132.00
Nb uops	603.00
Nb loads	24.00
Nb stores	5.00
Nb stack references	6.00
FLOP/cycle	0.74
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	24.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.21
Bytes prefetched	0.00
Bytes loaded	708.00
Bytes stored	288.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	84.06
Vectorization ratio load	85.71
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	66.67
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	83.33
Vector-efficiency ratio all	70.83
Vector-efficiency ratio load	76.79
Vector-efficiency ratio store	90.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	53.13
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	69.92

Metric	Value
CQA speedup if no scalar integer	1.10
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.11
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue,
Function	advancePosition.extracted
Source	timestep.c:85-94
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	75.38
CQA cycles if no scalar integer	68.50
CQA cycles if FP arith vectorized	75.38
CQA cycles if fully vectorized	67.74
Front-end cycles	75.38
P0 cycles	7.00
P1 cycles	7.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.00
P5 cycles	7.00
P6 cycles	24.75
P7 cycles	24.75
P8 cycles	24.75
P9 cycles	24.75
P10 cycles	37.25
P11 cycles	37.25
P12 cycles	37.17
P13 cycles	37.33
P14 cycles	63.00
P15 cycles	63.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	132.00
Nb uops	603.00
Nb loads	24.00
Nb stores	5.00
Nb stack references	6.00
FLOP/cycle	0.74
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	24.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.21
Bytes prefetched	0.00
Bytes loaded	708.00
Bytes stored	288.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	84.06
Vectorization ratio load	85.71
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	66.67
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	83.33
Vector-efficiency ratio all	70.83
Vector-efficiency ratio load	76.79
Vector-efficiency ratio store	90.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	53.13
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	69.92

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advancePosition.extracted
Source file and lines	timestep.c:85-94
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 75.38 to 68.50 cycles (1.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 70% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 75.38 to 67.74 cycles (1.11x speedup).

Details

84% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

85% of SSE/AVX loads are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
83% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 24 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VGATHERQPD: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:91
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88
VPBROADCASTQ: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:90
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88
VSCATTERQPD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88
VMOVUPS: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:91
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
VSCATTERQPD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

4 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 56 FP arithmetical operations:

24: addition or subtraction (all inside FMA instructions)
24: multiply (all inside FMA instructions)
8: divide

The binary loop is loading 708 bytes (88 double precision FP elements). The binary loop is storing 288 bytes (36 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	132
nb uops	603
loop length	707
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	4
used zmm registers	12
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	75.38 cycles
front end	75.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.00	7.00	7.00	7.00	7.00	7.00	24.75	24.75	24.75	24.75	37.25	37.25	37.17	37.33	63.00	63.00
cycles	7.00	7.00	7.00	7.00	7.00	7.00	24.75	24.75	24.75	24.75	37.25	37.25	37.17	37.33	63.00	63.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	75.38
Dispatch	63.00
DIV/SQRT	4.00
Overall L1	75.38

Vectorization ratios

INT

all	57%
load	66%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
other	46%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	84%
load	85%
store	100%
mul	100%
add-sub	66%
fma	100%
div/sqrt	100%
other	83%

Vector efficiency ratios

INT

all	38%
load	45%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	53%
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	90%
load	100%
store	90%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	100%
other	88%

INT+FP

all	70%
load	76%
store	90%
mul	100%
add-sub	53%
fma	100%
div/sqrt	100%
other	69%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 75.38 cycles. At this rate:

3% of peak load performance is reached (9.39 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.82 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 75.38 to 63.00 cycles (1.20x speedup).

ASM code

In the binary file, the address of the loop is: 40fea3

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTD %R14D,%YMM26	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VPSUBD %YMM26,%YMM25,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVDQU 0x14656(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPCMPNLEUD %YMM2,%YMM25,%K1																				vect (50.0%)
MOVSXD %R14D,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU32 (%R10,%RAX,4),%YMM25{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA32 %YMM25,%YMM23{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPMOVSXDQ %YMM23,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPSLLQ $0x4,%ZMM25,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM25,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPXORD %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD 0x8(,%ZMM24,1),%ZMM25{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VPBROADCASTQ %R15,%ZMM24	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDD %YMM2,%YMM26,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMOVSXDQ %YMM26,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %ZMM25,%ZMM22{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VDIVPD %ZMM22,%ZMM1,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VPADDQ %ZMM26,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPMULLQ 0x1391d(%RIP){1to8},%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VPXORD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R9,%ZMM24,1),%ZMM26{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM26,%ZMM21{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R8,%ZMM24,1),%ZMM26{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM26,%ZMM20{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM21,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM20,%ZMM25,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VSCATTERQPD %ZMM26,(%R8,%ZMM24,1){%K2}	48	0	0	0	0	0	0	2	2	2	2	0	3	3.50	1.50	9	9	1-40	12.14	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD 0x8(%R9,%ZMM24,1),%ZMM26{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM26,%ZMM19{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD 0x8(%R8,%ZMM24,1),%ZMM26{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM26,%ZMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM19,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM18,%ZMM25,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VSCATTERQPD %ZMM26,0x8(%R8,%ZMM24,1){%K2}	48	0	0	0	0	0	0	2	2	2	2	0	3	3.50	1.50	9	9	1-40	12.14	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD 0x10(%R9,%ZMM24,1),%ZMM26{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM26,%ZMM17{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD 0x10(%R8,%ZMM24,1),%ZMM26{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM26,%ZMM16{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM16,%ZMM17,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSCATTERQPD %ZMM25,0x10(%R8,%ZMM24,1){%K1}	48	0	0	0	0	0	0	2	2	2	2	0	3	3.50	1.50	9	9	1-40	12.14	vect (100.0%)
LEA 0x1(%RDI),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x40,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP 0x50(%RSP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 40fc64 <advancePosition.extracted+0x84>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%RDI,%RDX,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x58(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RCX,4),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40fe8e <advancePosition.extracted+0x2ae>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ESI,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RCX,4),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RDI,%RDX,1),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x6,%R15D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV 0x48(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RDX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RDX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA -0x1(%R11),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVSXD %EDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RDX,%RDX,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R9,%RDX,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x10,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (,%R15,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RBX,2),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R8,%RBX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 40ffb0 <advancePosition.extracted+0x3d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %R9,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R8,%RDX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x10,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 40ffb0 <advancePosition.extracted+0x3d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%RCX,%RCX,2),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 40fe8e <advancePosition.extracted+0x2ae>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %R11D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTD %R11D,%YMM25	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VPBROADCASTQ %R12,%ZMM24	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
AND $-0x8,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 40fd2e <advancePosition.extracted+0x14e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPS %YMM23,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPS %ZMM21,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVAPD %ZMM22,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM20,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM19,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM18,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM17,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM16,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
LEA (%RCX,%RCX,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%R14),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R10,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R14D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPD %ZMM18,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM20,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM19,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM22,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM23,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM21,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVUPD 0x80(%RSP),%ZMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQU64 0x60(%RSP),%YMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
JNE 40fd36 <advancePosition.extracted+0x156>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 40fe8e <advancePosition.extracted+0x2ae>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	advancePosition.extracted
Source file and lines	timestep.c:85-94
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

84% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

85% of SSE/AVX loads are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
83% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 24 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VGATHERQPD: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:91
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88
VPBROADCASTQ: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:90
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88
VSCATTERQPD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88
VMOVUPS: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:91
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
VSCATTERQPD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

4 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 56 FP arithmetical operations:

24: addition or subtraction (all inside FMA instructions)
24: multiply (all inside FMA instructions)
8: divide

The binary loop is loading 708 bytes (88 double precision FP elements). The binary loop is storing 288 bytes (36 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	132
nb uops	603
loop length	707
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	4
used zmm registers	12
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	75.38 cycles
front end	75.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.00	7.00	7.00	7.00	7.00	7.00	24.75	24.75	24.75	24.75	37.25	37.25	37.17	37.33	63.00	63.00
cycles	7.00	7.00	7.00	7.00	7.00	7.00	24.75	24.75	24.75	24.75	37.25	37.25	37.17	37.33	63.00	63.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	75.38
Dispatch	63.00
DIV/SQRT	4.00
Overall L1	75.38

Vectorization ratios

INT

all	57%
load	66%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
other	46%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	84%
load	85%
store	100%
mul	100%
add-sub	66%
fma	100%
div/sqrt	100%
other	83%

Vector efficiency ratios

INT

all	38%
load	45%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	53%
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	90%
load	100%
store	90%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	100%
other	88%

INT+FP

all	70%
load	76%
store	90%
mul	100%
add-sub	53%
fma	100%
div/sqrt	100%
other	69%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 75.38 cycles. At this rate:

3% of peak load performance is reached (9.39 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.82 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 40fea3

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTD %R14D,%YMM26	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VPSUBD %YMM26,%YMM25,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVDQU 0x14656(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPCMPNLEUD %YMM2,%YMM25,%K1																				vect (50.0%)
MOVSXD %R14D,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU32 (%R10,%RAX,4),%YMM25{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA32 %YMM25,%YMM23{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPMOVSXDQ %YMM23,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPSLLQ $0x4,%ZMM25,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM25,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPXORD %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD 0x8(,%ZMM24,1),%ZMM25{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VPBROADCASTQ %R15,%ZMM24	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDD %YMM2,%YMM26,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMOVSXDQ %YMM26,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %ZMM25,%ZMM22{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VDIVPD %ZMM22,%ZMM1,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VPADDQ %ZMM26,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPMULLQ 0x1391d(%RIP){1to8},%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VPXORD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R9,%ZMM24,1),%ZMM26{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM26,%ZMM21{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R8,%ZMM24,1),%ZMM26{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM26,%ZMM20{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM21,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM20,%ZMM25,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VSCATTERQPD %ZMM26,(%R8,%ZMM24,1){%K2}	48	0	0	0	0	0	0	2	2	2	2	0	3	3.50	1.50	9	9	1-40	12.14	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD 0x8(%R9,%ZMM24,1),%ZMM26{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM26,%ZMM19{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD 0x8(%R8,%ZMM24,1),%ZMM26{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM26,%ZMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM19,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM18,%ZMM25,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VSCATTERQPD %ZMM26,0x8(%R8,%ZMM24,1){%K2}	48	0	0	0	0	0	0	2	2	2	2	0	3	3.50	1.50	9	9	1-40	12.14	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD 0x10(%R9,%ZMM24,1),%ZMM26{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM26,%ZMM17{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD 0x10(%R8,%ZMM24,1),%ZMM26{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM26,%ZMM16{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM16,%ZMM17,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSCATTERQPD %ZMM25,0x10(%R8,%ZMM24,1){%K1}	48	0	0	0	0	0	0	2	2	2	2	0	3	3.50	1.50	9	9	1-40	12.14	vect (100.0%)
LEA 0x1(%RDI),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x40,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP 0x50(%RSP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 40fc64 <advancePosition.extracted+0x84>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%RDI,%RDX,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x58(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RCX,4),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40fe8e <advancePosition.extracted+0x2ae>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ESI,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RCX,4),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RDI,%RDX,1),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x6,%R15D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV 0x48(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RDX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RDX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA -0x1(%R11),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVSXD %EDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RDX,%RDX,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R9,%RDX,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x10,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (,%R15,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RBX,2),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R8,%RBX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 40ffb0 <advancePosition.extracted+0x3d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %R9,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R8,%RDX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x10,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 40ffb0 <advancePosition.extracted+0x3d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%RCX,%RCX,2),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 40fe8e <advancePosition.extracted+0x2ae>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %R11D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTD %R11D,%YMM25	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VPBROADCASTQ %R12,%ZMM24	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
AND $-0x8,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 40fd2e <advancePosition.extracted+0x14e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPS %YMM23,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPS %ZMM21,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVAPD %ZMM22,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM20,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM19,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM18,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM17,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM16,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
LEA (%RCX,%RCX,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%R14),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R10,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R14D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPD %ZMM18,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM20,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM19,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM22,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM23,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM21,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVUPD 0x80(%RSP),%ZMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQU64 0x60(%RSP),%YMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
JNE 40fd36 <advancePosition.extracted+0x156>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 40fe8e <advancePosition.extracted+0x2ae>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

▶Scalability Runs Description

Run 8x1	Number processes: 8Number nodes: 1Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/run/oneview_runs/multicore/icx/oneview_run_1740438801OMP_NUM_THREADS: 1I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x12	Number processes: 8Number nodes: 1Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/run/oneview_runs/multicore/icx/oneview_run_1740438801OMP_NUM_THREADS: 12I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x16	Number processes: 8Number nodes: 1Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/run/oneview_runs/multicore/icx/oneview_run_1740438801OMP_NUM_THREADS: 16I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x20	Number processes: 8Number nodes: 1Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/run/oneview_runs/multicore/icx/oneview_run_1740438801OMP_NUM_THREADS: 20I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x24	Number processes: 8Number nodes: 1Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/run/oneview_runs/multicore/icx/oneview_run_1740438801OMP_NUM_THREADS: 24I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x28	Number processes: 8Number nodes: 1Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/run/oneview_runs/multicore/icx/oneview_run_1740438801OMP_NUM_THREADS: 28I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x32	Number processes: 8Number nodes: 1Run Command: <executable> -x 200 -y 200 -z 200 --xproc=2 --yproc=2 --zproc=2MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/run/oneview_runs/multicore/icx/oneview_run_1740438801OMP_NUM_THREADS: 32I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads

(8x1) Efficiency	(8x1) Potential Speed-Up (%)	(8x12) Efficiency	(8x12) Potential Speed-Up (%)	(8x16) Efficiency	(8x16) Potential Speed-Up (%)	(8x20) Efficiency	(8x20) Potential Speed-Up (%)	(8x24) Efficiency	(8x24) Potential Speed-Up (%)	(8x28) Efficiency	(8x28) Potential Speed-Up (%)	(8x32) Efficiency	(8x32) Potential Speed-Up (%)
1	0	0.73	0.15	0.69	0.17	0.64	0.19	0.6	0.21	0.56	0.23	0.59	0.19

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
8x1	8	1	1	1	2.4099988937378	0.46886938810349
8x12	96	0.73	8.73	12	0.32999992370605	0.54016679525375
8x16	128	0.69	11.08	16	0.27999997138977	0.54402035474777
8x20	160	0.64	12.83	20	0.25499999523163	0.52124148607254
8x24	192	0.6	14.29	24	0.22499999403954	0.52975392341614
8x28	224	0.56	15.76	28	0.22999998927116	0.51618868112564
8x32	256	0.59	18.94	32	0.19999997317791	0.45479193329811

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency