OV - exec - Loop 87

	Loop Id: 87	Module: exec	Source: ljForce.c:187-216 [...]	Coverage: 11.85%

0x40ba20 MOV	0x18(%R8),%RBX

0x40ba24 LEA	(%R14,%R14,2),%R9

0x40ba28 MOV	%EAX,%R10D

0x40ba2b NOT	%R10D

0x40ba2e ADD	%R12D,%R10D

0x40ba31 AND	$0x1,%R10D

0x40ba35 LEA	(%RBX,%R9,1),%R11

0x40ba39 ADD	%RDI,%RBX

0x40ba3c VMOVSD	(%R11),%XMM15

0x40ba41 VMOVSD	0x8(%R11),%XMM1

0x40ba47 VSUBSD	(%RBX),%XMM15,%XMM16

0x40ba4d VSUBSD	0x8(%RBX),%XMM1,%XMM1

0x40ba52 VMULSD	%XMM1,%XMM1,%XMM0

0x40ba56 VFMADD231SD	%XMM16,%XMM16,%XMM0

0x40ba5c VMOVSD	0x10(%R11),%XMM2

0x40ba62 VSUBSD	0x10(%RBX),%XMM2,%XMM2

0x40ba67 VFMADD231SD	%XMM2,%XMM2,%XMM0

0x40ba6c VCOMISD	%XMM0,%XMM3

0x40ba70 JB	40baf7

0x40ba76 VCOMISD	%XMM6,%XMM0

0x40ba7a JBE	40baf7

0x40ba7c VDIVSD	%XMM0,%XMM9,%XMM0

0x40ba80 VMULSD	%XMM0,%XMM0,%XMM15

0x40ba84 VMULSD	%XMM10,%XMM0,%XMM17

0x40ba8a VMULSD	%XMM0,%XMM12,%XMM0

0x40ba8e VMULSD	%XMM0,%XMM15,%XMM0

0x40ba92 VSUBSD	%XMM9,%XMM0,%XMM15

0x40ba97 VFMSUB132SD	%XMM0,%XMM11,%XMM15

0x40ba9c MOV	0x30(%R8),%RDX

0x40baa0 MOV	0x28(%R8),%RSI

0x40baa4 VMOVAPD	%XMM15,%XMM20

0x40baaa VFMADD231SD	%XMM8,%XMM15,%XMM7

0x40baaf VMOVAPD	%XMM0,%XMM15

0x40bab3 VFMADD132SD	%XMM14,%XMM13,%XMM15

0x40bab8 ADD	%R14,%RDX

0x40babb ADD	%R9,%RSI

0x40babe VFMADD213SD	(%RDX),%XMM8,%XMM20

0x40bac4 VMOVSD	%XMM20,(%RDX)

0x40baca VMULSD	%XMM15,%XMM0,%XMM0

0x40bacf VMULSD	%XMM17,%XMM0,%XMM15

0x40bad5 VFNMADD213SD	(%RSI),%XMM15,%XMM16

0x40badb VFNMADD213SD	0x8(%RSI),%XMM15,%XMM1

0x40bae1 VMOVSD	%XMM16,(%RSI)

0x40bae7 VFNMADD213SD	0x10(%RSI),%XMM2,%XMM15

0x40baed VMOVSD	%XMM1,0x8(%RSI)

0x40baf2 VMOVSD	%XMM15,0x10(%RSI)

0x40baf7 LEA	0x1(%RAX),%EDX

0x40bafa LEA	0x18(%RBX),%RSI

0x40bafe CMP	%R12D,%EDX

0x40bb01 JGE	40bd6f

0x40bb07 TEST	%R10D,%R10D

0x40bb0a JE	40bbe0

0x40bb10 VMOVSD	(%R11),%XMM1

0x40bb15 VMOVSD	0x8(%R11),%XMM2

0x40bb1b VSUBSD	0x18(%RBX),%XMM1,%XMM18

0x40bb22 VSUBSD	0x8(%RSI),%XMM2,%XMM1

0x40bb27 VMULSD	%XMM1,%XMM1,%XMM0

0x40bb2b VFMADD231SD	%XMM18,%XMM18,%XMM0

0x40bb31 VMOVSD	0x10(%R11),%XMM15

0x40bb37 VSUBSD	0x10(%RSI),%XMM15,%XMM2

0x40bb3c VFMADD231SD	%XMM2,%XMM2,%XMM0

0x40bb41 VCOMISD	%XMM0,%XMM3

0x40bb45 JB	40bbce

0x40bb4b VCOMISD	%XMM6,%XMM0

0x40bb4f JBE	40bbce

0x40bb51 VDIVSD	%XMM0,%XMM9,%XMM0

0x40bb55 VMULSD	%XMM0,%XMM0,%XMM15

0x40bb59 VMULSD	%XMM10,%XMM0,%XMM19

0x40bb5f VMULSD	%XMM0,%XMM12,%XMM0

0x40bb63 VMULSD	%XMM0,%XMM15,%XMM0

0x40bb67 VSUBSD	%XMM9,%XMM0,%XMM15

0x40bb6c VFMSUB132SD	%XMM0,%XMM11,%XMM15

0x40bb71 MOV	0x30(%R8),%RBX

0x40bb75 MOV	0x28(%R8),%R10

0x40bb79 VMOVAPD	%XMM15,%XMM23

0x40bb7f VFMADD231SD	%XMM8,%XMM15,%XMM7

0x40bb84 VMOVAPD	%XMM0,%XMM15

0x40bb88 VFMADD132SD	%XMM14,%XMM13,%XMM15

0x40bb8d ADD	%R14,%RBX

0x40bb90 ADD	%R9,%R10

0x40bb93 VFMADD213SD	(%RBX),%XMM8,%XMM23

0x40bb99 VMOVSD	%XMM23,(%RBX)

0x40bb9f VMULSD	%XMM15,%XMM0,%XMM0

0x40bba4 VMULSD	%XMM19,%XMM0,%XMM15

0x40bbaa VFNMADD213SD	(%R10),%XMM15,%XMM18

0x40bbb0 VFNMADD213SD	0x8(%R10),%XMM15,%XMM1

0x40bbb6 VMOVSD	%XMM18,(%R10)

0x40bbbc VFNMADD213SD	0x10(%R10),%XMM2,%XMM15

0x40bbc2 VMOVSD	%XMM1,0x8(%R10)

0x40bbc8 VMOVSD	%XMM15,0x10(%R10)

0x40bbce INC	%EDX

0x40bbd0 ADD	$0x18,%RSI

0x40bbd4 CMP	%R12D,%EDX

0x40bbd7 JGE	40bd6f

0x40bbdd NOPL	(%RAX)

  (88) 0x40bbe0 VMOVSD	(%R11),%XMM1

  (88) 0x40bbe5 VMOVSD	0x8(%R11),%XMM2

  (88) 0x40bbeb VSUBSD	(%RSI),%XMM1,%XMM24

  (88) 0x40bbf1 VSUBSD	0x8(%RSI),%XMM2,%XMM1

  (88) 0x40bbf6 VMULSD	%XMM1,%XMM1,%XMM0

  (88) 0x40bbfa VFMADD231SD	%XMM24,%XMM24,%XMM0

  (88) 0x40bc00 VMOVSD	0x10(%R11),%XMM15

  (88) 0x40bc06 VSUBSD	0x10(%RSI),%XMM15,%XMM2

  (88) 0x40bc0b VFMADD231SD	%XMM2,%XMM2,%XMM0

  (88) 0x40bc10 VCOMISD	%XMM0,%XMM3

  (88) 0x40bc14 JB	40bc9d

  (88) 0x40bc1a VCOMISD	%XMM6,%XMM0

  (88) 0x40bc1e JBE	40bc9d

  (88) 0x40bc20 VDIVSD	%XMM0,%XMM9,%XMM0

  (88) 0x40bc24 VMULSD	%XMM0,%XMM0,%XMM15

  (88) 0x40bc28 VMULSD	%XMM10,%XMM0,%XMM25

  (88) 0x40bc2e VMULSD	%XMM0,%XMM12,%XMM0

  (88) 0x40bc32 VMULSD	%XMM0,%XMM15,%XMM0

  (88) 0x40bc36 VSUBSD	%XMM9,%XMM0,%XMM15

  (88) 0x40bc3b VFMSUB132SD	%XMM0,%XMM11,%XMM15

  (88) 0x40bc40 MOV	0x30(%R8),%RBX

  (88) 0x40bc44 MOV	0x28(%R8),%R10

  (88) 0x40bc48 VMOVAPD	%XMM15,%XMM26

  (88) 0x40bc4e VFMADD231SD	%XMM8,%XMM15,%XMM7

  (88) 0x40bc53 VMOVAPD	%XMM0,%XMM15

  (88) 0x40bc57 VFMADD132SD	%XMM14,%XMM13,%XMM15

  (88) 0x40bc5c ADD	%R14,%RBX

  (88) 0x40bc5f ADD	%R9,%R10

  (88) 0x40bc62 VFMADD213SD	(%RBX),%XMM8,%XMM26

  (88) 0x40bc68 VMOVSD	%XMM26,(%RBX)

  (88) 0x40bc6e VMULSD	%XMM15,%XMM0,%XMM0

  (88) 0x40bc73 VMULSD	%XMM25,%XMM0,%XMM15

  (88) 0x40bc79 VFNMADD213SD	(%R10),%XMM15,%XMM24

  (88) 0x40bc7f VFNMADD213SD	0x8(%R10),%XMM15,%XMM1

  (88) 0x40bc85 VMOVSD	%XMM24,(%R10)

  (88) 0x40bc8b VFNMADD213SD	0x10(%R10),%XMM2,%XMM15

  (88) 0x40bc91 VMOVSD	%XMM1,0x8(%R10)

  (88) 0x40bc97 VMOVSD	%XMM15,0x10(%R10)

  (88) 0x40bc9d VMOVSD	(%R11),%XMM1

  (88) 0x40bca2 VMOVSD	0x8(%R11),%XMM2

  (88) 0x40bca8 VSUBSD	0x18(%RSI),%XMM1,%XMM27

  (88) 0x40bcaf VSUBSD	0x20(%RSI),%XMM2,%XMM1

  (88) 0x40bcb4 VMULSD	%XMM1,%XMM1,%XMM0

  (88) 0x40bcb8 VFMADD231SD	%XMM27,%XMM27,%XMM0

  (88) 0x40bcbe VMOVSD	0x10(%R11),%XMM15

  (88) 0x40bcc4 VSUBSD	0x28(%RSI),%XMM15,%XMM15

  (88) 0x40bcc9 INC	%EDX

  (88) 0x40bccb LEA	0x18(%RSI),%RBX

  (88) 0x40bccf VFMADD231SD	%XMM15,%XMM15,%XMM0

  (88) 0x40bcd4 VCOMISD	%XMM0,%XMM3

  (88) 0x40bcd8 JB	40bd60

  (88) 0x40bcde VCOMISD	%XMM6,%XMM0

  (88) 0x40bce2 JBE	40bd60

  (88) 0x40bce4 VDIVSD	%XMM0,%XMM9,%XMM0

  (88) 0x40bce8 VMULSD	%XMM0,%XMM0,%XMM2

  (88) 0x40bcec VMULSD	%XMM10,%XMM0,%XMM28

  (88) 0x40bcf2 VMULSD	%XMM0,%XMM12,%XMM0

  (88) 0x40bcf6 VMULSD	%XMM0,%XMM2,%XMM0

  (88) 0x40bcfa VSUBSD	%XMM9,%XMM0,%XMM2

  (88) 0x40bcff VFMSUB132SD	%XMM0,%XMM11,%XMM2

  (88) 0x40bd04 MOV	0x30(%R8),%RSI

  (88) 0x40bd08 MOV	0x28(%R8),%R10

  (88) 0x40bd0c VMOVAPD	%XMM2,%XMM29

  (88) 0x40bd12 VFMADD231SD	%XMM8,%XMM2,%XMM7

  (88) 0x40bd17 VMOVAPD	%XMM0,%XMM2

  (88) 0x40bd1b VFMADD132SD	%XMM14,%XMM13,%XMM2

  (88) 0x40bd20 ADD	%R14,%RSI

  (88) 0x40bd23 ADD	%R9,%R10

  (88) 0x40bd26 VFMADD213SD	(%RSI),%XMM8,%XMM29

  (88) 0x40bd2c VMOVSD	%XMM29,(%RSI)

  (88) 0x40bd32 VMULSD	%XMM2,%XMM0,%XMM0

  (88) 0x40bd36 VMULSD	%XMM28,%XMM0,%XMM2

  (88) 0x40bd3c VFNMADD213SD	(%R10),%XMM2,%XMM27

  (88) 0x40bd42 VFNMADD213SD	0x8(%R10),%XMM2,%XMM1

  (88) 0x40bd48 VMOVSD	%XMM27,(%R10)

  (88) 0x40bd4e VFNMADD213SD	0x10(%R10),%XMM15,%XMM2

  (88) 0x40bd54 VMOVSD	%XMM1,0x8(%R10)

  (88) 0x40bd5a VMOVSD	%XMM2,0x10(%R10)

  (88) 0x40bd60 INC	%EDX

  (88) 0x40bd62 LEA	0x18(%RBX),%RSI

  (88) 0x40bd66 CMP	%R12D,%EDX

  (88) 0x40bd69 JL	40bbe0

0x40bd6f INC	%R15D

0x40bd72 ADD	$0x8,%R14

0x40bd76 CMP	%R15D,%ECX

0x40bd79 JG	40ba20

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 187 - 216

--------------------------------------------------------------------------------

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module
►96.81+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.73+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	ljForce	ljForce.c:172	exec
○	timestep	timestep.c:51	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.38
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	P10, P11,
Function	ljForce._omp_fn.1
Source	ljForce.c:187-187,ljForce.c:191-191,ljForce.c:197-198,ljForce.c:201-201,ljForce.c:206-210,ljForce.c:213-213,ljForce.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	7.16
CQA cycles if fully vectorized	2.13
Front-end cycles	12.63
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	4.50
P3 cycles	4.50
P4 cycles	4.50
P5 cycles	4.50
P6 cycles	8.25
P7 cycles	8.25
P8 cycles	8.25
P9 cycles	8.25
P10 cycles	17.00
P11 cycles	17.00
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	6.00
P15 cycles	6.00
DIV/SQRT cycles	8.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	99.00
Nb uops	101.00
Nb loads	25.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	3.53
Nb FLOP add-sub	8.00
Nb FLOP mul	14.00
Nb FLOP fma	18.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.53
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	5.97
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	36.36
Vector-efficiency ratio all	12.97
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	15.34

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.38
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	P10, P11,
Function	ljForce._omp_fn.1
Source	ljForce.c:187-187,ljForce.c:191-191,ljForce.c:197-198,ljForce.c:201-201,ljForce.c:206-210,ljForce.c:213-213,ljForce.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	7.16
CQA cycles if fully vectorized	2.13
Front-end cycles	12.63
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	4.50
P3 cycles	4.50
P4 cycles	4.50
P5 cycles	4.50
P6 cycles	8.25
P7 cycles	8.25
P8 cycles	8.25
P9 cycles	8.25
P10 cycles	17.00
P11 cycles	17.00
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	6.00
P15 cycles	6.00
DIV/SQRT cycles	8.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	99.00
Nb uops	101.00
Nb loads	25.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	3.53
Nb FLOP add-sub	8.00
Nb FLOP mul	14.00
Nb FLOP fma	18.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.53
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	5.97
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	36.36
Vector-efficiency ratio all	12.97
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	15.34

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:187-216
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187-191,197-216.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187,191,197-198,201,206-210,213,216.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 120 paths individually, rerun with max-paths=120
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 120 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 17.00 to 2.12 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.00 to 12.63 cycles (1.35x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 17.00 to 16.00 cycles (1.06x speedup).

FMA

Detected 18 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:201
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:201
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:201
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:201

Type of elements and instruction set

46 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 60 FP arithmetical operations:

26: addition or subtraction (18 inside FMA instructions)
32: multiply (18 inside FMA instructions)
2: divide

The binary loop is loading 200 bytes (25 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.23 FP operations per loaded or stored byte.

General properties

nb instructions	99
nb uops	101
loop length	464
used x86 registers	13
used mmx registers	0
used xmm registers	20
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.57

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	12.63 cycles
front end	12.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.50	4.50	4.50	4.50	4.50	4.50	8.25	8.25	8.25	8.25	17.00	17.00	6.00	6.00	6.00	6.00
cycles	4.50	4.50	4.50	4.50	4.50	4.50	8.25	8.25	8.25	8.25	17.00	17.00	6.00	6.00	6.00	6.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

8.00

Cycles summary

Front-end	12.63
Dispatch	17.00
DIV/SQRT	8.00
Overall L1	17.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	6%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	50%

INT+FP

all	5%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	36%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

4% of peak load performance is reached (11.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.76 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40ba20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0x18(%R8),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R14,%R14,2),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOT %R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R12D,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RBX,%R9,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%R11),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R11),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD (%RBX),%XMM15,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD 0x8(%RBX),%XMM1,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM16,%XMM16,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0x10(%R11),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD 0x10(%RBX),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD231SD %XMM2,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM0,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JB 40baf7 <ljForce._omp_fn.1+0x377>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VCOMISD %XMM6,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 40baf7 <ljForce._omp_fn.1+0x377>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VDIVSD %XMM0,%XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMULSD %XMM0,%XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM10,%XMM0,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM0,%XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM0,%XMM15,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM9,%XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMSUB132SD %XMM0,%XMM11,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%R8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%R8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPD %XMM15,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD231SD %XMM8,%XMM15,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD132SD %XMM14,%XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
ADD %R14,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD (%RDX),%XMM8,%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM20,(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD %XMM15,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM17,%XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFNMADD213SD (%RSI),%XMM15,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFNMADD213SD 0x8(%RSI),%XMM15,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM16,(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VFNMADD213SD 0x10(%RSI),%XMM2,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,0x8(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM15,0x10(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x1(%RAX),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x18(%RBX),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R12D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40bd6f <ljForce._omp_fn.1+0x5ef>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST %R10D,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40bbe0 <ljForce._omp_fn.1+0x460>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R11),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R11),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD 0x18(%RBX),%XMM1,%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD 0x8(%RSI),%XMM2,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM18,%XMM18,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0x10(%R11),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD 0x10(%RSI),%XMM15,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD231SD %XMM2,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM0,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JB 40bbce <ljForce._omp_fn.1+0x44e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VCOMISD %XMM6,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 40bbce <ljForce._omp_fn.1+0x44e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VDIVSD %XMM0,%XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMULSD %XMM0,%XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM10,%XMM0,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM0,%XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM0,%XMM15,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM9,%XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMSUB132SD %XMM0,%XMM11,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%R8),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%R8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPD %XMM15,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD231SD %XMM8,%XMM15,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD132SD %XMM14,%XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
ADD %R14,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R9,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD (%RBX),%XMM8,%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM23,(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD %XMM15,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM19,%XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFNMADD213SD (%R10),%XMM15,%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFNMADD213SD 0x8(%R10),%XMM15,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM18,(%R10)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VFNMADD213SD 0x10(%R10),%XMM2,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,0x8(%R10)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM15,0x10(%R10)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40bd6f <ljForce._omp_fn.1+0x5ef>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JG 40ba20 <ljForce._omp_fn.1+0x2a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:187-216
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 120 paths individually, rerun with max-paths=120
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 17.00 to 16.00 cycles (1.06x speedup).

FMA

Detected 18 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:201
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:201
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:201
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:201

Type of elements and instruction set

46 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 60 FP arithmetical operations:

26: addition or subtraction (18 inside FMA instructions)
32: multiply (18 inside FMA instructions)
2: divide

The binary loop is loading 200 bytes (25 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.23 FP operations per loaded or stored byte.

General properties

nb instructions	99
nb uops	101
loop length	464
used x86 registers	13
used mmx registers	0
used xmm registers	20
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.57

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	12.63 cycles
front end	12.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.50	4.50	4.50	4.50	4.50	4.50	8.25	8.25	8.25	8.25	17.00	17.00	6.00	6.00	6.00	6.00
cycles	4.50	4.50	4.50	4.50	4.50	4.50	8.25	8.25	8.25	8.25	17.00	17.00	6.00	6.00	6.00	6.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

8.00

Cycles summary

Front-end	12.63
Dispatch	17.00
DIV/SQRT	8.00
Overall L1	17.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	6%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	50%

INT+FP

all	5%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	36%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

4% of peak load performance is reached (11.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.76 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40ba20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0x18(%R8),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R14,%R14,2),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOT %R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R12D,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RBX,%R9,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%R11),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R11),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD (%RBX),%XMM15,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD 0x8(%RBX),%XMM1,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM16,%XMM16,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0x10(%R11),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD 0x10(%RBX),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD231SD %XMM2,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM0,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JB 40baf7 <ljForce._omp_fn.1+0x377>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VCOMISD %XMM6,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 40baf7 <ljForce._omp_fn.1+0x377>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VDIVSD %XMM0,%XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMULSD %XMM0,%XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM10,%XMM0,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM0,%XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM0,%XMM15,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM9,%XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMSUB132SD %XMM0,%XMM11,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%R8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%R8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPD %XMM15,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD231SD %XMM8,%XMM15,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD132SD %XMM14,%XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
ADD %R14,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD (%RDX),%XMM8,%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM20,(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD %XMM15,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM17,%XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFNMADD213SD (%RSI),%XMM15,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFNMADD213SD 0x8(%RSI),%XMM15,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM16,(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VFNMADD213SD 0x10(%RSI),%XMM2,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,0x8(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM15,0x10(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x1(%RAX),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x18(%RBX),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R12D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40bd6f <ljForce._omp_fn.1+0x5ef>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST %R10D,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40bbe0 <ljForce._omp_fn.1+0x460>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R11),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R11),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD 0x18(%RBX),%XMM1,%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD 0x8(%RSI),%XMM2,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM18,%XMM18,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0x10(%R11),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD 0x10(%RSI),%XMM15,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD231SD %XMM2,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM0,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JB 40bbce <ljForce._omp_fn.1+0x44e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VCOMISD %XMM6,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 40bbce <ljForce._omp_fn.1+0x44e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VDIVSD %XMM0,%XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMULSD %XMM0,%XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM10,%XMM0,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM0,%XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM0,%XMM15,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM9,%XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMSUB132SD %XMM0,%XMM11,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%R8),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%R8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPD %XMM15,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD231SD %XMM8,%XMM15,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD132SD %XMM14,%XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
ADD %R14,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R9,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD (%RBX),%XMM8,%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM23,(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD %XMM15,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM19,%XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFNMADD213SD (%R10),%XMM15,%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFNMADD213SD 0x8(%R10),%XMM15,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM18,(%R10)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VFNMADD213SD 0x10(%R10),%XMM2,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,0x8(%R10)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM15,0x10(%R10)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40bd6f <ljForce._omp_fn.1+0x5ef>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JG 40ba20 <ljForce._omp_fn.1+0x2a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code