OV - exec - Loop 85

	Loop Id: 85	Module: exec	Source: ljForce.c:178-216 [...]	Coverage: 0.28%

0x40b8a6 MOV	(%R9),%R15D

0x40b8a9 TEST	%R15D,%R15D

0x40b8ac JS	40bed0

0x40b8b2 MOVSXD	%R15D,%RBX

0x40b8b5 VMOVQ	%XMM4,%RSI

0x40b8ba VMOVD	%XMM5,%EDI

0x40b8be MOV	(%RSI,%RBX,4),%R8D

0x40b8c2 TEST	%EDI,%EDI

0x40b8c4 JLE	40b9b4

0x40b8ca MOV	%EAX,%R10D

0x40b8cd LEA	(%RBX,%RBX,2),%RDX

0x40b8d1 MOV	%EAX,%R14D

0x40b8d4 MOV	-0x48(%RBP),%RBX

0x40b8d8 NOT	%R10D

0x40b8db SAL	$0x6,%R15D

0x40b8df ADD	%ECX,%R10D

0x40b8e2 LEA	(%R8,%R15,1),%R12D

0x40b8e6 SAL	$0x9,%RDX

0x40b8ea AND	$0x7,%R10D

0x40b8ee TEST	%R8D,%R8D

0x40b8f1 JG	40b9f4

0x40b8f7 MOV	-0x48(%RBP),%R11

0x40b8fb LEA	0x1(%RAX),%R14D

0x40b8ff LEA	0x8(%R11),%RBX

0x40b903 CMP	%ECX,%R14D

0x40b906 JGE	40b9b4

0x40b90c TEST	%R10D,%R10D

0x40b90f JE	40b9a2

0x40b915 CMP	$0x1,%R10D

0x40b919 JE	40b991

0x40b91b CMP	$0x2,%R10D

0x40b91f JE	40b985

0x40b921 CMP	$0x3,%R10D

0x40b925 JE	40b979

0x40b927 CMP	$0x4,%R10D

0x40b92b JE	40b969

0x40b92d CMP	$0x5,%R10D

0x40b931 JE	40b959

0x40b933 CMP	$0x6,%R10D

0x40b937 JE	40b949

0x40b939 TEST	%R8D,%R8D

0x40b93c JG	40b9f4

0x40b942 INC	%R14D

0x40b945 ADD	$0x8,%RBX

0x40b949 TEST	%R8D,%R8D

0x40b94c JG	40b9f4

0x40b952 INC	%R14D

0x40b955 ADD	$0x8,%RBX

0x40b959 TEST	%R8D,%R8D

0x40b95c JG	40b9f4

0x40b962 INC	%R14D

0x40b965 ADD	$0x8,%RBX

0x40b969 TEST	%R8D,%R8D

0x40b96c JG	40b9f4

0x40b972 INC	%R14D

0x40b975 ADD	$0x8,%RBX

0x40b979 TEST	%R8D,%R8D

0x40b97c JG	40b9f4

0x40b97e INC	%R14D

0x40b981 ADD	$0x8,%RBX

0x40b985 TEST	%R8D,%R8D

0x40b988 JG	40b9f4

0x40b98a INC	%R14D

0x40b98d ADD	$0x8,%RBX

0x40b991 TEST	%R8D,%R8D

0x40b994 JG	40b9f4

0x40b996 INC	%R14D

0x40b999 ADD	$0x8,%RBX

0x40b99d CMP	%ECX,%R14D

0x40b9a0 JGE	40b9b4

  (89) 0x40b9a2 TEST	%R8D,%R8D

  (89) 0x40b9a5 JG	40b9f4

  (89) 0x40b9a7 ADD	$0x8,%R14D

  (89) 0x40b9ab ADD	$0x40,%RBX

  (89) 0x40b9af CMP	%ECX,%R14D

  (89) 0x40b9b2 JL	40b9a2

0x40b9b4 ADD	$0x4,%R9

0x40b9b8 CMP	%R9,-0x58(%RBP)

0x40b9bc JNE	40b8a6

0x40b9f4 MOV	-0x50(%RBP),%RSI

0x40b9f8 MOV	%EAX,-0x34(%RBP)

0x40b9fb MOV	%RDX,%RDI

0x40b9fe MOV	%R15D,%EAX

0x40ba01 MOV	%R14D,%R15D

0x40ba04 MOV	%RBX,%R14

0x40ba07 VXORPD	%XMM6,%XMM6,%XMM6

0x40ba0b MOV	%R9,-0x40(%RBP)

0x40ba0f MOV	0x20(%RSI),%R8

0x40ba13 NOPW	%CS:(%RAX,%RAX,1)

0x40ba1e XCHG	%AX,%AX

  (87) 0x40ba20 MOV	0x18(%R8),%RBX

  (87) 0x40ba24 LEA	(%R14,%R14,2),%R9

  (87) 0x40ba28 MOV	%EAX,%R10D

  (87) 0x40ba2b NOT	%R10D

  (87) 0x40ba2e ADD	%R12D,%R10D

  (87) 0x40ba31 AND	$0x1,%R10D

  (87) 0x40ba35 LEA	(%RBX,%R9,1),%R11

  (87) 0x40ba39 ADD	%RDI,%RBX

  (87) 0x40ba3c VMOVSD	(%R11),%XMM15

  (87) 0x40ba41 VMOVSD	0x8(%R11),%XMM1

  (87) 0x40ba47 VSUBSD	(%RBX),%XMM15,%XMM16

  (87) 0x40ba4d VSUBSD	0x8(%RBX),%XMM1,%XMM1

  (87) 0x40ba52 VMULSD	%XMM1,%XMM1,%XMM0

  (87) 0x40ba56 VFMADD231SD	%XMM16,%XMM16,%XMM0

  (87) 0x40ba5c VMOVSD	0x10(%R11),%XMM2

  (87) 0x40ba62 VSUBSD	0x10(%RBX),%XMM2,%XMM2

  (87) 0x40ba67 VFMADD231SD	%XMM2,%XMM2,%XMM0

  (87) 0x40ba6c VCOMISD	%XMM0,%XMM3

  (87) 0x40ba70 JB	40baf7

  (87) 0x40ba76 VCOMISD	%XMM6,%XMM0

  (87) 0x40ba7a JBE	40baf7

  (87) 0x40ba7c VDIVSD	%XMM0,%XMM9,%XMM0

  (87) 0x40ba80 VMULSD	%XMM0,%XMM0,%XMM15

  (87) 0x40ba84 VMULSD	%XMM10,%XMM0,%XMM17

  (87) 0x40ba8a VMULSD	%XMM0,%XMM12,%XMM0

  (87) 0x40ba8e VMULSD	%XMM0,%XMM15,%XMM0

  (87) 0x40ba92 VSUBSD	%XMM9,%XMM0,%XMM15

  (87) 0x40ba97 VFMSUB132SD	%XMM0,%XMM11,%XMM15

  (87) 0x40ba9c MOV	0x30(%R8),%RDX

  (87) 0x40baa0 MOV	0x28(%R8),%RSI

  (87) 0x40baa4 VMOVAPD	%XMM15,%XMM20

  (87) 0x40baaa VFMADD231SD	%XMM8,%XMM15,%XMM7

  (87) 0x40baaf VMOVAPD	%XMM0,%XMM15

  (87) 0x40bab3 VFMADD132SD	%XMM14,%XMM13,%XMM15

  (87) 0x40bab8 ADD	%R14,%RDX

  (87) 0x40babb ADD	%R9,%RSI

  (87) 0x40babe VFMADD213SD	(%RDX),%XMM8,%XMM20

  (87) 0x40bac4 VMOVSD	%XMM20,(%RDX)

  (87) 0x40baca VMULSD	%XMM15,%XMM0,%XMM0

  (87) 0x40bacf VMULSD	%XMM17,%XMM0,%XMM15

  (87) 0x40bad5 VFNMADD213SD	(%RSI),%XMM15,%XMM16

  (87) 0x40badb VFNMADD213SD	0x8(%RSI),%XMM15,%XMM1

  (87) 0x40bae1 VMOVSD	%XMM16,(%RSI)

  (87) 0x40bae7 VFNMADD213SD	0x10(%RSI),%XMM2,%XMM15

  (87) 0x40baed VMOVSD	%XMM1,0x8(%RSI)

  (87) 0x40baf2 VMOVSD	%XMM15,0x10(%RSI)

  (87) 0x40baf7 LEA	0x1(%RAX),%EDX

  (87) 0x40bafa LEA	0x18(%RBX),%RSI

  (87) 0x40bafe CMP	%R12D,%EDX

  (87) 0x40bb01 JGE	40bd6f

  (87) 0x40bb07 TEST	%R10D,%R10D

  (87) 0x40bb0a JE	40bbe0

  (87) 0x40bb10 VMOVSD	(%R11),%XMM1

  (87) 0x40bb15 VMOVSD	0x8(%R11),%XMM2

  (87) 0x40bb1b VSUBSD	0x18(%RBX),%XMM1,%XMM18

  (87) 0x40bb22 VSUBSD	0x8(%RSI),%XMM2,%XMM1

  (87) 0x40bb27 VMULSD	%XMM1,%XMM1,%XMM0

  (87) 0x40bb2b VFMADD231SD	%XMM18,%XMM18,%XMM0

  (87) 0x40bb31 VMOVSD	0x10(%R11),%XMM15

  (87) 0x40bb37 VSUBSD	0x10(%RSI),%XMM15,%XMM2

  (87) 0x40bb3c VFMADD231SD	%XMM2,%XMM2,%XMM0

  (87) 0x40bb41 VCOMISD	%XMM0,%XMM3

  (87) 0x40bb45 JB	40bbce

  (87) 0x40bb4b VCOMISD	%XMM6,%XMM0

  (87) 0x40bb4f JBE	40bbce

  (87) 0x40bb51 VDIVSD	%XMM0,%XMM9,%XMM0

  (87) 0x40bb55 VMULSD	%XMM0,%XMM0,%XMM15

  (87) 0x40bb59 VMULSD	%XMM10,%XMM0,%XMM19

  (87) 0x40bb5f VMULSD	%XMM0,%XMM12,%XMM0

  (87) 0x40bb63 VMULSD	%XMM0,%XMM15,%XMM0

  (87) 0x40bb67 VSUBSD	%XMM9,%XMM0,%XMM15

  (87) 0x40bb6c VFMSUB132SD	%XMM0,%XMM11,%XMM15

  (87) 0x40bb71 MOV	0x30(%R8),%RBX

  (87) 0x40bb75 MOV	0x28(%R8),%R10

  (87) 0x40bb79 VMOVAPD	%XMM15,%XMM23

  (87) 0x40bb7f VFMADD231SD	%XMM8,%XMM15,%XMM7

  (87) 0x40bb84 VMOVAPD	%XMM0,%XMM15

  (87) 0x40bb88 VFMADD132SD	%XMM14,%XMM13,%XMM15

  (87) 0x40bb8d ADD	%R14,%RBX

  (87) 0x40bb90 ADD	%R9,%R10

  (87) 0x40bb93 VFMADD213SD	(%RBX),%XMM8,%XMM23

  (87) 0x40bb99 VMOVSD	%XMM23,(%RBX)

  (87) 0x40bb9f VMULSD	%XMM15,%XMM0,%XMM0

  (87) 0x40bba4 VMULSD	%XMM19,%XMM0,%XMM15

  (87) 0x40bbaa VFNMADD213SD	(%R10),%XMM15,%XMM18

  (87) 0x40bbb0 VFNMADD213SD	0x8(%R10),%XMM15,%XMM1

  (87) 0x40bbb6 VMOVSD	%XMM18,(%R10)

  (87) 0x40bbbc VFNMADD213SD	0x10(%R10),%XMM2,%XMM15

  (87) 0x40bbc2 VMOVSD	%XMM1,0x8(%R10)

  (87) 0x40bbc8 VMOVSD	%XMM15,0x10(%R10)

  (87) 0x40bbce INC	%EDX

  (87) 0x40bbd0 ADD	$0x18,%RSI

  (87) 0x40bbd4 CMP	%R12D,%EDX

  (87) 0x40bbd7 JGE	40bd6f

  (87) 0x40bbdd NOPL	(%RAX)

    (88) 0x40bbe0 VMOVSD	(%R11),%XMM1

    (88) 0x40bbe5 VMOVSD	0x8(%R11),%XMM2

    (88) 0x40bbeb VSUBSD	(%RSI),%XMM1,%XMM24

    (88) 0x40bbf1 VSUBSD	0x8(%RSI),%XMM2,%XMM1

    (88) 0x40bbf6 VMULSD	%XMM1,%XMM1,%XMM0

    (88) 0x40bbfa VFMADD231SD	%XMM24,%XMM24,%XMM0

    (88) 0x40bc00 VMOVSD	0x10(%R11),%XMM15

    (88) 0x40bc06 VSUBSD	0x10(%RSI),%XMM15,%XMM2

    (88) 0x40bc0b VFMADD231SD	%XMM2,%XMM2,%XMM0

    (88) 0x40bc10 VCOMISD	%XMM0,%XMM3

    (88) 0x40bc14 JB	40bc9d

    (88) 0x40bc1a VCOMISD	%XMM6,%XMM0

    (88) 0x40bc1e JBE	40bc9d

    (88) 0x40bc20 VDIVSD	%XMM0,%XMM9,%XMM0

    (88) 0x40bc24 VMULSD	%XMM0,%XMM0,%XMM15

    (88) 0x40bc28 VMULSD	%XMM10,%XMM0,%XMM25

    (88) 0x40bc2e VMULSD	%XMM0,%XMM12,%XMM0

    (88) 0x40bc32 VMULSD	%XMM0,%XMM15,%XMM0

    (88) 0x40bc36 VSUBSD	%XMM9,%XMM0,%XMM15

    (88) 0x40bc3b VFMSUB132SD	%XMM0,%XMM11,%XMM15

    (88) 0x40bc40 MOV	0x30(%R8),%RBX

    (88) 0x40bc44 MOV	0x28(%R8),%R10

    (88) 0x40bc48 VMOVAPD	%XMM15,%XMM26

    (88) 0x40bc4e VFMADD231SD	%XMM8,%XMM15,%XMM7

    (88) 0x40bc53 VMOVAPD	%XMM0,%XMM15

    (88) 0x40bc57 VFMADD132SD	%XMM14,%XMM13,%XMM15

    (88) 0x40bc5c ADD	%R14,%RBX

    (88) 0x40bc5f ADD	%R9,%R10

    (88) 0x40bc62 VFMADD213SD	(%RBX),%XMM8,%XMM26

    (88) 0x40bc68 VMOVSD	%XMM26,(%RBX)

    (88) 0x40bc6e VMULSD	%XMM15,%XMM0,%XMM0

    (88) 0x40bc73 VMULSD	%XMM25,%XMM0,%XMM15

    (88) 0x40bc79 VFNMADD213SD	(%R10),%XMM15,%XMM24

    (88) 0x40bc7f VFNMADD213SD	0x8(%R10),%XMM15,%XMM1

    (88) 0x40bc85 VMOVSD	%XMM24,(%R10)

    (88) 0x40bc8b VFNMADD213SD	0x10(%R10),%XMM2,%XMM15

    (88) 0x40bc91 VMOVSD	%XMM1,0x8(%R10)

    (88) 0x40bc97 VMOVSD	%XMM15,0x10(%R10)

    (88) 0x40bc9d VMOVSD	(%R11),%XMM1

    (88) 0x40bca2 VMOVSD	0x8(%R11),%XMM2

    (88) 0x40bca8 VSUBSD	0x18(%RSI),%XMM1,%XMM27

    (88) 0x40bcaf VSUBSD	0x20(%RSI),%XMM2,%XMM1

    (88) 0x40bcb4 VMULSD	%XMM1,%XMM1,%XMM0

    (88) 0x40bcb8 VFMADD231SD	%XMM27,%XMM27,%XMM0

    (88) 0x40bcbe VMOVSD	0x10(%R11),%XMM15

    (88) 0x40bcc4 VSUBSD	0x28(%RSI),%XMM15,%XMM15

    (88) 0x40bcc9 INC	%EDX

    (88) 0x40bccb LEA	0x18(%RSI),%RBX

    (88) 0x40bccf VFMADD231SD	%XMM15,%XMM15,%XMM0

    (88) 0x40bcd4 VCOMISD	%XMM0,%XMM3

    (88) 0x40bcd8 JB	40bd60

    (88) 0x40bcde VCOMISD	%XMM6,%XMM0

    (88) 0x40bce2 JBE	40bd60

    (88) 0x40bce4 VDIVSD	%XMM0,%XMM9,%XMM0

    (88) 0x40bce8 VMULSD	%XMM0,%XMM0,%XMM2

    (88) 0x40bcec VMULSD	%XMM10,%XMM0,%XMM28

    (88) 0x40bcf2 VMULSD	%XMM0,%XMM12,%XMM0

    (88) 0x40bcf6 VMULSD	%XMM0,%XMM2,%XMM0

    (88) 0x40bcfa VSUBSD	%XMM9,%XMM0,%XMM2

    (88) 0x40bcff VFMSUB132SD	%XMM0,%XMM11,%XMM2

    (88) 0x40bd04 MOV	0x30(%R8),%RSI

    (88) 0x40bd08 MOV	0x28(%R8),%R10

    (88) 0x40bd0c VMOVAPD	%XMM2,%XMM29

    (88) 0x40bd12 VFMADD231SD	%XMM8,%XMM2,%XMM7

    (88) 0x40bd17 VMOVAPD	%XMM0,%XMM2

    (88) 0x40bd1b VFMADD132SD	%XMM14,%XMM13,%XMM2

    (88) 0x40bd20 ADD	%R14,%RSI

    (88) 0x40bd23 ADD	%R9,%R10

    (88) 0x40bd26 VFMADD213SD	(%RSI),%XMM8,%XMM29

    (88) 0x40bd2c VMOVSD	%XMM29,(%RSI)

    (88) 0x40bd32 VMULSD	%XMM2,%XMM0,%XMM0

    (88) 0x40bd36 VMULSD	%XMM28,%XMM0,%XMM2

    (88) 0x40bd3c VFNMADD213SD	(%R10),%XMM2,%XMM27

    (88) 0x40bd42 VFNMADD213SD	0x8(%R10),%XMM2,%XMM1

    (88) 0x40bd48 VMOVSD	%XMM27,(%R10)

    (88) 0x40bd4e VFNMADD213SD	0x10(%R10),%XMM15,%XMM2

    (88) 0x40bd54 VMOVSD	%XMM1,0x8(%R10)

    (88) 0x40bd5a VMOVSD	%XMM2,0x10(%R10)

    (88) 0x40bd60 INC	%EDX

    (88) 0x40bd62 LEA	0x18(%RBX),%RSI

    (88) 0x40bd66 CMP	%R12D,%EDX

    (88) 0x40bd69 JL	40bbe0

  (87) 0x40bd6f INC	%R15D

  (87) 0x40bd72 ADD	$0x8,%R14

  (87) 0x40bd76 CMP	%R15D,%ECX

  (87) 0x40bd79 JG	40ba20

0x40bd7f MOV	-0x40(%RBP),%R9

0x40bd83 MOV	-0x34(%RBP),%EAX

0x40bd86 ADD	$0x4,%R9

0x40bd8a CMP	%R9,-0x58(%RBP)

0x40bd8e JNE	40b8a6

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 178 - 216

--------------------------------------------------------------------------------

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module
►97.01+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.60+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	ljForce	ljForce.c:172	exec
○	timestep	timestep.c:51	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	15.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P0, P1, P2, P3, P4, P5,
Function	ljForce._omp_fn.1
Source	ljForce.c:178-184,ljForce.c:187-187,ljForce.c:191-191,ljForce.c:201-201
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.17
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	11.17
CQA cycles if fully vectorized	0.72
Front-end cycles	10.75
P0 cycles	11.17
P1 cycles	11.17
P2 cycles	11.17
P3 cycles	11.17
P4 cycles	11.17
P5 cycles	11.17
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	89.00
Nb uops	86.00
Nb loads	10.00
Nb stores	2.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.16
Bytes prefetched	0.00
Bytes loaded	68.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	2.50
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	3.33
Vector-efficiency ratio all	7.66
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	7.92

Metric	Value
CQA speedup if no scalar integer	1.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	15.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P0, P1, P2, P3, P4, P5,
Function	ljForce._omp_fn.1
Source	ljForce.c:178-184,ljForce.c:187-187,ljForce.c:191-191,ljForce.c:201-201
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.17
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	11.17
CQA cycles if fully vectorized	0.72
Front-end cycles	10.75
P0 cycles	11.17
P1 cycles	11.17
P2 cycles	11.17
P3 cycles	11.17
P4 cycles	11.17
P5 cycles	11.17
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	89.00
Nb uops	86.00
Nb loads	10.00
Nb stores	2.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.16
Bytes prefetched	0.00
Bytes loaded	68.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	2.50
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	3.33
Vector-efficiency ratio all	7.66
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	7.92

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:178-216
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-191,197-216.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-184,187,191,201.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 4457 paths individually, rerun with max-paths=4457
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 4457 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.17 to 7.00 cycles (1.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.17 to 0.72 cycles (15.54x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 68 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	89
nb uops	86
loop length	331
used x86 registers	14
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.75 cycles
front end	10.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	11.17	11.17	11.17	11.17	11.17	11.17	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	1.00	1.00
cycles	11.17	11.17	11.17	11.17	11.17	11.17	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.75
Dispatch	11.17
Overall L1	11.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

Vector efficiency ratios

INT

all	7%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	7%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.17 cycles. At this rate:

2% of peak load performance is reached (6.09 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.07 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40b8a6

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
MOV (%R9),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
TEST %R15D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JS 40bed0 <ljForce._omp_fn.1+0x750>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD %R15D,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM4,%RSI	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVD %XMM5,%EDI	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	scal (6.3%)
MOV (%RSI,%RBX,4),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
TEST %EDI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40b9b4 <ljForce._omp_fn.1+0x234>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA (%RBX,%RBX,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0x48(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
NOT %R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x6,%R15D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
ADD %ECX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA (%R8,%R15,1),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
SAL $0x9,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
AND $0x7,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b9f4 <ljForce._omp_fn.1+0x274>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x48(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA 0x1(%RAX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(%R11),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
CMP %ECX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40b9b4 <ljForce._omp_fn.1+0x234>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
TEST %R10D,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40b9a2 <ljForce._omp_fn.1+0x222>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40b991 <ljForce._omp_fn.1+0x211>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40b985 <ljForce._omp_fn.1+0x205>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40b979 <ljForce._omp_fn.1+0x1f9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40b969 <ljForce._omp_fn.1+0x1e9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40b959 <ljForce._omp_fn.1+0x1d9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40b949 <ljForce._omp_fn.1+0x1c9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b9f4 <ljForce._omp_fn.1+0x274>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b9f4 <ljForce._omp_fn.1+0x274>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b9f4 <ljForce._omp_fn.1+0x274>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b9f4 <ljForce._omp_fn.1+0x274>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b9f4 <ljForce._omp_fn.1+0x274>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b9f4 <ljForce._omp_fn.1+0x274>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b9f4 <ljForce._omp_fn.1+0x274>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %ECX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40b9b4 <ljForce._omp_fn.1+0x234>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,-0x58(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JNE 40b8a6 <ljForce._omp_fn.1+0x126>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x50(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %EAX,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VXORPD %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R9,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RSI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x40(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x34(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD $0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,-0x58(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
JNE 40b8a6 <ljForce._omp_fn.1+0x126>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:178-216
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 4457 paths individually, rerun with max-paths=4457
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.17 to 7.00 cycles (1.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 68 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	89
nb uops	86
loop length	331
used x86 registers	14
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.75 cycles
front end	10.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	11.17	11.17	11.17	11.17	11.17	11.17	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	1.00	1.00
cycles	11.17	11.17	11.17	11.17	11.17	11.17	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.75
Dispatch	11.17
Overall L1	11.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

Vector efficiency ratios

INT

all	7%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	7%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.17 cycles. At this rate:

2% of peak load performance is reached (6.09 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.07 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40b8a6

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
MOV (%R9),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
TEST %R15D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JS 40bed0 <ljForce._omp_fn.1+0x750>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD %R15D,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM4,%RSI	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVD %XMM5,%EDI	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	scal (6.3%)
MOV (%RSI,%RBX,4),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
TEST %EDI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40b9b4 <ljForce._omp_fn.1+0x234>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA (%RBX,%RBX,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0x48(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
NOT %R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x6,%R15D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
ADD %ECX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA (%R8,%R15,1),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
SAL $0x9,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
AND $0x7,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b9f4 <ljForce._omp_fn.1+0x274>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x48(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA 0x1(%RAX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(%R11),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
CMP %ECX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40b9b4 <ljForce._omp_fn.1+0x234>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
TEST %R10D,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40b9a2 <ljForce._omp_fn.1+0x222>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40b991 <ljForce._omp_fn.1+0x211>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40b985 <ljForce._omp_fn.1+0x205>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40b979 <ljForce._omp_fn.1+0x1f9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40b969 <ljForce._omp_fn.1+0x1e9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40b959 <ljForce._omp_fn.1+0x1d9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40b949 <ljForce._omp_fn.1+0x1c9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b9f4 <ljForce._omp_fn.1+0x274>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b9f4 <ljForce._omp_fn.1+0x274>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b9f4 <ljForce._omp_fn.1+0x274>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b9f4 <ljForce._omp_fn.1+0x274>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b9f4 <ljForce._omp_fn.1+0x274>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b9f4 <ljForce._omp_fn.1+0x274>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b9f4 <ljForce._omp_fn.1+0x274>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %ECX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40b9b4 <ljForce._omp_fn.1+0x234>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,-0x58(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JNE 40b8a6 <ljForce._omp_fn.1+0x126>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x50(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %EAX,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VXORPD %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R9,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RSI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x40(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x34(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD $0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,-0x58(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
JNE 40b8a6 <ljForce._omp_fn.1+0x126>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code