OV - exec - Loop 63

	Loop Id: 63	Module: exec	Source: initAtoms.c:221-228	Coverage: 0.02%

0x4091d9 MOVSXD	(%RDI),%R11    [4]

0x4091dc MOVSXD	0x4(%RDI),%RDX    [4]

0x4091e0 MOVSXD	0x8(%RDI),%RCX    [4]

0x4091e4 ADD	$0x10,%RDI

0x4091e8 VADDSD	(%RAX),%XMM3,%XMM4    [2]

0x4091ec VADDSD	0x8(%RAX),%XMM2,%XMM5    [2]

0x4091f1 VADDSD	0x10(%RAX),%XMM1,%XMM6    [2]

0x4091f6 VADDSD	0x18(%RAX),%XMM4,%XMM8    [2]

0x4091fb VADDSD	0x20(%RAX),%XMM5,%XMM9    [2]

0x409200 VADDSD	0x28(%RAX),%XMM6,%XMM10    [2]

0x409205 VADDSD	0x30(%RAX),%XMM8,%XMM12    [2]

0x40920a VADDSD	0x38(%RAX),%XMM9,%XMM13    [2]

0x40920f VADDSD	0x40(%RAX),%XMM10,%XMM14    [2]

0x409214 VADDSD	0x48(%RAX),%XMM12,%XMM3    [2]

0x409219 VADDSD	0x50(%RAX),%XMM13,%XMM2    [2]

0x40921e VADDSD	0x58(%RAX),%XMM14,%XMM1    [2]

0x409223 ADD	$0x60,%RAX

0x409227 SAL	$0x4,%R11

0x40922b VADDSD	0x8(%R9,%R11,1),%XMM0,%XMM7    [1]

0x409232 MOVSXD	-0x4(%RDI),%R11    [3]

0x409236 SAL	$0x4,%RDX

0x40923a SAL	$0x4,%RCX

0x40923e VADDSD	0x8(%R9,%RDX,1),%XMM7,%XMM11    [1]

0x409245 SAL	$0x4,%R11

0x409249 VADDSD	0x8(%R9,%RCX,1),%XMM11,%XMM15    [1]

0x409250 VADDSD	0x8(%R9,%R11,1),%XMM15,%XMM0    [1]

0x409257 CMP	%RDI,%R10

0x40925a JNE	4091d9

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 221 - 228

--------------------------------------------------------------------------------

221:       for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff)

222:       {

223:          v0 += s->atoms->p[iOff][0];

224:          v1 += s->atoms->p[iOff][1];

225:          v2 += s->atoms->p[iOff][2];

226:

227:          int iSpecies = s->atoms->iSpecies[iOff];

228:          v3 += s->species[iSpecies].mass;

Coverage (%)	Name	Source Location	Module
►98.41+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.59+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	setVcm	initAtoms.c:218	exec
○	setTemperature	initAtoms.c:170	exec
○	main	CoMD.c:200	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:468	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.94
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P12, P13,
Function	computeVcm._omp_fn.0
Source	initAtoms.c:221-228
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	4.13
CQA cycles if fully vectorized	1.00
Front-end cycles	3.38
P0 cycles	1.83
P1 cycles	1.83
P2 cycles	1.83
P3 cycles	1.83
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	27.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	1.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.94
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P12, P13,
Function	computeVcm._omp_fn.0
Source	initAtoms.c:221-228
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	4.13
CQA cycles if fully vectorized	1.00
Front-end cycles	3.38
P0 cycles	1.83
P1 cycles	1.83
P2 cycles	1.83
P3 cycles	1.83
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	27.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	1.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	computeVcm._omp_fn.0
Source file and lines	initAtoms.c:221-228
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:221-228.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 1.00 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP add operations (the FP add unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.00 to 5.00 cycles (1.60x speedup).

Workaround

Reduce the number of FP add instructions

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

16 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

16: addition or subtraction

The binary loop is loading 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	28
nb uops	27
loop length	135
used x86 registers	7
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.38 cycles
front end	3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.83	1.83	1.83	1.83	1.83	1.83	5.00	5.00	5.00	5.00	0.00	0.00	8.00	8.00	0.00	0.00
cycles	1.83	1.83	1.83	1.83	1.83	1.83	5.00	5.00	5.00	5.00	0.00	0.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	3.38
Dispatch	8.00
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

7% of peak load performance is reached (18.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4091d9

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	Latency	Recip. throughput	Vectorization
MOVSXD (%RDI),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
MOVSXD 0x4(%RDI),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
MOVSXD 0x8(%RDI),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
ADD $0x10,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VADDSD (%RAX),%XMM3,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x8(%RAX),%XMM2,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x10(%RAX),%XMM1,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x18(%RAX),%XMM4,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x20(%RAX),%XMM5,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x28(%RAX),%XMM6,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x30(%RAX),%XMM8,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x38(%RAX),%XMM9,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x40(%RAX),%XMM10,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x48(%RAX),%XMM12,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x50(%RAX),%XMM13,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x58(%RAX),%XMM14,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
ADD $0x60,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VADDSD 0x8(%R9,%R11,1),%XMM0,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
MOVSXD -0x4(%RDI),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
SAL $0x4,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
SAL $0x4,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VADDSD 0x8(%R9,%RDX,1),%XMM7,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
SAL $0x4,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VADDSD 0x8(%R9,%RCX,1),%XMM11,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x8(%R9,%R11,1),%XMM15,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
CMP %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JNE 4091d9 <computeVcm._omp_fn.0+0x159>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Function	computeVcm._omp_fn.0
Source file and lines	initAtoms.c:221-228
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 1.00 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of FP add instructions

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

16 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

16: addition or subtraction

The binary loop is loading 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	28
nb uops	27
loop length	135
used x86 registers	7
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.38 cycles
front end	3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.83	1.83	1.83	1.83	1.83	1.83	5.00	5.00	5.00	5.00	0.00	0.00	8.00	8.00	0.00	0.00
cycles	1.83	1.83	1.83	1.83	1.83	1.83	5.00	5.00	5.00	5.00	0.00	0.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	3.38
Dispatch	8.00
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

7% of peak load performance is reached (18.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4091d9

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	Latency	Recip. throughput	Vectorization
MOVSXD (%RDI),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
MOVSXD 0x4(%RDI),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
MOVSXD 0x8(%RDI),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
ADD $0x10,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VADDSD (%RAX),%XMM3,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x8(%RAX),%XMM2,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x10(%RAX),%XMM1,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x18(%RAX),%XMM4,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x20(%RAX),%XMM5,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x28(%RAX),%XMM6,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x30(%RAX),%XMM8,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x38(%RAX),%XMM9,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x40(%RAX),%XMM10,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x48(%RAX),%XMM12,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x50(%RAX),%XMM13,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x58(%RAX),%XMM14,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
ADD $0x60,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VADDSD 0x8(%R9,%R11,1),%XMM0,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
MOVSXD -0x4(%RDI),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
SAL $0x4,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
SAL $0x4,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VADDSD 0x8(%R9,%RDX,1),%XMM7,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
SAL $0x4,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VADDSD 0x8(%R9,%RCX,1),%XMM11,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
VADDSD 0x8(%R9,%R11,1),%XMM15,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
CMP %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JNE 4091d9 <computeVcm._omp_fn.0+0x159>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

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Vectorization

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Execution units bottlenecks

Workaround

Slow data structures access

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

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General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code