OV - exec - Loop 103

	Loop Id: 103	Module: exec	Source: timestep.c:110-116	Coverage: 0.11%

0x40ef30 VMOVSD	(%RAX),%XMM4    [3]

0x40ef34 VMOVSD	0x8(%RAX),%XMM2    [3]

0x40ef39 VMULSD	%XMM2,%XMM2,%XMM5

0x40ef3d VFMADD231SD	%XMM4,%XMM4,%XMM5

0x40ef42 MOVSXD	(%RDX),%R14    [5]

0x40ef45 VMOVSD	0x10(%RAX),%XMM6    [3]

0x40ef4a VMOVSD	0x20(%RAX),%XMM8    [3]

0x40ef4f VMULSD	%XMM8,%XMM8,%XMM9

0x40ef54 MOVSXD	0x4(%RDX),%RSI    [5]

0x40ef58 VMOVSD	0x28(%RAX),%XMM10    [3]

0x40ef5d VMOVSD	0x30(%RAX),%XMM12    [3]

0x40ef62 VMOVSD	0x38(%RAX),%XMM13    [3]

0x40ef67 VMULSD	%XMM13,%XMM13,%XMM14

0x40ef6c VFMADD231SD	%XMM12,%XMM12,%XMM14

0x40ef71 MOVSXD	0x8(%RDX),%RCX    [5]

0x40ef75 VMOVSD	0x40(%RAX),%XMM15    [3]

0x40ef7a VFMADD132SD	%XMM6,%XMM5,%XMM6

0x40ef7f VMOVSD	0x48(%RAX),%XMM2    [3]

0x40ef84 VMOVSD	0x50(%RAX),%XMM1    [3]

0x40ef89 VMULSD	%XMM1,%XMM1,%XMM5

0x40ef8d VFMADD231SD	%XMM2,%XMM2,%XMM5

0x40ef92 ADD	$0x10,%RDX

0x40ef96 ADD	$0x60,%RAX

0x40ef9a SAL	$0x4,%R14

0x40ef9e VFMADD132SD	%XMM15,%XMM14,%XMM15

0x40efa3 VDIVSD	0x8(%RDI,%R14,1),%XMM3,%XMM7    [1]

0x40efaa VFMADD132SD	%XMM6,%XMM0,%XMM7

0x40efaf VMOVSD	-0x48(%RAX),%XMM0    [2]

0x40efb4 VFMADD231SD	%XMM0,%XMM0,%XMM9

0x40efb9 SAL	$0x4,%RSI

0x40efbd VMOVSD	-0x8(%RAX),%XMM0    [2]

0x40efc2 VFMADD132SD	%XMM0,%XMM5,%XMM0

0x40efc7 VDIVSD	0x8(%RDI,%RSI,1),%XMM3,%XMM11    [1]

0x40efcd MOVSXD	-0x4(%RDX),%R14    [4]

0x40efd1 VFMADD132SD	%XMM10,%XMM9,%XMM10

0x40efd6 SAL	$0x4,%RCX

0x40efda VDIVSD	0x8(%RDI,%RCX,1),%XMM3,%XMM4    [1]

0x40efe0 VFMADD132SD	%XMM10,%XMM7,%XMM11

0x40efe5 SAL	$0x4,%R14

0x40efe9 VDIVSD	0x8(%RDI,%R14,1),%XMM3,%XMM6    [1]

0x40eff0 VFMADD132SD	%XMM15,%XMM11,%XMM4

0x40eff5 VFMADD132SD	%XMM6,%XMM4,%XMM0

0x40effa CMP	%RDX,%R11

0x40effd JNE	40ef30

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 110 - 116

--------------------------------------------------------------------------------

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

Coverage (%)	Name	Source Location	Module
►97.02+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.96+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	kineticEnergy	timestep.c:123	exec
○	timestep	timestep.c:60	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.48
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P10, P11,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-116
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	6.45
CQA cycles if fully vectorized	2.00
Front-end cycles	5.38
P0 cycles	1.83
P1 cycles	1.83
P2 cycles	1.83
P3 cycles	1.83
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	10.00
P11 cycles	10.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	43.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	0.00
Nb FLOP mul	4.00
Nb FLOP fma	12.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.48
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P10, P11,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-116
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	6.45
CQA cycles if fully vectorized	2.00
Front-end cycles	5.38
P0 cycles	1.83
P1 cycles	1.83
P2 cycles	1.83
P3 cycles	1.83
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	10.00
P11 cycles	10.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	43.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	0.00
Nb FLOP mul	4.00
Nb FLOP fma	12.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-116
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-116.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 16.00 to 2.00 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.00 to 10.00 cycles (1.60x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

FMA

Detected 12 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

20 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
16: multiply (12 inside FMA instructions)
4: divide

The binary loop is loading 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	44
nb uops	43
loop length	211
used x86 registers	7
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.38 cycles
front end	5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.83	1.83	1.83	1.83	1.83	1.83	5.00	5.00	5.00	5.00	10.00	10.00	0.00	0.00	0.00	0.00
cycles	1.83	1.83	1.83	1.83	1.83	1.83	5.00	5.00	5.00	5.00	10.00	10.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	5.38
Dispatch	10.00
DIV/SQRT	16.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

3% of peak load performance is reached (9.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40ef30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSD (%RAX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM2,%XMM2,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM4,%XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
MOVSXD (%RDX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x10(%RAX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x20(%RAX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM8,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
MOVSXD 0x4(%RDX),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x28(%RAX),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x30(%RAX),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x38(%RAX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM13,%XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM12,%XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
MOVSXD 0x8(%RDX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x40(%RAX),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VFMADD132SD %XMM6,%XMM5,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VMOVSD 0x48(%RAX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x50(%RAX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM2,%XMM2,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
ADD $0x10,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x60,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VFMADD132SD %XMM15,%XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VDIVSD 0x8(%RDI,%R14,1),%XMM3,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD132SD %XMM6,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VMOVSD -0x48(%RAX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VFMADD231SD %XMM0,%XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VMOVSD -0x8(%RAX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VFMADD132SD %XMM0,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VDIVSD 0x8(%RDI,%RSI,1),%XMM3,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
MOVSXD -0x4(%RDX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VFMADD132SD %XMM10,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RDI,%RCX,1),%XMM3,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD132SD %XMM10,%XMM7,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RDI,%R14,1),%XMM3,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD132SD %XMM15,%XMM11,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VFMADD132SD %XMM6,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
CMP %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JNE 40ef30 <kineticEnergy._omp_fn.0+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-116
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-116.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 16.00 to 2.00 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

FMA

Detected 12 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

20 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
16: multiply (12 inside FMA instructions)
4: divide

The binary loop is loading 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	44
nb uops	43
loop length	211
used x86 registers	7
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.38 cycles
front end	5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.83	1.83	1.83	1.83	1.83	1.83	5.00	5.00	5.00	5.00	10.00	10.00	0.00	0.00	0.00	0.00
cycles	1.83	1.83	1.83	1.83	1.83	1.83	5.00	5.00	5.00	5.00	10.00	10.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	5.38
Dispatch	10.00
DIV/SQRT	16.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

3% of peak load performance is reached (9.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40ef30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSD (%RAX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM2,%XMM2,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM4,%XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
MOVSXD (%RDX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x10(%RAX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x20(%RAX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM8,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
MOVSXD 0x4(%RDX),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x28(%RAX),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x30(%RAX),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x38(%RAX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM13,%XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM12,%XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
MOVSXD 0x8(%RDX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x40(%RAX),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VFMADD132SD %XMM6,%XMM5,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VMOVSD 0x48(%RAX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x50(%RAX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM2,%XMM2,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
ADD $0x10,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x60,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VFMADD132SD %XMM15,%XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VDIVSD 0x8(%RDI,%R14,1),%XMM3,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD132SD %XMM6,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VMOVSD -0x48(%RAX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VFMADD231SD %XMM0,%XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VMOVSD -0x8(%RAX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VFMADD132SD %XMM0,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VDIVSD 0x8(%RDI,%RSI,1),%XMM3,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
MOVSXD -0x4(%RDX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VFMADD132SD %XMM10,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RDI,%RCX,1),%XMM3,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD132SD %XMM10,%XMM7,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RDI,%R14,1),%XMM3,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD132SD %XMM15,%XMM11,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VFMADD132SD %XMM6,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
CMP %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JNE 40ef30 <kineticEnergy._omp_fn.0+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code